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Bibliographies thématiques / Network-on-chip, Dataflow Computing, Performance, Framework / Articles de revues

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Articles de revues sur le sujet « Network-on-chip, Dataflow Computing, Performance, Framework »

Auteur : Grafiati

Publié le 14 mars 2023

Mis à jour le 31 juillet 2025

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1

Alam, Shahanur, Chris Yakopcic, Qing Wu, Mark Barnell, Simon Khan, and Tarek M. Taha. "Survey of Deep Learning Accelerators for Edge and Emerging Computing." Electronics 13, no. 15 (2024): 2988. http://dx.doi.org/10.3390/electronics13152988.

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The unprecedented progress in artificial intelligence (AI), particularly in deep learning algorithms with ubiquitous internet connected smart devices, has created a high demand for AI computing on the edge devices. This review studied commercially available edge processors, and the processors that are still in industrial research stages. We categorized state-of-the-art edge processors based on the underlying architecture, such as dataflow, neuromorphic, and processing in-memory (PIM) architecture. The processors are analyzed based on their performance, chip area, energy efficiency, and applica

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Fang, Juan, Sitong Liu, Shijian Liu, Yanjin Cheng, and Lu Yu. "Hybrid Network-on-Chip: An Application-Aware Framework for Big Data." Complexity 2018 (July 30, 2018): 1–11. http://dx.doi.org/10.1155/2018/1040869.

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Burst growing IoT and cloud computing demand exascale computing systems with high performance and low power consumption to process massive amounts of data. Modern system platforms based on fundamental requirements encounter a performance gap in chasing exponential growth in data speed and amount. To narrow the gap, a heterogamous design gives us a hint. A network-on-chip (NoC) introduces a packet-switched fabric for on-chip communication and becomes the de facto many-core interconnection mechanism; it refers to a vital shared resource for multifarious applications which will notably affect sys

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Muhsen, Yousif, Nor Azura Husin, Maslina Binti Zolkepli, Noridayu Manshor, Ahmed Abbas Jasim Al-Hchaimi, and A. S. Albahri. "Routing Techniques in Network-On-Chip Based Multiprocessor-System-on-Chip for IOT: A Systematic Review." Iraqi Journal For Computer Science and Mathematics 5, no. 1 (2024): 181–204. http://dx.doi.org/10.52866/ijcsm.2024.05.01.014.

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Routing techniques (RTs) play a critical role in modern computing systems that use network-on-chip (NoC) communication infrastructure within multiprocessor system-on-chip (MPSoC) platforms. RTs contribute greatly to the successful performance of NoC-based MPSoCs due to traffic congestion avoidance, quality-of-service assurance, fault handling and optimisation of power usage. This paper outlines our efforts to catalogue RTs, limitations, recommendations and key challenges associated with these RTs used in NoC-based MPSoC systems for the IoT domain. We utilized the PRISMA method to collect data

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Lin, Yanru, Yanjun Zhang, and Xu Yang. "A Low Memory Requirement MobileNets Accelerator Based on FPGA for Auxiliary Medical Tasks." Bioengineering 10, no. 1 (2022): 28. http://dx.doi.org/10.3390/bioengineering10010028.

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Convolutional neural networks (CNNs) have been widely applied in the fields of medical tasks because they can achieve high accuracy in many fields using a large number of parameters and operations. However, many applications designed for auxiliary checks or help need to be deployed into portable devices, where the huge number of operations and parameters of a standard CNN can become an obstruction. MobileNet adopts a depthwise separable convolution to replace the standard convolution, which can greatly reduce the number of operations and parameters while maintaining a relatively high accuracy.

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Sowmya B J and Dr Jamuna S. "Design of Area Efficient Network-On-Chip Router: A Comprehensive Review." International Research Journal on Advanced Engineering Hub (IRJAEH) 2, no. 07 (2024): 1895–908. http://dx.doi.org/10.47392/irjaeh.2024.0260.

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The number of uses for cutting-edge technologies has led to a further growth in a single chip's computational capacity. In this case, several applications want to build on a single chip for computing resources. As a result, connecting the IP cores becomes yet another difficult chore. The many-core System-On-Chips (SoCs) are being replaced by Network-On-Chip (NoC) as an on-chip connectivity option. As a result, the Network on Chip was created as a cutting-edge framework for those networks inside the System on Chip. Modern multiprocessor architectures would benefit more from a NoC architecture a

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Qi, Shengrong, Zekang Fan, Zhongzhen Sun, and Kefeng Ji. "Ship Target Detection in SAR Images Based on Improved YOLOv5 and Edge Deployment on Huawei Ascend." Journal of Physics: Conference Series 3055, no. 1 (2025): 012048. https://doi.org/10.1088/1742-6596/3055/1/012048.

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Abstract Aiming at the challenges faced in ship target detection in complex large scenes of spaceborne SAR images, such as difficulties in detecting small targets, severe target occlusion, large amounts of SAR data, and limited computing power of airborne/spaceborne computing units, this paper proposes a lightweight ship detection model based on the improved YOLOv5 and realizes the edge deployment of the algorithm in combination with the Huawei Ascend hardware platform. The main contributions include: 1) Rotating target detection framework: By introducing an angle classification head, the prob

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Sabah, Yousri. "Quantum-Inspired Temporal Synchronization in Dynamic Mesh Networks: A Non-Local Approach to Latency Optimization." Wasit Journal for Pure sciences 4, no. 1 (2025): 86–93. https://doi.org/10.31185/wjps.710.

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This paper presents a novel method for achieving temporal synchronization in Network-on-Chip (NoC) architectures, using optimization techniques derived from quantum mechanics. We provide a non-local temporal coordination framework to optimize network latency in dynamic mesh networks using quantum principles such as entanglement and superposition. A specialized router design using quantum-inspired control units incorporates the Quantum-Inspired Temporal Coordination Algorithm (QTCA) and Non-Local State Synchronization Protocol (NSSP), which are essential components of the proposed architecture.

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Sheng, Huayi, and Muhammad Shemyal Nisar. "Simulating an Integrated Photonic Image Classifier for Diffractive Neural Networks." Micromachines 15, no. 1 (2023): 50. http://dx.doi.org/10.3390/mi15010050.

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The slowdown of Moore’s law and the existence of the “von Neumann bottleneck” has led to electronic-based computing systems under von Neumann’s architecture being unable to meet the fast-growing demand for artificial intelligence computing. However, all-optical diffractive neural networks provide a possible solution to this challenge. They can outperform conventional silicon-based electronic neural networks due to the significantly higher speed of the propagation of optical signals (≈108 m.s−1) compared to electrical signals (≈105 m.s−1), their parallelism in nature, and their low power consum

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Apoorva, Reddy Proddutoori. "Optimistic Workload Configuration of Parallel Matrices On CPU." European Journal of Advances in Engineering and Technology 8, no. 8 (2021): 66–70. https://doi.org/10.5281/zenodo.12770771.

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This study compares and uses different feature parallelization techniques Fast Fourier Transform (FFT) and Discrete Wavelet Transform (DWT) for classification of matrices. Convolutional Neural Network (CNN) is used to determine the classifications. In the classification, CNN is a unique technique that can be effectively used as a classifier. This study helps to extract features in the most efficient way with less computing time in real life. The framework provides comprehensive and flexible APIs that enable efficient implementation of multi-threaded applications. To meet the real-time performa

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Sui, Xuefu, Qunbo Lv, Liangjie Zhi, et al. "A Hardware-Friendly High-Precision CNN Pruning Method and Its FPGA Implementation." Sensors 23, no. 2 (2023): 824. http://dx.doi.org/10.3390/s23020824.

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To address the problems of large storage requirements, computational pressure, untimely data supply of off-chip memory, and low computational efficiency during hardware deployment due to the large number of convolutional neural network (CNN) parameters, we developed an innovative hardware-friendly CNN pruning method called KRP, which prunes the convolutional kernel on a row scale. A new retraining method based on LR tracking was used to obtain a CNN model with both a high pruning rate and accuracy. Furthermore, we designed a high-performance convolutional computation module on the FPGA platfor

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Chen, Hui, Zihao Zhang, Peng Chen, Xiangzhong Luo, Shiqing Li, and Weichen Liu. "MARCO: A High-performance Task M apping a nd R outing Co -optimization Framework for Point-to-Point NoC-based Heterogeneous Computing Systems." ACM Transactions on Embedded Computing Systems 20, no. 5s (2021): 1–21. http://dx.doi.org/10.1145/3476985.

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Heterogeneous computing systems (HCSs), which consist of various processing elements (PEs) that vary in their processing ability, are usually facilitated by the network-on-chip (NoC) to interconnect its components. The emerging point-to-point NoCs which support single-cycle-multi-hop transmission, reduce or eliminate the latency dependence on distance, addressing the scalability concern raised by high latency for long-distance transmission and enlarging the design space of the routing algorithm to search the non-shortest paths. For such point-to-point NoC-based HCSs, resource management strate

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Deyannis, Dimitris, Eva Papadogiannaki, Grigorios Chrysos, Konstantinos Georgopoulos, and Sotiris Ioannidis. "The Diversification and Enhancement of an IDS Scheme for the Cybersecurity Needs of Modern Supply Chains." Elecronics 11, no. 13 (2022): 17. https://doi.org/10.3390/electronics11131944.

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Despite the tremendous socioeconomic importance of supply chains (SCs), security officers and operators are faced with no easy and integrated way for protecting their critical, and interconnected, infrastructures from cyber-attacks. As a result, solutions and methodologies that support the detection of malicious activity on SCs are constantly researched into and proposed. Hence, this work presents the implementation of a low-cost reconfigurable intrusion detection system (IDS), on the edge, that can be easily integrated into SC networks, thereby elevating the featured levels of security. Speci

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Georgios, Smaragdos, Chatzikonstantis Georgios, Kukreja Rahul, et al. "BrainFrame: A node-level heterogeneous accelerator platform for neuron simulations." December 13, 2016. https://doi.org/10.1088/1741-2552/aa7fc5.

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Objective: The advent of High-Performance Computing (HPC) in recent years has led to its increasing use in brain study through computational models. The scale and complexity of such models are constantly increasing, leading to challenging computational requirements. Even though modern HPC platforms can often deal with such challenges, the vast diversity of the modelling field does not permit for a single acceleration (or homogeneous) platform to effectively address the complete array of modelling requirements. Approach: In this paper we propose and build BrainFrame, a heterogeneous acceleratio

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Mazumdar, Somnath, Alberto Scionti, Stéphane Zuckerman, and Antoni Portero. "NoC-based hardware software co-design framework for dataflow thread management." Journal of Supercomputing, May 11, 2023. http://dx.doi.org/10.1007/s11227-023-05335-8.

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AbstractApplications running in a large and complex manycore system can significantly benefit from adopting the dataflow model of computation. In a dataflow execution environment, a thread can run only if all its required inputs are available. While the potential benefits are large, it is not trivial to improve resource utilization and energy efficiency by focusing on dataflow thread execution models (i.e., the ways specifying how the threads adhering to a dataflow model of computation execute on a given compute/communication architecture). This paper proposes and implements a hardware-softwar

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Xu, Jinwei, Jingfei Jiang, Lei Gao, Xifu Qian, and Yong Dou. "SPDFA: A Novel Dataflow Fusion Sparse Deep Neural Network Accelerator." ACM Transactions on Reconfigurable Technology and Systems, May 30, 2025. https://doi.org/10.1145/3737462.

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Unstructured sparse pruning significantly reduces the computational and parametric complexities of deep neural network models. Nevertheless, the highly irregular nature of sparse models limits its performance and efficiency on traditional computing platforms, thereby prompting the development of specialized hardware solutions. To improve computational efficiency, we introduce the Sparse Dataflow Fusion Accelerator (SPDFA), a specialized architecture meticulously designed for sparse deep neural networks. Firstly, we present a non-blocking data distribution-computing engine that integrates inner

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Yu, Miao, Tingting Xiang, Venkata Pavan Kumar Miriyala, and Trevor E. Carlson. "Multiply-and-Fire (MnF): An Event-driven Sparse Neural Network Accelerator." ACM Transactions on Architecture and Code Optimization, October 27, 2023. http://dx.doi.org/10.1145/3630255.

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Deep neural network inference has become a vital workload for many systems, from edge-based computing to data centers. To reduce the performance and power requirements for DNNs running on these systems, pruning is commonly used as a way to maintain most of the accuracy of the system while significantly reducing the workload requirements. Unfortunately, accelerators designed for unstructured pruning typically employ expensive methods to either determine non-zero activation-weight pairings or reorder computation. These methods require additional storage and memory accesses compared to the more r

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Behera, Debasis, and Suvendu Naraya Mishra. "Enhancing Network-On-Chip Performance: Advanced Mmu Techniques For Lower Latency And Higher Bandwidth." International Journal of Computational and Experimental Science and Engineering 11, no. 2 (2025). https://doi.org/10.22399/ijcesen.2556.

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With the increasing complexity of high-performance computing systems, Network-on-Chip (NoC) architectures face critical performance bottlenecks due to memory management latency and inefficient bandwidth utilization. This research presents a novel, mathematically rigorous framework for optimizing NoC performance through advanced Memory Management Unit (MMU) techniques, specifically Translation Lookaside Buffer (TLB) caching and hybrid address mapping. The study develops symbolic models of latency and bandwidth as optimization functions, accounting for memory translation delays and dynamic workl

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Shao, Yingzhao, Jincheng Shang, Yunsong Li, et al. "A Configurable Accelerator for CNN‐Based Remote Sensing Object Detection on FPGAs." IET Computers & Digital Techniques 2024, no. 1 (2024). http://dx.doi.org/10.1049/2024/4415342.

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Convolutional neural networks (CNNs) have been widely used in satellite remote sensing. However, satellites in orbit with limited resources and power consumption cannot meet the storage and computing power requirements of current million‐scale artificial intelligence models. This paper proposes a new generation of high flexibility and intelligent CNNs hardware accelerator for satellite remote sensing in order to make its computing carrier more lightweight and efficient. A data quantization scheme for INT16 or INT8 is designed based on the idea of dynamic fixed point numbers and is applied to d

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Ma, Fuqi, Bo Wang, Min Li, et al. "Edge Intelligent Perception Method for Power Grid Icing Condition Based on Multi-Scale Feature Fusion Target Detection and Model Quantization." Frontiers in Energy Research 9 (October 4, 2021). http://dx.doi.org/10.3389/fenrg.2021.754335.

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Insulator is an important equipment of power transmission line. Insulator icing can seriously affect the stable operation of power transmission line. So insulator icing condition monitoring has great significance of the safety and stability of power system. Therefore, this paper proposes a lightweight intelligent recognition method of insulator icing thickness for front-end ice monitoring device. In this method, the residual network (ResNet) and feature pyramid network (FPN) are fused to construct a multi-scale feature extraction network framework, so that the shallow features and deep feature

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Raju, Bandi, and Shoban Mude. "Neural Architecture Search (NAS) for Auto-Configurable SoC Designs." International Journal For Multidisciplinary Research 7, no. 3 (2025). https://doi.org/10.36948/ijfmr.2025.v07i03.49273.

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The increasing complexity of System-on-Chip (SoC) designs necessitates advanced techniques for automating the configuration of heterogeneous computing resources. Neural Architecture Search (NAS), a subdomain of AutoML, has emerged as a powerful tool to optimize deep neural network architectures. In this paper, we propose a novel framework that integrates NAS into the design flow of Auto-Configurable SoC architectures. By combining design-space exploration (DSE) with hardware-aware NAS algorithms, the proposed approach enables automated customization of SoC components such as accelerators, memo

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Wang, Song, Qiushuang Yu, Tiantian Xie, Cheng Ma, and Jing Pei. "Approaching the mapping limit with closed-loop mapping strategy for deploying neural networks on neuromorphic hardware." Frontiers in Neuroscience 17 (May 18, 2023). http://dx.doi.org/10.3389/fnins.2023.1168864.

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The decentralized manycore architecture is broadly adopted by neuromorphic chips for its high computing parallelism and memory locality. However, the fragmented memories and decentralized execution make it hard to deploy neural network models onto neuromorphic hardware with high resource utilization and processing efficiency. There are usually two stages during the model deployment: one is the logical mapping that partitions parameters and computations into small slices and allocate each slice into a single core with limited resources; the other is the physical mapping that places each logical

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Lin, Wei-Ting, Hsiang-Yun Cheng, Chia-Lin Yang, et al. "DL-RSIM: A Reliability and Deployment Strategy Simulation Framework for ReRAM-based CNN Accelerators." ACM Transactions on Embedded Computing Systems, January 31, 2022. http://dx.doi.org/10.1145/3507639.

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Memristor-based deep learning accelerators provide a promising solution to improve the energy efficiency of neuromorphic computing systems. However, the electrical properties and crossbar structure of memristors make these accelerators error-prone. In addition, due to the hardware constraints, the way to deploy neural network models on memristor crossbar arrays affects the computation parallelism and communication overheads.To enable reliable and energy-efficient memristor-based accelerators, a simulation platform is needed to precisely analyze the impact of non-ideal circuit/device properties

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Boikynia, Artur O., Nikita S. Tkachenko, Yuriy V. Didenko, Ostap O. Oliinyk, and Dmitry D. Tatarchuk. "Investigation of Electrical Signals Transmission through Light-Induced Conductive Channels on the Surface of CdS Single Crystal." Microsystems, Electronics and Acoustics 29, no. 2 (2024). http://dx.doi.org/10.20535/2523-4455.mea.304564.

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Further development of information technologies hinges on innovations in the electronic components sector, particularly in enhancing electronic communication devices. This involves creating dynamic interconnects—electrically conductive channels that can be configured on-demand within chip circuitry to overcome the "tyranny of interconnects," which limits electronic systems due to the fixed nature of conventional interconnects. This paper presents experimental verification of transmitting information through photoconductive channels formed on a photosensitive cadmium sulfide (CdS) semiconductor

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