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Littérature scientifique sur le sujet « SOC [System-on-Chip Soc] »

Auteur : Grafiati

Publié le 4 juin 2021

Mis à jour le 13 février 2022

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Articles de revues sur le sujet "SOC [System-on-Chip Soc]"

Sagar, G. Venkataramana, et Dr K. Srinivasa Rao. « Reconfigurable FFT System on Chip (SOC) ». International Journal of Computer Applications 11, n^o 5 (10 décembre 2010) : 35–38. http://dx.doi.org/10.5120/1575-2107.

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Chitti, Sridevi, P. Chandrasekhar et M. Asharani. « A Unique Test Bench for Various System-on-a-Chip ». International Journal of Electrical and Computer Engineering (IJECE) 7, n^o 6 (1 décembre 2017) : 3318. http://dx.doi.org/10.11591/ijece.v7i6.pp3318-3322.

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This paper discusses a standard flow on how an automated test bench environment which is randomized with constraints can verify a SOC efficiently for its functionality and coverage. Today, in the time of multimillion gate ASICs, reusable intellectual property (IP), and system-on-a-chip (SoC) designs, verification consumes about 70 % of the design effort. Automation means a machine completes a task autonomously, quicker and with predictable results. Automation requires standard processes with well-defined inputs and outputs. By using this efficient methodology it is possible to provide a general purpose automation solution for verification, given today’s technology. Tools automating various portions of the verification process are being introduced. Here, we have Communication based SOC The content of the paper discusses about the methodology used to verify such a SOC-based environment. Cadence Efficient Verification Methodology libraries are explored for the solution of this problem. We can take this as a state of art approach in verifying SOC environments. The goal of this paper is to emphasize the unique testbench for different SOC using Efficient Verification Constructs implemented in system verilog for SOC verification.

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Jia, Hao, Shanglin Yang, Ting Zhou, Sizhu Shao, Xin Fu, Lei Zhang et Lin Yang. « WDM-compatible multimode optical switching system-on-chip ». Nanophotonics 8, n^o 5 (27 avril 2019) : 889–98. http://dx.doi.org/10.1515/nanoph-2019-0005.

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AbstractThe development of optical interconnect techniques greatly expands the communication bandwidth and decreases the power consumption at the same time. It provides a prospective solution for both intra-chip and inter-chip links. Herein reported is an integrated wavelength-division multiplexing (WDM)-compatible multimode optical switching system-on-chip (SoC) for large-capacity optical switching among processors. The interfaces for the input and output of the processor signals are electrical, and the on-chip data transmission and switching process are optical. It includes silicon-based microring optical modulator arrays, mode multiplexers/de-multiplexers, optical switches, microring wavelength de-multiplexers and germanium-silicon high-speed photodetectors. By introducing external multi-wavelength laser sources, the SoC achieved the function of on-chip WDM and mode-division multiplexing (MDM) hybrid-signal data transmission and switching on a standard silicon photonics platform. As a proof of concept, signals with a 25 Gbps data rate are implemented on each microring modulator of the fabricated SoC. We illustrated 25 × 3 × 2 Gbps on-chip data throughput with two-by-two multimode switching functionality through implementing three wavelength-channels and two mode-channel hybrid-multiplexed signals for each multimode transmission waveguide. The architecture of the SoC is flexible to scale, both for the number of supported processors and the data throughput. The demonstration paves the way to a large-capacity multimode optical switching SoC.

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Liu, Xiang Wen, et Li Min Liu. « The IP Design for a Customized Mobile SoC ». Advanced Materials Research 605-607 (décembre 2012) : 2087–90. http://dx.doi.org/10.4028/www.scientific.net/amr.605-607.2087.

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IP, Intellectual Property, modules are essential and important for SoC applications. SoC, System on a Chip, is a system integrated on a single semiconductor chip. It is a research hot-point in embedded systems. In this paper, the IP design for a customized mobile SoC is discussed. The customized mobile SoC integrates a mobile computing control or monitor system into one chip FPGA, Field Programmable Gate Arrays. The SoC is required smaller in size and more efficient in operation.

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Dorothy, R., et Sasilatha T. « System on Chip Based RTC in Power Electronics ». Bulletin of Electrical Engineering and Informatics 6, n^o 4 (1 décembre 2017) : 358–63. http://dx.doi.org/10.11591/eei.v6i4.867.

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Current control systems and emulation systems (Hardware-in-the-Loop, HIL or Processor-in-the-Loop, PIL) for high-end power-electronic applications often consist of numerous components and interlinking busses: a micro controller for communication and high level control, a DSP for real-time control, an FPGA section for fast parallel actions and data acquisition, multiport RAM structures or bus systems as interconnecting structure. System-on-Chip (SoC) combines many of these functions on a single die. This gives the advantage of space reduction combined with cost reduction and very fast internal communication. Such systems become very relevant for research and also for industrial applications. The SoC used here as an example combines a Dual-Core ARM 9 hard processor system (HPS) and an FPGA, including fast interlinks between these components. SoC systems require careful software and firmware concepts to provide real-time control and emulation capability. This paper demonstrates an optimal way to use the resources of the SoC and discusses challenges caused by the internal structure of SoC. The key idea is to use asymmetric multiprocessing: One core uses a bare-metal operating system for hard real time. The other core runs a “real-time” Linux for service functions and communication. The FPGA is used for flexible process-oriented interfaces (A/D, D/A, switching signals), quasi-hard-wired protection and the precise timing of the real-time control cycle. This way of implementation is generally known and sometimes even suggested–but to the knowledge of the author’s seldomly implemented and documented in the context of demanding real-time control or emulation. The paper details the way of implementation, including process interfaces, and discusses the advantages and disadvantages of the chosen concept. Measurement results demonstrate the properties of the solution.

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Patil, Mr Abhijit, et Mr A. A. Shirolkar. « A Review on System-on-Chip SoC Designs for Real-Time Industrial Application ». International Journal of Trend in Scientific Research and Development Volume-2, Issue-1 (31 décembre 2017) : 1534–37. http://dx.doi.org/10.31142/ijtsrd7077.

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IIDA, Atsuko, Yutaka ONOZUKA, Hiroshi YAMADA, Toshihiko NAGANO et Kazuhiko ITAYA. « High-quality multiple global layers on chip-redistributed wafer for wafer-level system integration using pseudo-SOC ». International Symposium on Microelectronics 2011, n^o 1 (1 janvier 2011) : 000820–27. http://dx.doi.org/10.4071/isom-2011-wp5-paper3.

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This paper reports an advanced process to realize high-quality multiple global layers on high-accuracy chip-redistributed wafer for wafer-level system integration using pseudo-SOC. We have been developing pseudo-SOC (p-SOC) technology by which KGD chips are integrated to a chip-redistributed wafer using high-rigidity epoxy resin and global layers with interconnecting chips are formed on it. The basic process has been established for p-SOC, and integration of MEMS and LSI, or front-end RF LSI and passive components, has been demonstrated. However, the first stage of p-SOC technology was based on a single global layer consisting of an insulating layer and a conductive layer, which limited the range of application. It is desirable to realize high-quality multiple global layers on the high-accuracy chip-redistributed wafer in order to expand its application toward system-level integration. For this purpose, it is necessary to keep all processes at low temperature for the reduction of warpage in the resin-based chip-redistributed wafer during several resin curing processes, to readjust resin-based materials, and to obtain high accuracy of chip position in chip-redistributed wafer. We developed the advanced p-SOC process to resolve these technical issues by improving the hardening process of resin, employing low-temperature-curing polyimide and optimizing the stress analysis by FEM simulation. As a result, realization of a novel one-chip module for a versatile high-sensitivity amplifier is demonstrated.

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Jung, Jun-Mo. « Low Power Test for SoC(System-On-Chip) ». Journal of information and communication convergence engineering 9, n^o 6 (31 décembre 2011) : 729–32. http://dx.doi.org/10.6109/ijice.2011.9.6.729.

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Charles, Subodha, et Prabhat Mishra. « A Survey of Network-on-Chip Security Attacks and Countermeasures ». ACM Computing Surveys 54, n^o 5 (juin 2021) : 1–36. http://dx.doi.org/10.1145/3450964.

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With the advances of chip manufacturing technologies, computer architects have been able to integrate an increasing number of processors and other heterogeneous components on the same chip. Network-on-Chip (NoC) is widely employed by multicore System-on-Chip (SoC) architectures to cater to their communication requirements. NoC has received significant attention from both attackers and defenders. The increased usage of NoC and its distributed nature across the chip has made it a focal point of potential security attacks. Due to its prime location in the SoC coupled with connectivity with various components, NoC can be effectively utilized to implement security countermeasures to protect the SoC from potential attacks. There is a wide variety of existing literature on NoC security attacks and countermeasures. In this article, we provide a comprehensive survey of security vulnerabilities in NoC-based SoC architectures and discuss relevant countermeasures.

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Marrouche, Wissam, Rana Farah et Haidar M. Harmanani. « A Strength Pareto Evolutionary Algorithm for Optimizing System-On-Chip Test Schedules ». International Journal of Computational Intelligence and Applications 17, n^o 02 (juin 2018) : 1850010. http://dx.doi.org/10.1142/s1469026818500104.

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System-on-chip (SOC) has become a mainstream design practice that integrates intellectual property cores on a single chip. The SOC test scheduling problem maximizes the simultaneous test of all cores by determining the order in which various cores are tested. The problem is tightly coupled with the test access mechanism (TAM) bandwidth and wrapper design. This paper presents a strength Pareto evolutionary algorithm for the SOC test scheduling problem with the objective of minimizing the power-constrained test application time, wrapper design and TAM assignment in flat and hierarchical core-based systems. We demonstrate the effectiveness of the method using the ITC’02 benchmarks.

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Thèses sur le sujet "SOC [System-on-Chip Soc]"

Gonciari, Paul Theo. « Low cost test for core-based system-on-a-chip ». Thesis, University of Southampton, 2003. https://eprints.soton.ac.uk/257354/.

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The availability of high level integration leads to building of millions of gates systemson- a-chip (SOC). Due to the high complexity of SOCs, testing them is becoming increasingly difficult. In addition, if the current test practises are maintained, the high cost of test will lead to a considerable production cost increase. To alleviate the test cost problem, this research investigates methods which lead to low-cost test of core-based systems-on-a-chip based on test resource partitioning and without changing the embedded cores. Analysing the factors which drive the continuous increase in test cost, this thesis identifies a number of factors which need to be addressed in order to reduce the cost of test. These include volume of test data, number of pins for test, bandwidth requirements and the cost of test equipment. The approaches proposed to alleviate the cost of test problem have been validated using academic and industrial benchmark cores. To reduce the volume of test data and the number of pins for test, the new Variablelength Input Huffman Coding (VIHC) test data compression method is proposed, which is capable of simultaneously reducing the volume of test data, the test application time and the on-chip area overhead, when compared to previously reported approaches. Due to the partitioning of resources among the SOC and the test equipment, various synchronisation issues arise. Synchronisation increases the cost of test equipment and hence limits the effectiveness of test resource partitioning schemes. Therefore, the synchronisation issues imposed by test data compression methods are analysed and an on-chip distribution architecture is proposed which in addition to accounting for the synchronisation issues also reduces the test application time. The cost of test equipment is related to the amount of test memory, and therefore efficient exploitation of this resource is of great importance. Analysing the memory requirements for core based SOCs, useless test data is identified as one contributor to the total amount of allocated memory, leading to inefficient memory usage. To address this problem a complementary approach to test data compression is proposed to reduce the test memory requirements through elimination of useless test data. Finally, a new test methodology is proposed which combines the approaches proposed in this thesis into an integrated solution for SOC test. The proposed solution leads to reduction in volume of test data, test pins, bandwidth requirements and cost of test equipment. Furthermore, the solution provides seamless integration with the design flow and refrains from changing the cores. Hence, it provides a low-cost test solution for corebased SOC using test resource partitioning.

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Yabarrena, Jean Mimar Santa Cruz. « Tecnologias system on chip e CAN em sistemas de controle distribuído ». Universidade de São Paulo, 2006. http://www.teses.usp.br/teses/disponiveis/18/18149/tde-31072006-203757/.

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Sistemas de controle precisam trabalhar com restrições temporais rigorosas para garantir seu correto funcionamento, sendo por isso considerados sistemas de tempo-real. Quando tais sistemas são distribuídos, as redes de sensores, atuadores e controladores estão interligados em geral, por redes de campo. Nesse contexto, as redes de campo desempenham um papel extremamente importante no comportamento global do sistema. O presente trabalho de pesquisa apresenta a descrição do processo de desenvolvimento de um system on-chip (SoC) para um sistema de controle. Diferentemente das abordagens clássicas, o trabalho está focado em implementar o sistema baseado em um paradigma diferenciado, baseado em lógica reprogramável. Apresenta-se o projeto e construção dos IP cores necessários para controlar um motor DC, utilizando o barramento control area network (CAN) para obter uma plataforma distribuída. A arquitetura on chip utilizada está baseada na especificação CoreConnect da IBM. São expostos, ainda, trabalhos de simulação tanto dos componentes isolados, como do sistema integrado, de forma a realizar uma comparação qualitativa do processo de desenvolvimento
Control systems require strict time constraints to work properly, being therefore considered real-time systems. When such systems are distributed, controllers, sensors, and actuators are generally interconnected by fieldbuses. In this context the fieldbuses play an important role in the system global behavior. This research presents the description of the development process of a system-on-chip SoC. Differentiated from the classical approaches, this work focus the implementation of a reprogrammable logic based system. This work explain the necessary IP cores implementation, allowing a DC motor control, using a control area network (CAN) bus to reach a distributed platform. The on-chip architecture used is based on the IBM CoreConnect specification. Moreover it shows isolated components and integral system simulations, in such a way to obtain a qualitative comparison of development processes

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Zhao, Wei. « Digital Surveillance Based on Video CODEC System-on-a-Chip (SoC) Platforms ». FIU Digital Commons, 2010. http://digitalcommons.fiu.edu/etd/334.

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Today, most conventional surveillance networks are based on analog system, which has a lot of constraints like manpower and high-bandwidth requirements. It becomes the barrier for today’s surveillance network development. This dissertation describes a digital surveillance network architecture based on the H.264 coding/decoding (CODEC) System-on-a-Chip (SoC) platform. The proposed digital surveillance network architecture includes three major layers: software layer, hardware layer, and the network layer. The following outlines the contributions to the proposed digital surveillance network architecture. (1) We implement an object recognition system and an object categorization system on the software layer by applying several Digital Image Processing (DIP) algorithms. (2) For better compression ratio and higher video quality transfer, we implement two new modules on the hardware layer of the H.264 CODEC core, i.e., the background elimination module and the Directional Discrete Cosine Transform (DDCT) module. (3) Furthermore, we introduce a Digital Signal Processor (DSP) sub-system on the main bus of H.264 SoC platforms as the major hardware support system for our software architecture. Thus we combine the software and hardware platforms to be an intelligent surveillance node. Lab results show that the proposed surveillance node can dramatically save the network resources like bandwidth and storage capacity.

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Dias, Marcelo Mallmann. « Plataforma para injeção de falhas em System-on-Chip (SOC) ». Pontifícia Universidade Católica do Rio Grande do Sul, 2011. http://hdl.handle.net/10923/3178.

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The increasing number of embedded computer systems being used in several segments of our society, from simple consumer products to safety critical applications, has intensified the study and development of new test methodologies and fault tolerance techniques capable of assuring the high reliability expected from those systems. Fault injection represents an extremely efficient way of the test and the fault-tolerant techniques often adopted in complex integrated circuits, such as Systems-on-Chip (SoCs). This work proposes a new fault injection platform that combines concepts related to hardware-based and simulation-based fault injection techniques. This new platform is able to inject different kinds of faults into the busses present in several functional components in a VHDL described SoC. The use of saboteurs controlled by a fault injection manager instantiated in the same FPGA as the target system provides high controllability coupled with low intrusiveness and a wide range of possible fault models. Moreover, it is worth noting that the proposed platform represents an easy solution with respect to the configuration and automation of fault injection campaigns.
O aumento do número de sistemas computacionais embarcados sendo utilizados em diversos segmentos de nossa sociedade, de simples bens de consumo até aplicações críticas, intensificou o desenvolvimento de novas metodologias de teste e técnicas de tolerância a falhas capazes de garantir o grau de confiabilidade esperado os mesmos. A injeção de falhas representa uma solução extremamente eficaz de avaliar metodologias de teste e técnicas de tolerância a falhas presentes em circuitos integrados complexos, tais como Systems-on-Chip (SoCs). Este trabalho propõe uma nova plataforma de injeção de falhas que combina conceitos relacionados a técnicas de injeção de falhas baseadas em hardware e em simulação. Esta nova plataforma proposta é capaz de injetar diferentes tipos de falhas nos barramentos presentes em diversos componentes funcionais de um SoC descrito em VHDL. O uso de sabotadores controlados por um gerenciador de injeção de falhas instanciado no mesmo FPGA que o sistema a ser avaliado é capaz de prover uma alta controlabilidade aliada a baixa intrusividade e uma grande gama de modelos de falhas. Além disso, é importante salientar que a plataforma proposta representa uma solução fácil no que diz respeito à configuração e automação de experimentos de injeção de falhas.

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Aulagnier, Guillaume. « Optimisation de convertisseurs DC-DC SoC (System on Chip) pour l'automobile ». Phd thesis, Toulouse, INPT, 2015. http://oatao.univ-toulouse.fr/19512/1/AULAGNIER_Guillaume.pdf.

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L’équipe de conception de Freescale à Toulouse développe des circuits intégrés dédiés au marché de l’automobile pour des applications châssis, sécurité ou loisir. Les contraintes associées à l’embarquement des circuits sont nombreuses : niveau d’intégration, fiabilité, températures élevées, et compatibilité électromagnétique. Les produits conçus par Freescale intègrent des convertisseurs à découpage pour l’alimentation en énergie des microcontrôleurs. Cette thèse a pour objet l’étude de nouvelles topologies de convertisseur d’énergie pour la baisse de l’encombrement et des perturbations électromagnétiques. La structure multiphase répond à la problématique dans son ensemble. Un prototype est réalisé dans une technologie silicium Freescale haute tension 0.25µm. Le volume des composants externes de filtrage est optimisé et réduit. Les mesures sur le prototype montrent des performances en accord avec les objectifs, et des émissions électromagnétiques particulièrement faibles.

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Adhipathi, Pradeep. « Model based approach to Hardware/ Software Partitioning of SOC Designs ». Thesis, Virginia Tech, 2003. http://hdl.handle.net/10919/9986.

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As the IT industry marks a paradigm shift from the traditional system design model to System-On-Chip (SOC) design, the design of custom hardware, embedded processors and associated software have become very tightly coupled. Any change in the implementation of one of the components affects the design of other components and, in turn, the performance of the system. This has led to an integrated design approach known as hardware/software co-design and co-verification. The conventional techniques for co-design favor partitioning the system into hardware and software components at an early stage of the design and then iteratively refining it until a good solution is found. This method is expensive and time consuming. A more modern approach is to model the whole system and rigorously test and refine it before the partitioning is done. The key to this method is the ability to model and simulate the entire system. The advent of new System Level Modeling Languages (SLML), like SystemC, has made this possible. This research proposes a strategy to automate the process of partitioning a system model after it has been simulated and verified. The partitioning idea is based on systems modeled using Process Model Graphs (PmG). It is possible to extract a PmG directly from a SLML like SystemC. The PmG is then annotated with additional attributes like IO delay and rate of activation. A complexity heuristic is generated from this information, which is then used by a greedy algorithm to partition the graph into different architectures. Further, a command line tool has been developed that can process textually represented PmGs and partition them based on this approach.
Master of Science

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Dias, Marcelo Mallmann. « Plataforma para inje??o de falhas em System-on-Chip (SOC) ». Pontif?cia Universidade Cat?lica do Rio Grande do Sul, 2009. http://tede2.pucrs.br/tede2/handle/tede/3036.

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O aumento do n?mero de sistemas computacionais embarcados sendo utilizados em diversos segmentos de nossa sociedade, de simples bens de consumo at? aplica??es cr?ticas, intensificou o desenvolvimento de novas metodologias de teste e t?cnicas de toler?ncia a falhas capazes de garantir o grau de confiabilidade esperado os mesmos. A inje??o de falhas representa uma solu??o extremamente eficaz de avaliar metodologias de teste e t?cnicas de toler?ncia a falhas presentes em circuitos integrados complexos, tais como Systems-on-Chip (SoCs). Este trabalho prop?e uma nova plataforma de inje??o de falhas que combina conceitos relacionados a t?cnicas de inje??o de falhas baseadas em hardware e em simula??o. Esta nova plataforma proposta ? capaz de injetar diferentes tipos de falhas nos barramentos presentes em diversos componentes funcionais de um SoC descrito em VHDL. O uso de sabotadores controlados por um gerenciador de inje??o de falhas instanciado no mesmo FPGA que o sistema a ser avaliado ? capaz de prover uma alta controlabilidade aliada a baixa intrusividade e uma grande gama de modelos de falhas. Al?m disso, ? importante salientar que a plataforma proposta representa uma solu??o f?cil no que diz respeito ? configura??o e automa??o de experimentos de inje??o de falhas.

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Lu, Jian. « Embedded Magnetics for Power System on Chip (PSoC) ». Doctoral diss., University of Central Florida, 2009. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/2993.

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A novel concept of on-chip bondwire inductors and transformers with ferrite epoxy glob coating is proposed, offering a cost effective approach to realize power systems on chip (PSoC) or System-in-Package (PSiP). The concept has been investigated both experimentally and with finite element modeling. Improvement in total inductance is demonstrated for multi-turn bondwire inductors over single bondwire inductors. The inductance and Q factor can be further boosted with coupled multi-turn inductor concept. Transformer parameters including self- and mutual inductance, and coupling factors are extracted from both modeled and measured S-parameters. More importantly, the bondwire magnetic components can be easily integrated into SoC manufacturing processes with minimal changes to the layout, and open enormous possibilities for realizing cost-effective, high current, high efficiency PSoC's or PSiP's. The design guidelines for single bondwire inductors as well as multi-turn inductors are discussed step by step in several chapters. Not only is the innovated concept for bondwire inductor with ferrite ink presented, but also the practical implementation and design rules are given. With all the well defined steps, people who want to use these bondwire inductors with ferrite ink in their PSoC research or products will find it as simple as using commercial inductors. Last but not least, the PSoC concept using a bondwire inductor is demonstrated by building the prototype of dc-dc buck converter IC as well as the whole package. IC and the whole function block are tested and presented in this work.
Ph.D.
School of Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering PhD

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Flórez, Martha Johanna Sepúlveda. « Estimativa de desempenho de uma NoC a partir de seu modelo em SYSTEMC-TLM ». Universidade de São Paulo, 2006. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-14122006-152854/.

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The wide variety of interconnection structures presently nowadays for SoC (Systemon- Chip), bus and networks-on-Chip NoCs, each of them with a wide set of setup parameters, provides a huge amount of design alternatives. Although the interconnection structure is a key SoC component, there are few design tools in order to set the appropriate configuration parameters for a given application. An efficient SoC project may comply an exploration stage among the possible solutions for the communication structure, during the first steps of the design process. The absence of appropriate tools for that exploration makes critical the designer?s judgment. The present study aims to enhance the communication SoC structure design area, when a NoC is used. This work proposes a methodology that allows the establishment of the NoC communication parameters using a high level model (SystemC TLM timed). Our approach analyzes and evaluates the NoC performance under a wide variety of traffic conditions. The experimental stage was conducted employing a model of a net represented by a SystemC TLM timed (Hermes_Temp). Parametric and pseudo-random generators control the network traffic. The analysis was carried on with a tool designed for these purpose, which generates a group of performance metrics. The results allow to elucidate the global and inner network behavior. The performance values are useful for the heterogeneous and homogeneous NoC design projects, improving the performance evaluation studies scope.
The wide variety of interconnection structures presently nowadays for SoC (Systemon- Chip), bus and networks-on-Chip NoCs, each of them with a wide set of setup parameters, provides a huge amount of design alternatives. Although the interconnection structure is a key SoC component, there are few design tools in order to set the appropriate configuration parameters for a given application. An efficient SoC project may comply an exploration stage among the possible solutions for the communication structure, during the first steps of the design process. The absence of appropriate tools for that exploration makes critical the designer?s judgment. The present study aims to enhance the communication SoC structure design area, when a NoC is used. This work proposes a methodology that allows the establishment of the NoC communication parameters using a high level model (SystemC TLM timed). Our approach analyzes and evaluates the NoC performance under a wide variety of traffic conditions. The experimental stage was conducted employing a model of a net represented by a SystemC TLM timed (Hermes_Temp). Parametric and pseudo-random generators control the network traffic. The analysis was carried on with a tool designed for these purpose, which generates a group of performance metrics. The results allow to elucidate the global and inner network behavior. The performance values are useful for the heterogeneous and homogeneous NoC design projects, improving the performance evaluation studies scope.

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Stadler, Manfred. « Verification issues of virtual components in system-on-a-chip (SOC) designs / ». Zürich, 2000. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=13814.

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Livres sur le sujet "SOC [System-on-Chip Soc]"

Madisetti, V. A platform-centric approach to system-on-chip (SOC) design. New York : Springer, 2010.

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Chonlameth, Arpnikanondt, dir. A platform-centric approach to system-on-chip (SoC) design. New York : Springer, 2005.

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Madisetti, Vijay K. A platform-centric approach to system-on-chip (SOC) design. New York, NY : Springer, 2005.

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Chakravarthi, Veena S. A Practical Approach to VLSI System on Chip (SoC) Design. Cham : Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-23049-4.

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Burg, Andreas, Ayṣe Coṣkun, Matthew Guthaus, Srinivas Katkoori et Ricardo Reis, dir. VLSI-SoC : From Algorithms to Circuits and System-on-Chip Design. Berlin, Heidelberg : Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-45073-0.

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Stadler, Manfred. Verification issues of virtual components in system-on-a-chip (SOC) designs. Konstanz : Hartung-Gorre, 2000.

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Chakrabarty, Krishnendu, dir. SOC (System-on-a-Chip) Testing for Plug and Play Test Automation. Boston, MA : Springer US, 2002. http://dx.doi.org/10.1007/978-1-4757-6527-4.

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Chakrabarty, Krishnendu. SOC (System-on-a-Chip) Testing for Plug and Play Test Automation. Boston, MA : Springer US, 2002.

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Finland) International Symposium on System-on-Chip (2012 Tampere. 2012 International Symposium on System on Chip (SoC 2012) : Tampere, Finland, 10-12 October 2012. Piscataway, NJ : IEEE, 2012.

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Hollstein, Thomas, Jaan Raik, Sergei Kostin, Anton Tšertov, Ian O'Connor et Ricardo Reis, dir. VLSI-SoC : System-on-Chip in the Nanoscale Era – Design, Verification and Reliability. Cham : Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-67104-8.

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Plus de sources

Chapitres de livres sur le sujet "SOC [System-on-Chip Soc]"

Farahmandi, Farimah, Yuanwen Huang et Prabhat Mishra. « SoC Security Verification Challenges ». Dans System-on-Chip Security, 15–35. Cham : Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-30596-3_2.

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Dongarra, Jack, Piotr Luszczek, Felix Wolf, Jesper Larsson Träff, Patrice Quinton, Hermann Hellwagner, Martin Fränzle et al. « System on Chip (SoC) ». Dans Encyclopedia of Parallel Computing, 1997. Boston, MA : Springer US, 2011. http://dx.doi.org/10.1007/978-0-387-09766-4_2101.

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Dongarra, Jack, Piotr Luszczek, Felix Wolf, Jesper Larsson Träff, Patrice Quinton, Hermann Hellwagner, Martin Fränzle et al. « SoC (System on Chip) ». Dans Encyclopedia of Parallel Computing, 1837–42. Boston, MA : Springer US, 2011. http://dx.doi.org/10.1007/978-0-387-09766-4_5.

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Farahmandi, Farimah, Yuanwen Huang et Prabhat Mishra. « SoC Trust Metrics and Benchmarks ». Dans System-on-Chip Security, 37–57. Cham : Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-30596-3_3.

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Chakravarthi, Veena S. « SOC Packaging ». Dans A Practical Approach to VLSI System on Chip (SoC) Design, 215–24. Cham : Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-23049-4_11.

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Chakravarthi, Veena S. « SOC Constituents ». Dans A Practical Approach to VLSI System on Chip (SoC) Design, 41–61. Cham : Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-23049-4_3.

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Chakravarthi, Veena S. « SOC Synthesis ». Dans A Practical Approach to VLSI System on Chip (SoC) Design, 81–97. Cham : Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-23049-4_5.

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Farahmandi, Farimah, Yuanwen Huang et Prabhat Mishra. « SoC Security Verification Using Property Checking ». Dans System-on-Chip Security, 137–52. Cham : Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-30596-3_7.

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Taraate, Vaibbhav. « System on Chip (SOC) Design ». Dans Digital Logic Design Using Verilog, 381–98. New Delhi : Springer India, 2016. http://dx.doi.org/10.1007/978-81-322-2791-5_15.

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Chakravarthi, Veena S. « System on Chip (SOC) Design ». Dans A Practical Approach to VLSI System on Chip (SoC) Design, 11–40. Cham : Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-23049-4_2.

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Actes de conférences sur le sujet "SOC [System-on-Chip Soc]"

Rogin, Frank, Rolf Drechsler et Steffen Rulke. « Automatic debugging of System-on-a-Chip designs ». Dans 2009 IEEE International SOC Conference (SOCC). IEEE, 2009. http://dx.doi.org/10.1109/soccon.2009.5398027.

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Ho, Chun Hok, Wayne Luk, Jakub M. Szefer et Ruby B. Lee. « Tuning instruction customisation for reconfigurable system-on-chip ». Dans 2009 IEEE International SOC Conference (SOCC). IEEE, 2009. http://dx.doi.org/10.1109/soccon.2009.5398096.

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Kaxiras, Stefanos, et Alberto Ros. « Efficient, snoopless, System-on-Chip coherence ». Dans 2012 IEEE 25th International SOC Conference (SOCC). IEEE, 2012. http://dx.doi.org/10.1109/socc.2012.6398353.

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Marshall, Andrew. « Advanced SoC components ». Dans 2016 29th IEEE International System-on-Chip Conference (SOCC). IEEE, 2016. http://dx.doi.org/10.1109/socc.2016.7905479.

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« SOC 2011 : Advanced program ». Dans 2011 International Symposium on System-on-Chip - SOC. IEEE, 2011. http://dx.doi.org/10.1109/issoc.2011.6089215.

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Hsing-Chih Hung, Ting-Hao Lin et Chung-Yang Huang. « QuteIP : An IP qualification framework for System on Chip ». Dans 2007 IEEE International SOC Conference (SOCC). IEEE, 2007. http://dx.doi.org/10.1109/socc.2007.4545466.

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Kopetz, H., C. El Salloum, B. Huber, R. Obermaisser et C. Paukovits. « Composability in the time-triggered system-on-chip architecture ». Dans 2008 IEEE International SOC Conference (SOCC). IEEE, 2008. http://dx.doi.org/10.1109/socc.2008.4641485.

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Isomaki, P., et N. Avessta. « Rapid Refinable SoC SDR Design ». Dans 2005 International Symposium on System-on-Chip. IEEE, 2005. http://dx.doi.org/10.1109/issoc.2005.1595659.

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Nigussie, E., J. Plosila et J. Isoaho. « Reliable Asynchronous Links for SoC ». Dans 2005 International Symposium on System-on-Chip. IEEE, 2005. http://dx.doi.org/10.1109/issoc.2005.1595660.

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Furber, S., et J. Bainbridge. « Future Trends in SoC Interconnect ». Dans 2005 International Symposium on System-on-Chip. IEEE, 2005. http://dx.doi.org/10.1109/issoc.2005.1595673.

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