Thèses : « SOC [System-on-Chip Soc] »

1

Gonciari, Paul Theo. « Low cost test for core-based system-on-a-chip ». Thesis, University of Southampton, 2003. https://eprints.soton.ac.uk/257354/.

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The availability of high level integration leads to building of millions of gates systemson- a-chip (SOC). Due to the high complexity of SOCs, testing them is becoming increasingly difficult. In addition, if the current test practises are maintained, the high cost of test will lead to a considerable production cost increase. To alleviate the test cost problem, this research investigates methods which lead to low-cost test of core-based systems-on-a-chip based on test resource partitioning and without changing the embedded cores. Analysing the factors which drive the continuous increase in test cost, this thesis identifies a number of factors which need to be addressed in order to reduce the cost of test. These include volume of test data, number of pins for test, bandwidth requirements and the cost of test equipment. The approaches proposed to alleviate the cost of test problem have been validated using academic and industrial benchmark cores. To reduce the volume of test data and the number of pins for test, the new Variablelength Input Huffman Coding (VIHC) test data compression method is proposed, which is capable of simultaneously reducing the volume of test data, the test application time and the on-chip area overhead, when compared to previously reported approaches. Due to the partitioning of resources among the SOC and the test equipment, various synchronisation issues arise. Synchronisation increases the cost of test equipment and hence limits the effectiveness of test resource partitioning schemes. Therefore, the synchronisation issues imposed by test data compression methods are analysed and an on-chip distribution architecture is proposed which in addition to accounting for the synchronisation issues also reduces the test application time. The cost of test equipment is related to the amount of test memory, and therefore efficient exploitation of this resource is of great importance. Analysing the memory requirements for core based SOCs, useless test data is identified as one contributor to the total amount of allocated memory, leading to inefficient memory usage. To address this problem a complementary approach to test data compression is proposed to reduce the test memory requirements through elimination of useless test data. Finally, a new test methodology is proposed which combines the approaches proposed in this thesis into an integrated solution for SOC test. The proposed solution leads to reduction in volume of test data, test pins, bandwidth requirements and cost of test equipment. Furthermore, the solution provides seamless integration with the design flow and refrains from changing the cores. Hence, it provides a low-cost test solution for corebased SOC using test resource partitioning.

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Yabarrena, Jean Mimar Santa Cruz. « Tecnologias system on chip e CAN em sistemas de controle distribuído ». Universidade de São Paulo, 2006. http://www.teses.usp.br/teses/disponiveis/18/18149/tde-31072006-203757/.

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Sistemas de controle precisam trabalhar com restrições temporais rigorosas para garantir seu correto funcionamento, sendo por isso considerados sistemas de tempo-real. Quando tais sistemas são distribuídos, as redes de sensores, atuadores e controladores estão interligados em geral, por redes de campo. Nesse contexto, as redes de campo desempenham um papel extremamente importante no comportamento global do sistema. O presente trabalho de pesquisa apresenta a descrição do processo de desenvolvimento de um system on-chip (SoC) para um sistema de controle. Diferentemente das abordagens clássicas, o trabalho está focado em implementar o sistema baseado em um paradigma diferenciado, baseado em lógica reprogramável. Apresenta-se o projeto e construção dos IP cores necessários para controlar um motor DC, utilizando o barramento control area network (CAN) para obter uma plataforma distribuída. A arquitetura on chip utilizada está baseada na especificação CoreConnect da IBM. São expostos, ainda, trabalhos de simulação tanto dos componentes isolados, como do sistema integrado, de forma a realizar uma comparação qualitativa do processo de desenvolvimento
Control systems require strict time constraints to work properly, being therefore considered real-time systems. When such systems are distributed, controllers, sensors, and actuators are generally interconnected by fieldbuses. In this context the fieldbuses play an important role in the system global behavior. This research presents the description of the development process of a system-on-chip SoC. Differentiated from the classical approaches, this work focus the implementation of a reprogrammable logic based system. This work explain the necessary IP cores implementation, allowing a DC motor control, using a control area network (CAN) bus to reach a distributed platform. The on-chip architecture used is based on the IBM CoreConnect specification. Moreover it shows isolated components and integral system simulations, in such a way to obtain a qualitative comparison of development processes

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Zhao, Wei. « Digital Surveillance Based on Video CODEC System-on-a-Chip (SoC) Platforms ». FIU Digital Commons, 2010. http://digitalcommons.fiu.edu/etd/334.

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Today, most conventional surveillance networks are based on analog system, which has a lot of constraints like manpower and high-bandwidth requirements. It becomes the barrier for today’s surveillance network development. This dissertation describes a digital surveillance network architecture based on the H.264 coding/decoding (CODEC) System-on-a-Chip (SoC) platform. The proposed digital surveillance network architecture includes three major layers: software layer, hardware layer, and the network layer. The following outlines the contributions to the proposed digital surveillance network architecture. (1) We implement an object recognition system and an object categorization system on the software layer by applying several Digital Image Processing (DIP) algorithms. (2) For better compression ratio and higher video quality transfer, we implement two new modules on the hardware layer of the H.264 CODEC core, i.e., the background elimination module and the Directional Discrete Cosine Transform (DDCT) module. (3) Furthermore, we introduce a Digital Signal Processor (DSP) sub-system on the main bus of H.264 SoC platforms as the major hardware support system for our software architecture. Thus we combine the software and hardware platforms to be an intelligent surveillance node. Lab results show that the proposed surveillance node can dramatically save the network resources like bandwidth and storage capacity.

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Dias, Marcelo Mallmann. « Plataforma para injeção de falhas em System-on-Chip (SOC) ». Pontifícia Universidade Católica do Rio Grande do Sul, 2011. http://hdl.handle.net/10923/3178.

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The increasing number of embedded computer systems being used in several segments of our society, from simple consumer products to safety critical applications, has intensified the study and development of new test methodologies and fault tolerance techniques capable of assuring the high reliability expected from those systems. Fault injection represents an extremely efficient way of the test and the fault-tolerant techniques often adopted in complex integrated circuits, such as Systems-on-Chip (SoCs). This work proposes a new fault injection platform that combines concepts related to hardware-based and simulation-based fault injection techniques. This new platform is able to inject different kinds of faults into the busses present in several functional components in a VHDL described SoC. The use of saboteurs controlled by a fault injection manager instantiated in the same FPGA as the target system provides high controllability coupled with low intrusiveness and a wide range of possible fault models. Moreover, it is worth noting that the proposed platform represents an easy solution with respect to the configuration and automation of fault injection campaigns.
O aumento do número de sistemas computacionais embarcados sendo utilizados em diversos segmentos de nossa sociedade, de simples bens de consumo até aplicações críticas, intensificou o desenvolvimento de novas metodologias de teste e técnicas de tolerância a falhas capazes de garantir o grau de confiabilidade esperado os mesmos. A injeção de falhas representa uma solução extremamente eficaz de avaliar metodologias de teste e técnicas de tolerância a falhas presentes em circuitos integrados complexos, tais como Systems-on-Chip (SoCs). Este trabalho propõe uma nova plataforma de injeção de falhas que combina conceitos relacionados a técnicas de injeção de falhas baseadas em hardware e em simulação. Esta nova plataforma proposta é capaz de injetar diferentes tipos de falhas nos barramentos presentes em diversos componentes funcionais de um SoC descrito em VHDL. O uso de sabotadores controlados por um gerenciador de injeção de falhas instanciado no mesmo FPGA que o sistema a ser avaliado é capaz de prover uma alta controlabilidade aliada a baixa intrusividade e uma grande gama de modelos de falhas. Além disso, é importante salientar que a plataforma proposta representa uma solução fácil no que diz respeito à configuração e automação de experimentos de injeção de falhas.

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Aulagnier, Guillaume. « Optimisation de convertisseurs DC-DC SoC (System on Chip) pour l'automobile ». Phd thesis, Toulouse, INPT, 2015. http://oatao.univ-toulouse.fr/19512/1/AULAGNIER_Guillaume.pdf.

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L’équipe de conception de Freescale à Toulouse développe des circuits intégrés dédiés au marché de l’automobile pour des applications châssis, sécurité ou loisir. Les contraintes associées à l’embarquement des circuits sont nombreuses : niveau d’intégration, fiabilité, températures élevées, et compatibilité électromagnétique. Les produits conçus par Freescale intègrent des convertisseurs à découpage pour l’alimentation en énergie des microcontrôleurs. Cette thèse a pour objet l’étude de nouvelles topologies de convertisseur d’énergie pour la baisse de l’encombrement et des perturbations électromagnétiques. La structure multiphase répond à la problématique dans son ensemble. Un prototype est réalisé dans une technologie silicium Freescale haute tension 0.25µm. Le volume des composants externes de filtrage est optimisé et réduit. Les mesures sur le prototype montrent des performances en accord avec les objectifs, et des émissions électromagnétiques particulièrement faibles.

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Adhipathi, Pradeep. « Model based approach to Hardware/ Software Partitioning of SOC Designs ». Thesis, Virginia Tech, 2003. http://hdl.handle.net/10919/9986.

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As the IT industry marks a paradigm shift from the traditional system design model to System-On-Chip (SOC) design, the design of custom hardware, embedded processors and associated software have become very tightly coupled. Any change in the implementation of one of the components affects the design of other components and, in turn, the performance of the system. This has led to an integrated design approach known as hardware/software co-design and co-verification. The conventional techniques for co-design favor partitioning the system into hardware and software components at an early stage of the design and then iteratively refining it until a good solution is found. This method is expensive and time consuming. A more modern approach is to model the whole system and rigorously test and refine it before the partitioning is done. The key to this method is the ability to model and simulate the entire system. The advent of new System Level Modeling Languages (SLML), like SystemC, has made this possible. This research proposes a strategy to automate the process of partitioning a system model after it has been simulated and verified. The partitioning idea is based on systems modeled using Process Model Graphs (PmG). It is possible to extract a PmG directly from a SLML like SystemC. The PmG is then annotated with additional attributes like IO delay and rate of activation. A complexity heuristic is generated from this information, which is then used by a greedy algorithm to partition the graph into different architectures. Further, a command line tool has been developed that can process textually represented PmGs and partition them based on this approach.
Master of Science

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Dias, Marcelo Mallmann. « Plataforma para inje??o de falhas em System-on-Chip (SOC) ». Pontif?cia Universidade Cat?lica do Rio Grande do Sul, 2009. http://tede2.pucrs.br/tede2/handle/tede/3036.

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O aumento do n?mero de sistemas computacionais embarcados sendo utilizados em diversos segmentos de nossa sociedade, de simples bens de consumo at? aplica??es cr?ticas, intensificou o desenvolvimento de novas metodologias de teste e t?cnicas de toler?ncia a falhas capazes de garantir o grau de confiabilidade esperado os mesmos. A inje??o de falhas representa uma solu??o extremamente eficaz de avaliar metodologias de teste e t?cnicas de toler?ncia a falhas presentes em circuitos integrados complexos, tais como Systems-on-Chip (SoCs). Este trabalho prop?e uma nova plataforma de inje??o de falhas que combina conceitos relacionados a t?cnicas de inje??o de falhas baseadas em hardware e em simula??o. Esta nova plataforma proposta ? capaz de injetar diferentes tipos de falhas nos barramentos presentes em diversos componentes funcionais de um SoC descrito em VHDL. O uso de sabotadores controlados por um gerenciador de inje??o de falhas instanciado no mesmo FPGA que o sistema a ser avaliado ? capaz de prover uma alta controlabilidade aliada a baixa intrusividade e uma grande gama de modelos de falhas. Al?m disso, ? importante salientar que a plataforma proposta representa uma solu??o f?cil no que diz respeito ? configura??o e automa??o de experimentos de inje??o de falhas.

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Lu, Jian. « Embedded Magnetics for Power System on Chip (PSoC) ». Doctoral diss., University of Central Florida, 2009. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/2993.

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A novel concept of on-chip bondwire inductors and transformers with ferrite epoxy glob coating is proposed, offering a cost effective approach to realize power systems on chip (PSoC) or System-in-Package (PSiP). The concept has been investigated both experimentally and with finite element modeling. Improvement in total inductance is demonstrated for multi-turn bondwire inductors over single bondwire inductors. The inductance and Q factor can be further boosted with coupled multi-turn inductor concept. Transformer parameters including self- and mutual inductance, and coupling factors are extracted from both modeled and measured S-parameters. More importantly, the bondwire magnetic components can be easily integrated into SoC manufacturing processes with minimal changes to the layout, and open enormous possibilities for realizing cost-effective, high current, high efficiency PSoC's or PSiP's. The design guidelines for single bondwire inductors as well as multi-turn inductors are discussed step by step in several chapters. Not only is the innovated concept for bondwire inductor with ferrite ink presented, but also the practical implementation and design rules are given. With all the well defined steps, people who want to use these bondwire inductors with ferrite ink in their PSoC research or products will find it as simple as using commercial inductors. Last but not least, the PSoC concept using a bondwire inductor is demonstrated by building the prototype of dc-dc buck converter IC as well as the whole package. IC and the whole function block are tested and presented in this work.
Ph.D.
School of Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering PhD

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Flórez, Martha Johanna Sepúlveda. « Estimativa de desempenho de uma NoC a partir de seu modelo em SYSTEMC-TLM ». Universidade de São Paulo, 2006. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-14122006-152854/.

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The wide variety of interconnection structures presently nowadays for SoC (Systemon- Chip), bus and networks-on-Chip NoCs, each of them with a wide set of setup parameters, provides a huge amount of design alternatives. Although the interconnection structure is a key SoC component, there are few design tools in order to set the appropriate configuration parameters for a given application. An efficient SoC project may comply an exploration stage among the possible solutions for the communication structure, during the first steps of the design process. The absence of appropriate tools for that exploration makes critical the designer?s judgment. The present study aims to enhance the communication SoC structure design area, when a NoC is used. This work proposes a methodology that allows the establishment of the NoC communication parameters using a high level model (SystemC TLM timed). Our approach analyzes and evaluates the NoC performance under a wide variety of traffic conditions. The experimental stage was conducted employing a model of a net represented by a SystemC TLM timed (Hermes_Temp). Parametric and pseudo-random generators control the network traffic. The analysis was carried on with a tool designed for these purpose, which generates a group of performance metrics. The results allow to elucidate the global and inner network behavior. The performance values are useful for the heterogeneous and homogeneous NoC design projects, improving the performance evaluation studies scope.
The wide variety of interconnection structures presently nowadays for SoC (Systemon- Chip), bus and networks-on-Chip NoCs, each of them with a wide set of setup parameters, provides a huge amount of design alternatives. Although the interconnection structure is a key SoC component, there are few design tools in order to set the appropriate configuration parameters for a given application. An efficient SoC project may comply an exploration stage among the possible solutions for the communication structure, during the first steps of the design process. The absence of appropriate tools for that exploration makes critical the designer?s judgment. The present study aims to enhance the communication SoC structure design area, when a NoC is used. This work proposes a methodology that allows the establishment of the NoC communication parameters using a high level model (SystemC TLM timed). Our approach analyzes and evaluates the NoC performance under a wide variety of traffic conditions. The experimental stage was conducted employing a model of a net represented by a SystemC TLM timed (Hermes_Temp). Parametric and pseudo-random generators control the network traffic. The analysis was carried on with a tool designed for these purpose, which generates a group of performance metrics. The results allow to elucidate the global and inner network behavior. The performance values are useful for the heterogeneous and homogeneous NoC design projects, improving the performance evaluation studies scope.

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Stadler, Manfred. « Verification issues of virtual components in system-on-a-chip (SOC) designs / ». Zürich, 2000. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=13814.

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Dickson, K. G. « System-on-chip (SoC) processor architecture for Givens rotations based matrix computations ». Thesis, Queen's University Belfast, 2006. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.431587.

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Benfica, Juliano D'Ornellas. « Plataforma para desenvolvimento de SoC (System-on-Chip) robusto à interferência eletromagnética ». Pontifícia Universidade Católica do Rio Grande do Sul, 2007. http://hdl.handle.net/10923/3169.

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The electromagnetic environment in which electronic systems operate is becoming more and more hostile. The society observes with enthusiasm the rapid proliferation of a vast diversity of wireless electronic equipments. Unfortunately, this tendency yields as consequence the pollution of the frequency spectrum, and thus, increasing dramatically the environmental noise where we live. At the same time, it is fundamental for the acceptance and reliability of these electronic equipments that the applications running on their platforms do not fail due to such noisy environment. Therefore, it is fundamental to understand how the electromagnetic noise impacts the reliability of complex electronic systems (Systemson- Chip, SoC). Some companies worldwide have been concerned with this situation. They have proposed several commercial platforms to design and test of SoC. However, these platforms do not allow an adequate measurement of SoC susceptibility to electromagnetic interference (EMI). Such scenario motivated this work. In the following we propose a new platform, reconfigurable, to evaluate and improve SoC designs having in mind the electromagnetic noise immunity. This platform is based on the international standard IEC 62. 132 to design and test electronic systems, at the board level. The final goal of this standard is to dictate rules to allow precise measurements of the SoCs susceptibility to (radiated and conducted) EMI. The proposed platform is based on two specific and complementary boards. The first one is devoted to the radiated noise immunity measurement in a Gigahertz Transverse Electromagnetic Cell (GTEM Cell) according to the standard IEC 62. 132-2 (IEC, 2004), whereas the second board is dedicated to the RF-conducted noise immunity measurement and was implemented according to the standards IEC 62. 132-4 and IEC 62. 132-2 (IEC, 2004), respectively. After the development of the proposed platform, a case-study based on the Xilinx soft-core processor, MicroBlaze, was designed by the Group SiSC and tested on the platform. The obtained results are rewarding and demonstrate the capability and flexibility of the proposed platform as a tool to evaluate the behavior of SoCs in EMIexposed environment.
O ambiente eletromagnético em que sistemas eletrônicos operam está tornando-se cada vez mais hostil. A sociedade observa com bastante entusiasmo a rápida proliferação de uma quantidade infindável de equipamentos eletrônicos sem fio (wireless). Infelizmente, esta tendência tem por conseqüência a poluição de forma dramática do espectro de freqüência, e portanto, aumentando o ruído intrínseco do ambiente onde vivemos. Por outro lado, é fundamental para a aceitação e a segurança destes equipamentos eletrônicos que estes não falhem devido ao ambiente eletromagnético. Assim, é de suma importância compreender como o ruído eletromagnético (Electromagnetic Interference, ou EMI) impacta a confiabilidade de sistemas integrados complexos (Systems-on-Chip, ou SoC). Algumas empresas em escala mundial têm demonstrado muita preocupação com este problema através do desenvolvimento de várias plataformas comerciais para o projeto e o teste de SoCs. Entretanto, estas plataformas não garantem medições adequadas da susceptibilidade dos sistemas eletrônicos à EMI. Este cenário nos motivou a propor uma plataforma de prototipagem reconfigurável para avaliar e aprimorar projetos de SoCs levando-se em consideração sua imunidade ao ruído eletromagnético. Esta plataforma é baseada em normas internacionais IEC 62. 132 para o projeto e o teste de sistemas eletrônicos, ao nível de placa. O objetivo final deste conjunto de normas é ditar regras que viabilizam a medição precisa da imunidade de circuitos integrados à EMI, tanto radiada quanto conduzida. A plataforma desenvolvida é baseada em duas placas específicas e complementares. A primeira é dedicada para o teste de imunidade ao ruído irradiado em uma Gigahertz Transverse Electromagnetic Cell (GTEM Cell) de acordo com a norma IEC 62. 132-2 (IEC, 2004).A segunda placa é dedicada ao teste conduzido de ruído de RF e foi implementada de acordo com as normas IEC 62. 132-4 e IEC 62. 132-2 (IEC, 2004), respectivamente. Após o desenvolvimento da plataforma em questão, um estudo-de-caso baseado no processador soft-core da Xilinx, MicroBlaze, operando sob o controle do sistema operacional uCOS-II foi desenvolvido pelo Grupo SiSC e testado na plataforma. Os resultados dos ensaios são bastante motivadores e demonstram a capacidade e a flexibilidade da plataforma ser utilizada como ferramenta para avaliar o comportamento de SoCs em ambiente ruidoso do tipo EMI.

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Avnit, Karin Computer Science &amp Engineering Faculty of Engineering UNSW. « Provably correct on-chip communication : a formal approach to automatic synthesis of SoC protocol converters ». Awarded By:University of New South Wales. Computer Science & ; Engineering, 2010. http://handle.unsw.edu.au/1959.4/44701.

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The field of chip design is characterized by contradictory pressures to reduce time-to-market and maintain a high level of reliability. As a result, module reuse has become common practice in chip design. To save time on both design and verification, Systems-on-Chips (SoCs) are composed using pre-designed and pre-verified modules. The integrated modules are often designed by different groups and for different purposes, and are later integrated into a single chip. In the absence of a single interface standard for such modules, "plug-n-play" style integration is not likely, as the subject modules are often designed to comply with different interface protocols. For such modules to communicate correctly there is a need for some glue logic, also called a protocol converter that mediates between them. Though much research has been dedicated to the protocol converter synthesis problem of SoC communication, converter synthesis is still performed manually, consuming development and verification time and risking human error. Current approaches to automatic synthesis of protocol converters mostly lack formal foundations and either employ abstractions far removed from the Hardware Description Language (HDL) implementation level or grossly simplify the structure of the protocols considered. This thesis develops and presents techniques for automatic synthesis of provably correct on-chip protocol converters. Basing the solution on a formal approach, a novel state-machine based formalism is presented for modelling bus-based protocols and formalizing the notions of protocol compatibility and correct protocol conversion. Algorithms for automatic compatibility checking and provably-correct converter synthesis are derived from the formalism, including a systematic exploration of the design space of the protocol converter, the first in the field, which enables generation of various alternative deterministic converters. The work presented is unique in its combination of a completely formal approach and the use of a low abstraction level that enables precise modelling of protocol characteristics and automatic translation of the constructed converter to HDL.

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Benfica, Juliano D'ornellas. « Plataforma para desenvolvimento de SoC (System-on-Chip) robusto ? interfer?ncia eletromagn?tica ». Pontif?cia Universidade Cat?lica do Rio Grande do Sul, 2007. http://tede2.pucrs.br/tede2/handle/tede/3060.

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O ambiente eletromagn?tico em que sistemas eletr?nicos operam est? tornando-se cada vez mais hostil. A sociedade observa com bastante entusiasmo a r?pida prolifera??o de uma quantidade infind?vel de equipamentos eletr?nicos sem fio (wireless). Infelizmente, esta tend?ncia tem por conseq??ncia a polui??o de forma dram?tica do espectro de freq??ncia, e portanto, aumentando o ru?do intr?nseco do ambiente onde vivemos. Por outro lado, ? fundamental para a aceita??o e a seguran?a destes equipamentos eletr?nicos que estes n?o falhem devido ao ambiente eletromagn?tico. Assim, ? de suma import?ncia compreender como o ru?do eletromagn?tico (Electromagnetic Interference, ou EMI) impacta a confiabilidade de sistemas integrados complexos (Systems-on-Chip, ou SoC). Algumas empresas em escala mundial t?m demonstrado muita preocupa??o com este problema atrav?s do desenvolvimento de v?rias plataformas comerciais para o projeto e o teste de SoCs. Entretanto, estas plataformas n?o garantem medi??es adequadas da susceptibilidade dos sistemas eletr?nicos ? EMI. Este cen?rio nos motivou a propor uma plataforma de prototipagem reconfigur?vel para avaliar e aprimorar projetos de SoCs levando-se em considera??o sua imunidade ao ru?do eletromagn?tico. Esta plataforma ? baseada em normas internacionais IEC 62.132 para o projeto e o teste de sistemas eletr?nicos, ao n?vel de placa. O objetivo final deste conjunto de normas ? ditar regras que viabilizam a medi??o precisa da imunidade de circuitos integrados ? EMI, tanto radiada quanto conduzida. A plataforma desenvolvida ? baseada em duas placas espec?ficas e complementares. A primeira ? dedicada para o teste de imunidade ao ru?do irradiado em uma Gigahertz Transverse Electromagnetic Cell (GTEM Cell) de acordo com a norma IEC 62.132-2 (IEC, 2004). A segunda placa ? dedicada ao teste conduzido de ru?do de RF e foi implementada de acordo com as normas IEC 62.132-4 e IEC 62.132-2 (IEC, 2004), respectivamente. Ap?s o desenvolvimento da plataforma em quest?o, um estudo-de-caso baseado no processador soft-core da Xilinx, MicroBlaze, operando sob o controle do sistema operacional uCOS-II foi desenvolvido pelo Grupo SiSC e testado na plataforma. Os resultados dos ensaios s?o bastante motivadores e demonstram a capacidade e a flexibilidade da plataforma ser utilizada como ferramenta para avaliar o comportamento de SoCs em ambiente ruidoso do tipo EMI

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Rego, Rodrigo Soares de Lima S ? « Projeto e implementa??o de uma plataforma MP-SoC usando SystemC ». Universidade Federal do Rio Grande do Norte, 2006. http://repositorio.ufrn.br:8080/jspui/handle/123456789/18031.

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This work presents the concept, design and implementation of a MP-SoC platform, named STORM (MP-SoC DirecTory-Based PlatfORM). Currently the platform is composed of the following modules: SPARC V8 processor, GPOP processor, Cache module, Memory module, Directory module and two different modles of Network-on-Chip, NoCX4 and Obese Tree. All modules were implemented using SystemC, simulated and validated, individually or in group. The modules description is presented in details. For programming the platform in C it was implemented a SPARC assembler, fully compatible with gcc s generated assembly code. For the parallel programming it was implemented a library for mutex managing, using the due assembler s support. A total of 10 simulations of increasing complexity are presented for the validation of the presented concepts. The simulations include real parallel applications, such as matrix multiplication, Mergesort, KMP, Motion Estimation and DCT 2D
Este trabalho apresenta o conceito, desenvolvimento e implementa??o de uma plataforma MP-SoC, batizada STORM (MP-SoC DirecTory-Based PlatfORM). A plataforma atualmente ? composta pelos seguintes m?dulos: processador SPARC V8, processador GPOP, m?dulo de Cache, m?dulo de Mem?ria, m?dulo de Diret?rio e dois diferentes modelos de Network-on-Chip, a NoCX4 e a ?rvore Obesa. Todos os m?dulos foram implementados usando a linguagem SystemC, simulados e validados, tanto separadamente quanto em conjunto. A descri??o dos m?dulos ? apresentada em detalhes. Para a programa??o da plataforma usando C foi implementado um montador SPARC, totalmente compat?vel com o c?digo assembly gerado pelo compilador gcc. Para a programa??o concorrente foi implementada uma biblioteca de fun??es para gerenciamento de mutexes, com o devido suporte por parte do montador. S?o apresentadas 10 simula??es do sistema, de complexidade crescente, para valida??o de todos os conceitos apresentados. As simula??es incluem aplica??es paralelas reais, como a multiplica??o de matrizes, Mergesort, KMP, Estima??o de Movimento e DCT 2D

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Beasley, Alexander. « Exploring the benefits and implications of dynamic partial reconfiguration using Field Programmable Gate Array-System on Chip architectures ». Thesis, University of Bath, 2019. https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.767597.

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Demands on modern computing are becoming more intensive. Keeping up with these demands has increasing complexity. Moore's Law is in decline. Increasing the number of cores on a device has diminishing returns. Specialised architectures provide more efficient and higher performing processors. However, it is not always practical to include every architecture on every device. Running non-native tasks on architectures often results in a drop in performance. This research examines the benefits and limitations of Field Programmable Gate Arrays - Systems on Chip (FPGA-SoC) devices to provide flexible hardware accelerators for heterogeneous architectures. A number of topics are covered, including hardware acceleration of floating-point mathematical functions, dynamic reconfiguration and high-level synthesis. A number of case studies are presented. Dynamic reconfiguration is used to change the configuration of the FPGA at runtime, allowing the hardware accelerators to be changed depending on the current processor tasks. Changing accelerators at runtime has limitations, such as data perturbation. Context switching techniques are applied to the hardware to prevent loss of data and enable de-fragmentation of the FPGA. High level synthesis techniques are used in conjunction with the presented hardware accelerators to synthesise high-level languages into hardware descriptions with optimisations. Techniques for runtime synthesis of hardware accelerators are presented. These can be combined with dynamic reconfiguration to configure FPGAs with appropriate hardware accelerators from a high-level language at runtime. The research demonstrates that FPGA-SoC devices have the potential for providing reconfigurable accelerators for processors in heterogeneous architectures. Metrics show that the FPGA configurations can perform better than other commercial processors. It was demonstrated that it is possible to context switch hardware at runtime, meaning the most can be made of the FPGA-SoC at all times, even as situations change. However, there are many limitations that still need to be overcome, such as management of the implemented hardware, synthesis of new hardware at runtime, reconfiguration times, interfacing of hardware with software and the design of hardware accelerators.

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Niu, Xinwei. « System-on-a-Chip (SoC) based Hardware Acceleration in Register Transfer Level (RTL) Design ». FIU Digital Commons, 2012. http://digitalcommons.fiu.edu/etd/888.

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Today, modern System-on-a-Chip (SoC) systems have grown rapidly due to the increased processing power, while maintaining the size of the hardware circuit. The number of transistors on a chip continues to increase, but current SoC designs may not be able to exploit the potential performance, especially with energy consumption and chip area becoming two major concerns. Traditional SoC designs usually separate software and hardware. Thus, the process of improving the system performance is a complicated task for both software and hardware designers. The aim of this research is to develop hardware acceleration workflow for software applications. Thus, system performance can be improved with constraints of energy consumption and on-chip resource costs. The characteristics of software applications can be identified by using profiling tools. Hardware acceleration can have significant performance improvement for highly mathematical calculations or repeated functions. The performance of SoC systems can then be improved, if the hardware acceleration method is used to accelerate the element that incurs performance overheads. The concepts mentioned in this study can be easily applied to a variety of sophisticated software applications. The contributions of SoC-based hardware acceleration in the hardware-software co-design platform include the following: (1) Software profiling methods are applied to H.264 Coder-Decoder (CODEC) core. The hotspot function of aimed application is identified by using critical attributes such as cycles per loop, loop rounds, etc. (2) Hardware acceleration method based on Field-Programmable Gate Array (FPGA) is used to resolve system bottlenecks and improve system performance. The identified hotspot function is then converted to a hardware accelerator and mapped onto the hardware platform. Two types of hardware acceleration methods – central bus design and co-processor design, are implemented for comparison in the proposed architecture. (3) System specifications, such as performance, energy consumption, and resource costs, are measured and analyzed. The trade-off of these three factors is compared and balanced. Different hardware accelerators are implemented and evaluated based on system requirements. 4) The system verification platform is designed based on Integrated Circuit (IC) workflow. Hardware optimization techniques are used for higher performance and less resource costs. Experimental results show that the proposed hardware acceleration workflow for software applications is an efficient technique. The system can reach 2.8X performance improvements and save 31.84% energy consumption by applying the Bus-IP design. The Co-processor design can have 7.9X performance and save 75.85% energy consumption.

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Söderman, Michael. « Loss-less on-chip test response compression for diagnosis and debug in volume production of system-on-chip ». Thesis, Linköping University, Department of Computer and Information Science, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-11948.

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The technical evolution during the past decade have escalated the use of electronic devices, which are more common today than ever before. The market is still growing rapidly and will continue to do so. The reason for this is the increased demand for devices with integrated circuits. In addition to the increased volume of production, the chips are also becoming more complex which is also reflected in the requirements of the chip design process.

An advanced chip that combines several different hardware modules (cores) to form a complete system is called a System-on-Chip (SoC). It is of great importance that these chips work according to expectation, although it can be difficult to guarantee. The purpose of SoC testing is to verify correct behaviour as well as for diagnosis and debug.

Complex systems lead to more and bigger tests which lead to increased test data volume and test time. This results in a higher test cost and many methods are proposed to remedy this situation.

This report proposes a method that minimises fail result data with a real-time compression component embedded on the chip. The compressed fail results can be saved on-chip and retrieved when needed instead of during the test.

Furthermore this method will facilitate debug and diagnosis of SoCs. A mask buffer is used to give the opportunity of choosing exactly which cycles, pins or bits that are relevant. All other result bits are masked and ignored.

The results are satisfying, the data is compressed to a much smaller size which is easier to store on-chip. The method is simple, fast and loss-less.

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Noun, Ziad. « Wireless Approach for SIP and SOC Testing ». Thesis, Montpellier 2, 2010. http://www.theses.fr/2010MON20002.

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Jusqu'à présent, le test de circuits intégrés et des systèmes au niveau wafer est basé sur un contact physique entre l'équipement de test et les circuits sur le wafer. Cette méthode basée sur le contact est limitée par plusieurs facteurs, tels que le nombre de circuits testés en parallèle, la réduction de la taille et de l'espacement entre les plots de contact, le nombre de contact avant que les plots soient endommagés, le coût des opérations de test, entre autres. Pour résoudre ces problèmes, nous proposons une nouvelle approche de test basée sur la communication sans fil entre le testeur et les circuits à tester (DUT). Pour cela, un Wireless Test Control Bloc (WTCB) est ajouté à chaque DUT sur le wafer comme une interface sans fil entre le testeur et les structures de test internes du DUT. Ce WTCB intègre une pile protocolaire de communication pour gérer la communication avec le testeur, et un Test Control Bloc (TCB) pour gérer l'application de test au niveau DUT. Profitant d'une transmission sans fil, le testeur peut diffuser les données de test à tous les DUT sur le wafer , maximisant le test simultané et réduisant donc le temps de test. En outre, notre architecture de WTCB permet une comparaison locale de la réponse de DUT avec la réponse correcte attendue par le testeur. En effectuant cette comparaison dans le WTCB du DUT, le testeur recueille de chaque DUT 1 seul bit comme résultat de la comparaison, au lieu d'une réponse complète, conduisant à un test sans fil plus rapide qui réduit le temps d'essai. Le WTCB a été mis en oeuvre sur FPGA, et une épreuve de test sans fil d'un circuit réel a été réalisée, prouvant la conception efficace de notre WTCB, et soulignant le potentiel de notre méthode de test sans fil, où elle peut être étendue et utilisée pour des applications de test in situ à distance
So far, the test of integrated circuits and systems at wafer level relies on a physical contact between the test equipment and the devices under test on the wafer. This contact-based method is limited by several factors, such as the number of devices tested in parallel, the reduction of the size and the pitch of the bond pads, the number of touchdowns before bond pads are damaged, the cost of the test operations, among others. To solve these issues, we propose a novel test approach and architecture based on wireless communication between the tester and the devices under test (DUT). For that, a Wireless Test Control Block (WTCB) is added to every DUT on the wafer as a wireless interface between the tester and the internal test structures of the DUT. This WTCB embeds a communication protocol stack to manage the communication with the tester, and a Test Control Block to manage the test application at DUT level. Taking advantage of a wireless transmission, the tester can broadcast the test data to all DUT on the wafer in one path, maximizing the concurrent test, and reducing therefore the test time. Moreover, our WTCB architecture allows a local comparison of the DUT response with the correct response expected by the tester. By performing this comparison in the WTCB of the DUT, the tester collects from every DUT its 1-bit comparison result instead of a complete response, leading to a faster wireless test and extremely reduced test time. The WTCB has been implemented on FPGA, and a successful wireless test of a real circuit was performed, proving the efficient design of our WTCB, and highlighting the potential of our wireless test method, where it can be extended and used to perform a remote in-situ test

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Richard, Aliénor. « Development and validation of NESSIE : a multi-criteria performance estimation tool for SoC ». Doctoral thesis, Universite Libre de Bruxelles, 2010. http://hdl.handle.net/2013/ULB-DIPOT:oai:dipot.ulb.ac.be:2013/210044.

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The work presented in this thesis aims at validating an original multicriteria performances estimation tool, NESSIE, dedicated to the prediction of performances to accelerate the design of electronic embedded systems.

This tool has been developed in a previous thesis to cope with the limitations of existing design tools and offers a new solution to face the growing complexity of the current applications and electronic platforms and the multiple constraints they are subjected to.

More precisely, the goal of the tool is to propose a flexible framework targeting embedded systems in a generic way and enable a fast exploration of the design space based on the estimation of user-defined criteria and a joint hierarchical representation of the application and the platform.

In this context, the purpose of the thesis is to put the original framework NESSIE to the test to analyze if it is indeed useful and able to solve current design problems. Hence, the dissertation presents :

- A study of the State-of-the-Art related to the existing design tools. I propose a classification of these tools and compare them based on typical criteria. This substantial survey completes the State-of-the-Art done in the previous work. This study shows that the NESSIE framework offers solutions to the limitations of these tools.

- The framework of our original mapping tool and its calculation engine. Through this presentation, I highlight the main ingredients of the tool and explain the implemented methodology.

- Two external case studies that have been chosen to validate NESSIE and that are the core of the thesis. These case studies propose two different design problems (a reconfigurable processor, ADRES, applied to a matrix multiplication kernel and a 3D stacking MPSoC problem applied to a video decoder) and show the ability of our tool to target different applications and platforms.

The validation is performed based on the comparison of a multi-criteria estimation of the performances for a significant amount of solutions, between NESSIE and the external design flow. In particular, I discuss the prediction capability of NESSIE and the accuracy of the estimation.

-The study is completed, for each case study, by a quantification of the modeling time and the design time in both flows, in order to analyze the gain achieved by our tool used upstream from the classical tool chain compared to the existing design flow alone.

The results showed that NESSIE is able to predict with a high degree of accuracy the solutions that are the best candidates for the design in the lower design flows. Moreover, in both case studies, modeled respectively at a low and higher abstraction level, I obtained a significant gain in the design time.

However, I also identified limitations that impact the modeling time and could prevent an efficient use of the tool for more complex problems.

To cope with these issues, I end up by proposing several improvements of the framework and give perspectives to further develop the tool.
Doctorat en Sciences de l'ingénieur
info:eu-repo/semantics/nonPublished

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Nugent, Steven Paul. « A Second Generation Generic Systems Simulator (GENESYS) for a Gigascale System-on-a-Chip (SoC) ». Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/6885.

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Future opportunities for gigascale integration will be governed by a hierarchy of theoretical and practical limits that can be codified as follows: fundamental, material, device, circuit, and system. An exponential increase in on-chip integration is driving System-on-Chip (SoC) methodologies as a dominant design solution for gigascale ICs. Therefore, a second generation generic systems simulator (GENESYS) is developed to address a need for rapid assessment of technology/architecture tradeoffs for multi-billion transistor SoCs while maintaining the depth of core modeling codified in the hierarchy of limits. A newly developed system methodology incorporates a hiearchical block-based model, a dual interconnect distribution for both local and global interconnects, a generic on-chip bus model, and cell placement algorithms. A comparison of simulation results for five commercial SoC implementations shows increased accuracy in predicting die size, clock frequency, and total power dissipation. ITRS projections for future technology requirments are applied with results indicating that increasing static power dissipation is a key impediment to making continued improvements in chip performance. Additionally, simulations of a generic chip multi-processor architecture utilizing several interconnect schemes shows that the most promising candidate for the future of on-chip global interconnect networks will be hierarchical bus structures providing a high degree of connectivity while maintaining high operating frequencies.

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Castello, Charles C. « System-on-a-chip (SoC) based environmental monitoring platform for the detection of hazardous materials ». FIU Digital Commons, 2011. http://digitalcommons.fiu.edu/etd/2073.

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The purpose of this research is design considerations for environmental monitoring platforms for the detection of hazardous materials using System-on-a-Chip (SoC) design. Design considerations focus on improving key areas such as: (1) sampling methodology; (2) context awareness; and (3) sensor placement. These design considerations for environmental monitoring platforms using wireless sensor networks (WSN) is applied to the detection of methylmercury (MeHg) and environmental parameters affecting its formation (methylation) and deformation (demethylation). The sampling methodology investigates a proof-of-concept for the monitoring of MeHg using three primary components: (1) chemical derivatization; (2) preconcentration using the purge-and-trap (P&T) method; and (3) sensing using Quartz Crystal Microbalance (QCM) sensors. This study focuses on the measurement of inorganic mercury (Hg) (e.g., Hg2+) and applies lessons learned to organic Hg (e.g., MeHg) detection. Context awareness of a WSN and sampling strategies is enhanced by using spatial analysis techniques, namely geostatistical analysis (i.e., classical variography and ordinary point kriging), to help predict the phenomena of interest in unmonitored locations (i.e., locations without sensors). This aids in making more informed decisions on control of the WSN (e.g., communications strategy, power management, resource allocation, sampling rate and strategy, etc.) This methodology improves the precision of controllability by adding potentially significant information of unmonitored locations. There are two types of sensors that are investigated in this study for near-optimal placement in a WSN: (1) environmental (e.g., humidity, moisture, temperature, etc.) and (2) visual (e.g., camera) sensors. The near-optimal placement of environmental sensors is found utilizing a strategy which minimizes the variance of spatial analysis based on randomly chosen points representing the sensor locations. Spatial analysis is employed using geostatistical analysis and optimization occurs with Monte Carlo analysis. Visual sensor placement is accomplished for omnidirectional cameras operating in a WSN using an optimal placement metric (OPM) which is calculated for each grid point based on line-of-site (LOS) in a defined number of directions where known obstacles are taken into consideration. Optimal areas of camera placement are determined based on areas generating the largest OPMs. Statistical analysis is examined by using Monte Carlo analysis with varying number of obstacles and cameras in a defined space.

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Fabris, Eric Ericson. « A Modular and digitally programmable interface based on band-pass sigma-delta modulator for mixed-signal systems-on-chip ». reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2005. http://hdl.handle.net/10183/6226.

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O foco desta tese é a descrição e validação de uma arquitetura de interface para processamento de sinais analógicos para SOC de sinais mistos. A abordagem proposta apresenta a possibilidade de cobertura de uma larga faixa de freqüências com performance praticamente constante associada a uma estrutura digital de programação. A premissa é usar uma célula analógica fixa e promover a configuração da aplicação no domínio digital, levando a uma arquitetura de interface de sinais mistos. O emprego de um bloco analógico fixo busca eliminar a perda inerente de performance decorrente da própria estrutura de programação em circuitos reconfiguráveis analógicos. A emprego da programação no domínio digital abre espaço para usos da vasta gama de ferramentas disponíveis para o projeto em alto nível de abstração, simulação e síntese automática para implementar a aplicação alvo com excelente predição do desempenho final. A abordagem proposta baseia-se no conceito de translação em freqüência (mixagem) do sinal de entrada seguida pela sua conversão para o domínio ΣΔ. A estrutura de processamento possibilita o emprego de um bloco analógico constante, e também, um processamento uniforme de sinais de entrada indo de DC até altas freqüências. A aplicação é configurada no domínio ΣΔ onde a performance pode ser predita de acordo com as especificações alvo. Objetivando a exploração do espaço de projeto foi desenvolvido o modelo de performance teórico e de simulação. Os modelos desenvolvidos auxiliam no também no projeto físico da interface proposta. Objetivando, tanto a validação dos modelos propostos, bem como o desenvolvimento de aplicações, foram construídos dois protótipos. São apresentados os usos da interface como um ADC paramétrico multi-banda e como um multiplicador e um somador de sinais analógicos. É proposta também uma arquitetura para uma interface analógica multi-canal. Os resultados experimentais empregados para a caracterização da interface proposta suportam as vantagens da mesma.
The focus of this thesis is to discuss the development and modeling of an interface architecture to be employed for interfacing analog signals in mixed-signal SOC. We claim that the approach that is going to be presented is able to achieve wide frequency range, and covers a large range of applications with constant performance, allied to digital configuration compatibility. Our primary assumptions are to use a fixed analog block and to promote application configurability in the digital domain, which leads to a mixed-signal interface. The use of a fixed analog block avoids the performance loss common to configurable analog blocks. The usage of configurability on the digital domain makes possible the use of all existing tools for high level design, simulation and synthesis to implement the target application, with very good performance prediction. The proposed approach utilizes the concept of frequency translation (mixing) of the input signal followed by its conversion to the ΣΔ domain, which makes possible the use of a fairly constant analog block, and also, a uniform treatment of input signal from DC to high frequencies. The programmability is performed in the ΣΔ digital domain where performance can be closely achieved according to application specification. The interface performance theoretical and simulation model are developed for design space exploration and for physical design support. Two prototypes are built and characterized to validate the proposed model and to implement some application examples. The usage of this interface as a multi-band parametric ADC and as a two channels analog multiplier and adder are shown. The multi-channel analog interface architecture is also presented. The characterization measurements support the main advantages of the approach proposed.

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Tuna, Matthieu. « Auto-test logiciel des systèmes intégrés sur puce (SOC) ». Paris 6, 2007. http://www.theses.fr/2007PA066120.

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Ryu, Kyeong Keol. « Automated Bus Generation for Multi-processor SoC Design ». Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/5076.

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In the design of a multi-processor System-on-a-Chip (SoC), the bus architecture typically comes to the forefront because the system performance is not dependent only on the speed of the Processing Elements (PEs) but also on the bus architecture in the system. An efficient bus architecture with effective arbitration for reducing contention on the bus plays an important role in maximizing performance. Therefore, among many issues of multi-processor SoC research, we focus on two issues related to the bus architecture in this dissertation. One issue is how to quickly and easily design an efficient bus architecture for an SoC. The second issue is how to quickly explore the design space across performance influencing factors to achieve a high performance bus system. The objective of this research is to provide a Computer-Aided Design (CAD) tool with which the user can quickly explore System-on-a-Chip (SoC) bus design space in search of a high performance SoC bus system. From a straightforward description of the numbers and types of Processing Elements (PEs), non-PEs, memories and buses (including, for example, the address and data bus widths of the buses and memories), our Bus Synthesis tool, called BusSynth, generates a Register-Transfer Level (RTL) Verilog Hardware Description Language (HDL) description of the specified bus system. The user can utilize this RTL Verilog in bus-accurate simulations to more quickly arrive at an efficient bus architecture for a multi-processor SoC. The methodology we propose gives designers a great benefit in fast design space exploration of bus systems across a variety of performance influencing factors such as bus types, PE types and software programming styles (e.g., pipelined parallel fashion or functional parallel fashion). We also show that BusSynth can efficiently generate bus systems in a matter of seconds as opposed to weeks of design effort to integrate together each system component by hand. Moreover, unlike the previous related work, BusSynth can support a wide variety of PEs, memory types and bus architectures (including a hybrid bus architecture) in search of a high performance SoC.

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Barber, Kristin M. « Improving Bug Visibility using System-Level Assertions and Transactions ». University of Cincinnati / OhioLINK, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1377875020.

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Kunz, Leonardo. « Memória transacional em hardware para sistemas embarcados multiprocessados conectados por redes-em-chip ». reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2010. http://hdl.handle.net/10183/28739.

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A Memória Transacional (TM) surgiu nos últimos anos como uma nova solução para sincronização em sistemas multiprocessados de memória compartilhada, permitindo explorar melhor o paralelismo das aplicações ao evitar limitações inerentes ao mecanismo de locks. Neste modelo, o programador define regiões de código que devem executar de forma atômica. O sistema tenta executá-las de forma concorrente, e, em caso de conflito nos acessos à memória, toma as medidas necessárias para preservar a atomicidade e isolamento das transações, na maioria das vezes abortando e reexecutando uma das transações. Um dos modelos mais aceitos de memória transacional em hardware é o LogTM, implementado neste trabalho em um MPSoC embarcado que utiliza uma NoC para interconexão. Os experimentos fazem uma comparação desta implementação com locks, levando-se em consideração performance e energia do sistema. Além disso, este trabalho mostra que o tempo que uma transação espera para reiniciar sua execução após ter abortado (chamado de backoff delay on abort) tem impactos significativos na performance e energia. Uma análise deste impacto é feita utilizando-se de três políticas de backoff. Um mecanismo baseado em um handshake entre transações, chamado Abort handshake, é proposto como solução para o problema. Os resultados dos experimentos são dependentes da aplicação e configuração do sistema e indicam ganhos da TM na maioria dos casos em relação ao mecanismo de locks. Houve redução de até 30% no tempo de execução e de até 32% na energia de aplicações de baixa demanda de sincronização. Em um segundo momento, é feita uma análise do backoff delay on abort na performance e energia de aplicações utilizando três políticas de backoff em comparação com o mecanismo Abort handshake. Os resultados mostram que o mecanismo proposto apresenta redução de até 20% no tempo de execução e de até 53% na energia comparado à melhor política de backoff dentre as analisadas. Para aplicações com alta demanda de sincronização, a TM mostra redução no tempo de execução de até 63% e redução de energia de até 71% em comparação com o mecanismo de locks.
Transactional Memory (TM) has emerged in the last years as a new solution for synchronization on shared memory multiprocessor systems, allowing a better exploration of the parallelism of the applications by avoiding inherent limitations of the lock mechanism. In this model, the programmer defines regions of code, called transactions, to execute atomically. The system tries to execute transactions concurrently, but in case of conflict on memory accesses, it takes the appropriate measures to preserve the atomicity and isolation, usually aborting and re-executing one of the transactions. One of the most accepted hardware transactional memory model is LogTM, implemented in this work in an embedded MPSoC that uses an NoC as interconnection mechanism. The experiments compare this implementation with locks, considering performance and energy. Furthermore, this work shows that the time a transaction waits to restart after abort (called backoff delay on abort) has significant impact on performance and energy. An analysis of this impact is done using three backoff policies. A novel mechanism based on handshake of transactions, called Abort handshake, is proposed as a solution to this issue. The results of the experiments depends on application and system configuration and show TM benefits in most cases in comparison to the locks mechanism, reaching reduction on the execution time up to 30% and reduction on the energy consumption up to 32% on low contention workloads. After that, an analysis of the backoff delay on abort on the performance and energy is presented, comparing to the Abort handshake mechanism. The proposed mechanism shows reduction of up to 20% on the execution time and up to 53% on the energy, when compared to the best backoff policy. For applications with a high degree of synchronization, TM shows reduction on the execution time up to 63% and energy savings up to 71% compared to locks.

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Ljungberg, Jan. « SYSTEM ON CHIP : Fördelar i konstruktion med system on chip i förhållande till fristående FPGA och processor ». Thesis, Tekniska Högskolan, Högskolan i Jönköping, JTH, Data- och elektroteknik, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:hj:diva-28263.

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In this exam project the investigation has been done to determine, which profits that can be made by switching an internal bus between two chips, one FPGA and a processor, to an internal bus implemented on only one chip, System on Chip. The work is based on measurements made in real time in Xilinx’s development tools on different buses, AXI4 and AXI4-Light connected to AXI3. The port that is used is FPGA’s own GP-port. Besides measuring the time of transactions also physical aspects have been investigated in this project: space, costs and time. Based on those criteria a comparison to the original construction was made to determine which benefits that can be achieved. The work has shown a number of results that are in comparison with the original construction. The System on Chip has turned out to be a better solution in most cases. When using the AXI4-Light-bus the benefits were not as obvious. Cosmic radiation, temperature or humidity are beyond the scope of this investigation. In the work the hypothetic deductive method has been used to prove that the System on Chip is faster than the original design. In this method three statements must be set up against each other; one statement that ought to be true, one statement that is a contradiction and a conclusion of what is proved. The pre-study pointed out that the System on Chip is a faster solution than the original construction. The method is useful since it proves that the pre-study is comparable to the measured results.
I detta examensarbete har undersökningar gjorts för att fastställa vilka vinster som går att göra genom att byta en internbuss mellan två chip, en FPGA och en processor, mot en intern buss implementerat på ett enda chip, System on Chip. Arbetet bygger på mätningar gjorda i realtid i Xilinx utvecklingsverktyg på olika bussar, AXI4 och AXI4‑Lite som är kopplade internt mot AXI3. Den port som används är FPGAs egen GP‑port. Förutom att mäta överföringshastigheterna, har även fysiska aspekter som utrymme, kostnader och utvecklingstid undersökts. Utifrån dessa kriterier har en jämförelse gjorts med den befintliga konstruktionen för att fastställa vilka vinster som går att uppnå. Arbetet har resulterat i ett antal resultat som är ställda mot de förutsättningar som fanns i den ursprungliga lösningen. I de flesta fall visar resultatet att ett System on Chip är en bättre lösning. De fall som var tveksamma var vid viss typ av överföring med AXI4‑Lite bussen. I arbetet har inte undersökning av kosmisk strålning, temperatur eller luftfuktighet betraktas. I arbetet med att försöka att bevisa att ett System on Chip är snabbare än den ursprungliga uppsättningen har utvecklingsmetoden hypotetisk deduktiv använts. Denna metod bygger på att man från början sätter upp ett påstående, som man förutsätter är sant, följt av en konjunktion, som inte får inträffa, för att slutligen dra en slutsats, som konstaterar fakta. Eftersom fakta som lästes in i början av arbetet pekade på att ett System on Chip var en snabbare och billigare lösning kändes metoden användbar. Under arbetets gång har det visat sig vara en bra metod som också ger ett resultat där sannolikheten för att det är en snabbare lösning ökar. Däremot säger inte metoden att det är helt säkert att den i alla situationer är bättre, vilket kan ändras om man använder andra förutsättningar eller tar med andra aspekter.

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Garzon, Johan Sebastian Eslava. « Estimativas de desempenho da estrutura de comunicação de SoC a partir de modelos de transações ». Universidade de São Paulo, 2009. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-20072009-165919/.

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A complexidade crescente (tanto da funcionalidade como da arquitetura) dos sistemas eletrônicos digitais sobre silício (conhecidos na literatura como System-on-Chip, SoC) exige novas metodologias que permitam diminuir seu tempo de desenvolvimento. O projeto no nível de sistemas (SLD) é proposto para aumentar a eficiência do projeto de SoC. SLD exige novas linguagens (como SystemC) e níveis de abstração (como TLM). A estrutura de comunicação (EC) de um SoC tem apresentado uma crescente importância devido à presença de uma maior quantidade (e funcionalidade) dos módulos a serem comunicados. Portanto, a EC apresenta um grande impacto no desempenho global do SoC. Nesta tese é proposta uma metodologia de projeto da EC chamada de MaLOC (Multi- Abstraction Level On-Chip communications structure design) que é baseada num enfoque top-down que percorre três níveis de transações (TLM). A tomada de decisões é feita utilizando-se duas importantes características que dão a originalidade a nossa proposta: 1) baseadas num conjunto de diversas métricas de desempenho que permite obter resultados mais confiáveis. 2) decisões ASAP (o mais rápido possível), antecipando a tomada de decisões utilizando níveis mais abstratos do que o RTL, permitindo diminuir o tempo de projeto da EC. Para validar a proposta uma série de análises de fidelidade foram realizadas, os resultados indicaram fidelidades maiores do que 96% e em cenários extremos maiores do que 72%. Adicionalmente os tempos de simulação no nível TLM atemporal foi até 2,6 vezes mais rápido do que o nível TLM de precisão de transferências, que foi até 1,6 vezes mais rápido do que o nível TLM de ciclos de relógio (menos abstrato). Estes resultados indicam a validade da metodologia para realizar a tomada de decisões, permitindo uma melhor exploração do espaço de projeto Os estudos de caso permitiram observar que além de configurar a EC procurando o melhor desempenho, MaLOC identificou soluções com menor consumo de energia, através do uso de um conjunto diverso de métricas, e configuração de parâmetros do sistema (tamanho da memória). Estas duas situações indicam o potencial que a metodologia apresenta para o projeto de diferentes tipos de EC, assim como de diferentes componentes de um SoC.
Modern and future System on Chip design requires several methodologies in order to handle their growing complexity (of both functional and architectural issues). System Level Design has emerged as a solution to handle the complex of nowadays and future SoC designs, increasing their efficiency and reducing the time to market. SLD requires new modeling languages (such as SystemC) and abstraction levels (such as Transaction Level Modeling - TLM). The integration of very different and composite IP cores into a SoC makes their physical and logical integration a very difficult task. Hence, the communication structure (CS) presents a significant impact on the SOC global performance. This thesis proposes a novel methodology named MaLOC (Multi-Abstraction Level On- Chip communications structure design) that uses a top-down approach. The parameters configuration is driven by two important considerations: 1) performance metrics based, this enables to obtain a most reliable solution; 2) an ASAP configuration schedule, this enables to reduce the CS design time through the use of higher abstraction levels. A fidelity test was performed. The results showed that in extreme conditions (such as burst size higher than time between transactions) the fidelity obtained was higher than 72%. In normal cases (burst size similar to the time between transactions) the fidelity was higher than 96%. The simulations execution times were compared among the three TLM levels and the results showed that TLM untimed simulations were 2.6 times faster than the TLM transfer accurate, also these were 1.6 times faster than the TLM cycle accurate. This means that TLM untimed simulations are 4 times faster than TLM Cycle accurate, enabling a enhanced space design exploration. The case studies performed showed that MaLOC can be useful to identify solutions that satisfy the performance required reducing the power consumption (reducing activities across the bus). Also, a system parameter was defined using the methodology (memory banks). These two situations indicate the MaLOC potential to design several CS types and SoC configuration parameters.

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Akgul, Bilge Ebru Saglam. « The System-on-a-Chip Lock Cache ». Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/5253.

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In this dissertation, we implement efficient lock-based synchronization by a novel, high performance, simple and scalable hardware technique and associated software for a target shared-memory multiprocessor System-on-a-Chip (SoC). The custom hardware part of our solution is provided in the form of an intellectual property (IP) hardware unit which we call the SoC Lock Cache (SoCLC). SoCLC provides effective lock hand-off by reducing on-chip memory traffic and improving performance in terms of lock latency, lock delay and bandwidth consumption. The proposed solution is independent from the memory hierarchy, cache protocol and the processor architectures used in the SoC, which enables easily applicable implementations of the SoCLC (e.g., as a reconfigurable or partially/fully custom logic), and which distinguishes SoCLC from previous approaches. Furthermore, the SoCLC mechanism has been extended to support priority inheritance with an immediate priority ceiling protocol (IPCP) implemented in hardware, which enhances the hard real-time performance of the system. Our experimental results in a four-processor SoC indicate that SoCLC can achieve up to 37% overall speedup over spin-lock and up to 48% overall speedup over MCS for a microbenchmark with false sharing. The priority inheritance implemented as part of the SoCLC hardware, on the other hand, achieves 1.43X speedup in overall execution time of a robot application when compared to the priority inheritance implementation under the Atalanta real-time operating system. Furthermore, it has been shown that with the IPCP mechanism integrated into the SoCLC, all of the tasks of the robot application could meet their deadlines (e.g., a high priority task with 250us worst case response time could complete its execution in 93us with SoCLC, however the same task missed its deadline by completing its execution in 283us without SoCLC). Therefore, with IPCP support, our solution can provide better real-time guarantees for real-time systems. To automate SoCLC design, we have also developed an SoCLC-generator tool, PARLAK, that generates user specified configurations of a custom SoCLC. We used PARLAK to generate SoCLCs from a version for two processors with 32 lock variables occupying 2,520 gates up to a version for fourteen processors with 256 lock variables occupying 78,240 gates.

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Vogelsang, Stefan, Steffen Köhler et Rainer G. Spallek. « Analyse von Test-Pattern für SoC Multiprozessortest und -debugging mittels Test Access Port (JTAG) ». Universitätsbibliothek Chemnitz, 2007. http://nbn-resolving.de/urn:nbn:de:swb:ch1-200701007.

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Bei der Entwickelung von System-on-Chip (SoC) Debuggern ist es leider hinreichend oft erforderlich den Debugger selbst auf mögliche Fehler zu untersuchen. Da alle ernstzunehmenden Debugger konstruktionsbedingt selbst ein eingebettetes System darstellen, erwächst die Notwendigkeit eine einfache und sicher kontrollierbare Diagnose-Hardware zu entwerfen, welche den Zugang zur Funktionsweise des Debuggers über seine Ausgänge erschließt. Derzeitig ist der Test Access Port (TAP nach IEEE 1149.1-Standard) für viele Integratoren die Grundlage für den Zugriff auf ihre instanzierte Hardware. Selbst in forschungsorientierten Multi- Core System-on-Chip Architekturen wie dem ARM11MP der Firma ARM wird dieses Verfahren noch immer eingesetzt. In unserem Beitrag möchten wir ein Spezialwerkzeug zur Analyse des TAPKommunikationsprotokolles vorstellen, welches den Einsatz teurer Analysetechnik (Logik- Analysatoren) unnötig werden lässt und darüber hinaus eine komfortable, weitergehende Unterstützung für Multi-Core-Systeme bietet. Aufbauend auf der Problematik der Abtastung und Erfassung der Signalzustände am TAP mittels FPGA wird auf die verschiedenen Visualisierungs- und Analyseaspekte der TAPProtokollphasen in einer Multi-Core-Prozessor-Zielsystemumgebung eingegangen. Die hier vorgestellte Lösung ist im Rahmen eines FuE-Verbundprojektes enstanden. Das Vorhaben wird im Rahmen der Technologieförderung mit Mitteln des Europäischen Fonds für regionale Entwicklung (EFRE) 2000-2006 und mit Mitteln des Freistaates Sachsen gefördert.

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Ara?jo, S?lvio Roberto Fernandes de. « Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores : sistema IPNoSys ». Universidade Federal do Rio Grande do Norte, 2008. http://repositorio.ufrn.br:8080/jspui/handle/123456789/17969.

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Made available in DSpace on 2014-12-17T15:47:45Z (GMT). No. of bitstreams: 1 SilvioRFA.pdf: 3522539 bytes, checksum: 0e7ac6eda46a29d5f5968d779986fb03 (MD5) Previous issue date: 2008-04-11
The increase of capacity to integrate transistors permitted to develop completed systems, with several components, in single chip, they are called SoC (System-on-Chip). However, the interconnection subsystem cans influence the scalability of SoCs, like buses, or can be an ad hoc solution, like bus hierarchy. Thus, the ideal interconnection subsystem to SoCs is the Network-on-Chip (NoC). The NoCs permit to use simultaneous point-to-point channels between components and they can be reused in other projects. However, the NoCs can raise the complexity of project, the area in chip and the dissipated power. Thus, it is necessary or to modify the way how to use them or to change the development paradigm. Thus, a system based on NoC is proposed, where the applications are described through packages and performed in each router between source and destination, without traditional processors. To perform applications, independent of number of instructions and of the NoC dimensions, it was developed the spiral complement algorithm, which finds other destination until all instructions has been performed. Therefore, the objective is to study the viability of development that system, denominated IPNoSys system. In this study, it was developed a tool in SystemC, using accurate cycle, to simulate the system that performs applications, which was implemented in a package description language, also developed to this study. Through the simulation tool, several result were obtained that could be used to evaluate the system performance. The methodology used to describe the application corresponds to transform the high level application in data-flow graph that become one or more packages. This methodology was used in three applications: a counter, DCT-2D and float add. The counter was used to evaluate a deadlock solution and to perform parallel application. The DCT was used to compare to STORM platform. Finally, the float add aimed to evaluate the efficiency of the software routine to perform a unimplemented hardware instruction. The results from simulation confirm the viability of development of IPNoSys system. They showed that is possible to perform application described in packages, sequentially or parallelly, without interruptions caused by deadlock, and also showed that the execution time of IPNoSys is more efficient than the STORM platform
O aumento na capacidade de integra??o de transistores permitiu o desenvolvimento de sistemas completos, com in?meros componentes, dentro de um ?nico chip, s?o os chamados SoCs (System-on-Chip). No entanto, o subsistema de interconex?o utilizado pode limitar a escalabilidade dos SoCs, como os barramentos, ou ser uma solu??o ad hoc, como a hierarquia de barramentos. Desse modo, a solu??o ideal para interconex?o no SoCs s?o as redes em chip ou NoCs (Network-on-Chip). As NoCs permitem m?ltiplas conex?o ponto-a-ponto entre os componente e podem ser reusadas em projetos diversos. Entretanto, o uso de NoCs pode representar o aumento na complexidade do projeto do sistema, da ?rea em chip e/ou pot?ncia dissipada. Dessa forma, ? necess?rio ampliar o horizonte de utiliza??o dos sistemas ou quebrar o paradigma do seu desenvolvimento. Assim, ? proposto um sistema baseado em uma NoC, onde as aplica??es s?o descritas em forma de pacotes e executadas de roteador em roteador durante o percurso entre origem e destino dos pacotes, sem a necessidade do uso de processadores convencionais. Para permitir a execu??o de aplica??es, independente do n?mero de instru??es e das dimens?es da rede, foi desenvolvido o algoritmo spiral complement, que permite re-rotear pacotes at? que todas as instru??es contidas nele sejam executadas. Portanto, o objetivo desse trabalho foi estudar a viabilidade do desenvolvimento de tal sistema, denominado sistema IPNoSys. Nesse estudo, foi desenvolvida em SystemC, com precis?o de ciclo, uma ferramenta para simula??o do sistema, a qual permite executar aplica??es implementadas na linguagem de descri??o de pacotes, tamb?m desenvolvida para esse fim. Atrav?s da ferramenta podem ser obtidos diversos resultados que permitem avaliar o funcionamento e desempenho do sistema. A metodologia empregada para descri??o das aplica??es corresponde, a priori, em obter o grafo de fluxo de dados da aplica??o em alto n?vel, e desse grafo descrev?-la em um ou mais pacotes. Utilizando essa metodologia, foram realizados tr?s estudos de casos: contador, DCT-2D e adi??o de ponto flutuante. O contador foi usado para avaliar a capacidade do sistema em tratar situa??es de deadlock e executar aplica??es em paralelo. A DCT-2D foi utilizada para realizar compara??es com a plataforma STORM. E, finalmente, a adi??o de ponto flutuante teve como objetivo ser usada como rotina de tratamento de uma instru??o n?o implementada em hardware. Os resultados de simula??o apontam favoravelmente com rela??o ? viabilidade do desenvolvimento do sistema IPNoSys. Mostrando que ? poss?vel executar aplica??es em forma de pacotes, inclusive paralelamente, sem interrup??es provocadas por eventuais deadlocks, e ainda indicam maior efici?ncia do sistema IPNoSys a respeito do tempo de execu??o comparada a plataforma STORM

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Yang, Xiaokun. « A High Performance Advanced Encryption Standard (AES) Encrypted On-Chip Bus Architecture for Internet-of-Things (IoT) System-on-Chips (SoC) ». FIU Digital Commons, 2016. http://digitalcommons.fiu.edu/etd/2477.

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With industry expectations of billions of Internet-connected things, commonly referred to as the IoT, we see a growing demand for high-performance on-chip bus architectures with the following attributes: small scale, low energy, high security, and highly configurable structures for integration, verification, and performance estimation. Our research thus mainly focuses on addressing these key problems and finding the balance among all these requirements that often work against each other. First of all, we proposed a low-cost and low-power System-on-Chips (SoCs) architecture (IBUS) that can frame data transfers differently. The IBUS protocol provides two novel transfer modes – the block and state modes, and is also backward compatible with the conventional linear mode. In order to evaluate the bus performance automatically and accurately, we also proposed an evaluation methodology based on the standard circuit design flow. Experimental results show that the IBUS based design uses the least hardware resource and reduces energy consumption to a half of an AMBA Advanced High-Performance Bus (AHB) and Advanced eXensible Interface (AXI). Additionally, the valid bandwidth of the IBUS based design is 2.3 and 1.6 times, respectively, compared with the AHB and AXI based implementations. As IoT advances, privacy and security issues become top tier concerns in addition to the high performance requirement of embedded chips. To leverage limited resources for tiny size chips and overhead cost for complex security mechanisms, we further proposed an advanced IBUS architecture to provide a structural support for the block-based AES algorithm. Our results show that the IBUS based AES-encrypted design costs less in terms of hardware resource and dynamic energy (60.2%), and achieves higher throughput (x1.6) compared with AXI. Effectively dealing with the automation in design and verification for mixed-signal integrated circuits is a critical problem, particularly when the bus architecture is new. Therefore, we further proposed a configurable and synthesizable IBUS design methodology. The flexible structure, together with bus wrappers, direct memory access (DMA), AES engine, memory controller, several mixed-signal verification intellectual properties (VIPs), and bus performance models (BPMs), forms the basic for integrated circuit design, allowing engineers to integrate application-specific modules and other peripherals to create complex SoCs.

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Chehaimi, Omar. « Parallelizzazione dell'algoritmo di ricostruzione di Feldkamp-Davis-Kress per architetture Low-Power di tipo System-On-Chip ». Master's thesis, Alma Mater Studiorum - Università di Bologna, 2017. http://amslaurea.unibo.it/13918/.

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In questa tesi,svolta presso il CNAF,si presentano i risultati ottenuti nel lavoro svolto per la parallelizzazione in CUDA dell'algoritmo di ricostruzione tomografica di Feldkamp-Davis-Kress (FDK),sulla base del software in versione sia sequenziale che parallela MPI,sviluppato presso i laboratori del X-ray Imaging Group.Gli obbiettivi di questo lavoro sono principalmente due:ridurre in modo sensibile i tempi di esecuzione dell'algoritmo di ricostruzione FDK parallelizzando su Graphics Processing Unit (GPU) e valutare,su diverse tipologie di architetture,i consumi energetici.Le piattaforme prese in esame sono:SoC (System-on-Chip) low-power, architetture a basso consumo energetico ma a limitata potenza di calcolo,e High Performance Computing (HPC),caratterizzate da un'elevata potenza di calcolo ma con un ingente consumo energetico.Si vuole mettere in risalto la differenza di prestazioni in relazione al tipo di architettura e rispetto al relativo consumo energetico.Poter sostituire nodi HPC con schede SoC low-power presenta il vantaggio di ridurre i consumi, la complessità dell'hardware e la possibilità di ottenere dei risultati direttamente in loco.I risultati ottenuti mostrano che la parallelizzazione di FDK su GPU sia la scelta più efficiente. Risulta infatti sempre,e su ogni architettura testata,più performante rispetto alla versione MPI,nonostante in quest'ultima venga parallelizzato tutto l'algoritmo.In CUDA invece si parallelizza solo la fase di ricostruzione.Inoltre si è risusciti a raggiungere un'efficienza di utilizzo della GPU del 100%.L'efficienza energetica rapportata alle prestazioni in termini di tempo è migliore per le architetture SoC rispetto a quelle HPC.Si propone infine un approccio ibrido MPI unito a CUDA che migliora ulteriormente le prestazioni di esecuzione.Il filtraggio e la ricostruzione sono operazioni indipendenti,si utilizza allora l'implementazione più efficiente per la data operazione,filtrare in MPI e ricostruire in CUDA.

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Pereira, Fábio Dacêncio. « Proposta e implementação de uma Camada de Integração de Serviços de Segurança (CISS) em SoC e multiplataforma ». Universidade de São Paulo, 2009. http://www.teses.usp.br/teses/disponiveis/3/3142/tde-18122009-124154/.

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As redes de computadores são ambientes cada vez mais complexos e dotados de novos serviços, usuários e infra-estruturas. A segurança e a privacidade de informações tornam-se fundamentais para a evolução destes ambientes. O anonimato, a fragilidade e outros fatores muitas vezes estimulam indivíduos mal intencionados a criar ferramentas e técnicas de ataques a informações e a sistemas computacionais. Isto pode gerar desde pequenas inconveniências até prejuízos financeiros e morais. Nesse sentido, a detecção de intrusão aliada a outras ferramentas de segurança pode proteger e evitar ataques maliciosos e anomalias em sistemas computacionais. Porém, considerada a complexidade e robustez de tais sistemas, os serviços de segurança muitas vezes não são capazes de analisar e auditar todo o fluxo de informações, gerando pontos falhos de segurança que podem ser descobertos e explorados. Neste contexto, esta tese de doutorado propõe, projeta, implementa e analisa o desempenho de uma camada de integração de serviços de segurança (CISS). Na CISS foram implementados e integrados serviços de segurança como Firewall, IDS, Antivírus, ferramentas de autenticação, ferramentas proprietárias e serviços de criptografia. Além disso, a CISS possui como característica principal a criação de uma estrutura comum para armazenar informações sobre incidentes ocorridos em um sistema computacional. Estas informações são consideradas como a fonte de conhecimento para que o sistema de detecção de anomalias, inserido na CISS, possa atuar com eficiência na prevenção e proteção de sistemas computacionais detectando e classificando prematuramente situações anômalas. Para isso, foram criados modelos comportamentais com base nos conceitos de Modelo Oculto de Markov (HMM) e modelos de análise de seqüências anômalas. A CISS foi implementada em três versões: (i) System-on-Chip (SoC), (ii) software JCISS em Java e (iii) simulador. Resultados como desempenho temporal, taxas de ocupação, o impacto na detecção de anomalias e detalhes de implementação são apresentados, comparados e analisados nesta tese. A CISS obteve resultados expressivos em relação às taxas de detecção de anomalias utilizando o modelo MHMM, onde se destacam: para ataques conhecidos obteve taxas acima de 96%; para ataques parciais por tempo, taxas acima de 80%; para ataques parciais por seqüência, taxas acima de 96% e para ataques desconhecidos, taxas acima de 54%. As principais contribuições da CISS são a criação de uma estrutura de integração de serviços de segurança e a relação e análise de ocorrências anômalas para a diminuição de falsos positivos, detecção e classificação prematura de anormalidades e prevenção de sistemas computacionais. Contudo, soluções foram criadas para melhorar a detecção como o modelo seqüencial e recursos como o subMHMM, para o aprendizado em tempo real. Por fim, as implementações em SoC e Java permitiram a avaliação e utilização da CISS em ambientes reais.
Computer networks are increasingly complex environments and equipped with new services, users and infrastructure. The information safety and privacy become fundamental to the evolution of these environments. The anonymity, the weakness and other factors often encourage people to create malicious tools and techniques of attacks to information and computer systems. It can generate small inconveniences or even moral and financial damage. Thus, the detection of intrusion combined with other security tools can protect and prevent malicious attacks and anomalies in computer systems. Yet, considering the complexity and robustness of these systems, the security services are not always able to examine and audit the entire information flow, creating points of security failures that can be discovered and explored. Therefore, this PhD thesis proposes, designs, implements and analyzes the performance of an Integrated Security Services Layer (ISSL). So several security services were implemented and integrated to the ISSL such as Firewall, IDS, Antivirus, authentication tools, proprietary tools and cryptography services. Furthermore, the main feature of our ISSL is the creation of a common structure for storing information about incidents in a computer system. This information is considered to be the source of knowledge so that the system of anomaly detection, inserted in the ISSL, can act effectively in the prevention and protection of computer systems by detecting and classifying early anomalous situations. In this sense, behavioral models were created based on the concepts of the Hidden Markov Model (MHMM) and models for analysis of anomalous sequences. The ISSL was implemented in three versions: (i) System-on-Chip (SoC), (ii) JCISS software in Java and (iii) one simulator. Results such as the time performance, occupancy rates, the impact on the detection of anomalies and details of implementation are presented, compared and analyzed in this thesis. The ISSL obtained significant results regarding the detection rates of anomalies using the model MHMM, which are: for known attacks, rates of over 96% were obtained; for partial attacks by a time, rates above 80%, for partial attacks by a sequence, rates were over 96% and for unknown attacks, rates were over 54%. The main contributions of ISSL are the creation of a structure for the security services integration and the relationship and analysis of anomalous occurrences to reduce false positives, early detection and classification of abnormalities and prevention of computer systems. Furthermore, solutions were figured out in order to improve the detection as the sequential model, and features such as subMHMM for learning at real time. Finally, the SoC and Java implementations allowed the evaluation and use of the ISSL in real environments.

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Montcalm, Michael R. « Scheduling Algorithms for Instruction Set Extended Symmetrical Homogeneous Multiprocessor Systems-on-Chip ». Thèse, Université d'Ottawa / University of Ottawa, 2011. http://hdl.handle.net/10393/20056.

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Embedded system designers face multiple challenges in fulfilling the runtime requirements of programs. Effective scheduling of programs is required to extract as much parallelism as possible. These scheduling algorithms must also improve speedup after instruction-set extensions have occurred. Scheduling of dynamic code at run time is made more difficult when the static components of the program are scheduled inefficiently. This research aims to optimize a program’s static code at compile time. This is achieved with four algorithms designed to schedule code at the task and instruction level. Additionally, the algorithms improve scheduling using instruction set extended code on symmetrical homogeneous multiprocessor systems. Using these algorithms, we achieve speedups up to 3.86X over sequential execution for a 4-issue 2-processor system, and show better performance than recent heuristic techniques for small programs. Finally, the algorithms generate speedup values for a 64-point FFT that are similar to the test runs.

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Bahmani, Maryam. « Exploration architecturale et étude des performances des réseaux sur puce 3D partiellement connectés verticalement ». Thesis, Grenoble, 2013. http://www.theses.fr/2013GRENM066/document.

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L'utilisation de la troisième dimension peut entraîner une réduction significative de la puissance et de la latence moyenne du trafic dans les réseaux sur puce (Network-on-Chip). La technologie des vias à travers le substrat (ou Through-Silicon Via) est la technologie la plus prometteuse pour l'intégration 3D, car elle offre des liens verticaux courts qui remédient au problème des longs fils dans les NoCs-2D. Les TSVs sont cependant énormes et les processus de fabrication sont immatures, ce qui réduit le rendement des systèmes sur puce à base de NoC-3D. Par conséquent, l'idée de réseaux sur puce 3D partiellement connectés verticalement a été introduite pour bénéficier de la technologie 3D tout en conservant un haut rendement. En outre, de tels réseaux sont flexibles, car le nombre, l'emplacement et l'affectation des liens verticaux dans chaque couche peuvent être décidés en fonction des exigences de l'application. Cependant, ce type de réseaux pose un certain nombre de défis : Le routage est le problème majeur, car l'élimination de certains liens verticaux fait que l'on ne peut utiliser les algorithmes classiques qui suivent l'ordre des dimensions. Pour répondre à cette question nous expliquons et évaluons un algorithme de routage déterministe appelé “Elevator First”, qui garanti d'une part que si un chemin existe, alors on le trouve, et que d'autre part il n'y aura pas d'interblocages. Fondamentalement, la performance du NoC est affecté par a) la micro architecture des routeurs et b) l'architecture d'interconnexion. L'architecture du routeur a un effet significatif sur la performance du NoC, à cause de la latence qu'il induit. Nous présentons la conception et la mise en œuvre de la micro-architecture d'un routeur à faible latence implantantl'algorithme de routage Elevator First, qui consomme une quantité raisonnable de surface et de puissance. Du point de vue de l'architecture, le nombre et le placement des liens verticaux ont un rôle important dans la performance des réseaux 3D partiellement connectés verticalement, car ils affectent le nombre moyen de sauts et le taux d'utilisation des FIFOs dans le réseau. En outre, l'affectation des liens verticaux vers les routeurs qui n'ont pas de ports vers le haut ou/et le bas est une question importante qui influe fortement sur les performances. Par conséquent, l'exploration architecturale des réseaux sur puce 3D partiellement connectés verticalement est importante. Nous définissons, étudions et évaluons des paramètres qui décrivent le comportement du réseau, de manière à déterminer le placement et l'affectation des liens verticaux dans les couches de manière simple et efficace. Nous proposons une méthode d'estimation quadratique visantà anticiper le seuil de saturation basée sur ces paramètres
Utilization of the third dimension can lead to a significant reduction in power and average hop-count in Networks- on-Chip (NoC). TSV technology, as the most promising technology in 3D integration, offers short and fast vertical links which copes with the long wire problem in 2D NoCs. Nonetheless, TSVs are huge and their manufacturing process is still immature, which reduces the yield of 3D NoC based SoC. Therefore, Vertically-Partially-Connected 3D-NoC has been introduced to benefit from both 3D technology and high yield. Moreover, Vertically-Partially-Connected 3D-NoC is flexible, due to the fact that the number, placement, and assignment of the vertical links in each layer can be decided based on the limitations and requirements of the design. However, there are challenges to present a feasible and high-performance Vertically-Partially-Connected Mesh-based 3D-NoC due to the removed vertical links between the layers. This thesis addresses the challenges of Vertically-Partially-Connected Mesh-based 3D-NoC: Routing is the major problem of the Vertically-Partially-Connected 3D-NoC. Since some vertical links are removed, some of the routers do not have up or/and down ports. Therefore, there should be a path to send a packet to upper or lower layer which obviously has to be determined by a routing algorithm. The suggested paths should not cause deadlock through the network. To cope with this problem we explain and evaluate a deadlock- and livelock-free routing algorithm called Elevator First. Fundamentally, the NoC performance is affected by both 1) micro-architecture of routers and 2) architecture of interconnection. The router architecture has a significant effect on the performance of NoC, as it is a part of transportation delay. Therefore, the simplicity and efficiency of the design of NoC router micro architecture are the critical issues, especially in Vertically-Partially-Connected 3D-NoC which has already suffered from high average latency due to some removed vertical links. Therefore, we present the design and implementation the micro-architecture of a router which not only exactly and quickly transfers the packets based on the Elevator First routing algorithm, but it also consumes a reasonable amount of area and power. From the architecture point of view, the number and placement of vertical links have a key role in the performance of the Vertically-Partially-Connected Mesh-based 3D-NoC, since they affect the average hop-count and link and buffer utilization in the network. Furthermore, the assignment of the vertical links to the routers which do not have up or/and down port(s) is an important issue which influences the performance of the 3D routers. Therefore, the architectural exploration of Vertically-Partially-Connected Mesh-based 3D-NoC is both important and non-trivial. We define, study, and evaluate the parameters which describe the behavior of the network. The parameters can be helpful to place and assign the vertical links in the layers effectively. Finally, we propose a quadratic-based estimation method to anticipate the saturation threshold of the network's average latency

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Mahmood, Adnan, et Zaheer Ahmed Mohammed. « DESIGN AND PROTOTYPE OF RESOURCE NETWORK INTERFACES FOR NETWORK ON CHIP ». Thesis, Jönköping University, JTH, Computer and Electrical Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:hj:diva-11114.

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Network on Chip (NoC) has emerged as a competitive and efficient communication infrastructure for the core based design of System on Chip. Resource (core), router and interface between router and core are the three main parts of a NoC. Each core communicates with the network through the interface, also called Resource Network Interface (RNI). One approach to speed up the design at NoC based systems is to develop standardized RNI. Design of RNI depends to some extent on the type of routing technique used in NoC. Control of route decision base the categorization of source and distributed routing algorithms. In source routing a complete path to the destination is provided in the packet header at the source, whereas in distributed routing, the path is dynamically computed in routers as the packet moves through the network. Buffering, flitization, deflitization and transfer of data from core to router and vice versa, are common responsibilities of RNI in both types of routing. In source routing, RNI has an extra functionality of storing complete paths to all destinations in tables, extracting path to reach a desired destination and adding it in the header flit. In this thesis, we have made an effort towards designing and prototyping a standardized and efficient RNI for both source and distributed routing. VHDL is used as a design language and prototyping of both types RNI has been carried out on Altera DE2 FPGA board. Testing of RNI was conducted by using Nios II soft core. Simulation results show that the best case flit latency, for both types RNI is 4 clock cycles. RNI design is also resource efficient because it consumes only 2% of the available resources on the target platform.

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Shalan, Mohamed A. « Dynamic memory management for embedded real-time multiprocessor system-on-a-chip ». Diss., Available online, Georgia Institute of Technology, 2003:, 2003. http://etd.gatech.edu/theses/available/etd-11252003-131621/unrestricted/shalanmohameda200312.pdf.

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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2004.
Vincent Mooney, Committee Chair; John Barry, Committee Member; James Hamblen, Committee Member; Karsten Schwan, Committee Member; Linda Wills, Committee Member. Includes bibliography.

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Noun, Ziad. « Méthode de test sans fil en vue des SIP et des SOC ». Phd thesis, Université Montpellier II - Sciences et Techniques du Languedoc, 2010. http://tel.archives-ouvertes.fr/tel-00512832.

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Aujourd'hui le test de fabrication de circuits intégrés au niveau wafer s'appuie sur une technologie par contact entre l'équipement de test et les circuits à tester. Cette méthode souffre de plusieurs limitations telles que l'endommagement des plots de contact lorsque plusieurs tests sont necessaires en cours de fabrication du système. Pour pallier ces limitations, nous avons exploré une alternative de test basée sur communication sans fil. Pour cela une interface de test a été développée, cette interface doit être intégrée au sein de chaque dispositif à tester. Cette solution innovante entièrement développée au cours de ma thèse permet d'une part au testeur de diffuser simultanément les données de test vers tous les dispositifs du wafer, et d'autre part à chaque dispositif de retourner ses réponses vers le testeur. Cette interface a été développée pour permettre le test d'un dispositif en cours de fabrication (tous les éléments composant le système ne sont pas présent), et optimiser le temps de test de l'ensemble d'un wafer. Plusieurs campagnes de test sur des dispositifs réels nous ont permis de valider une solution au problème de l'alimentation des dispositifs sur le wafer. Cette solution s'appuie sur une distribution des alimentations par des rails insérées sur les lignes de découpage du wafer. Enfin, un prototype de notre interface de test sans fil a été réalisé sur une plateforme reconfigurable et nous a permis de valider son fonctionnement en testant un circuit du commerce.

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Zine, Elabidine Khouloud. « Méthode de prototypage virtuel permettant l'évaluation précoce de la consommation énergétique dans les systèmes intégrés sur puce ». Thesis, Paris 6, 2014. http://www.theses.fr/2014PA066669/document.

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Depuis quelques années, les systèmes embarqués n’ont pas cessé d’évoluer. Cette évolution a conduit à des circuits de plus en plus complexes pouvant comporter plusieurs centaines de processeurs sur une même puce.Si la progression des techniques de fabrication des systèmes intégrés, a permis l’amélioration des performances de ces derniers en terme de temps et de capacité de traitement, elle a malheureusement amené une nouvelle contrainte de conception. En effet, cette nouvelle génération de systèmes consomme plus d’énergie et nécessite donc la prise en compte, pendant la phase de conception, des caractéristiques énergétiques dans le but de trouver le meilleur compromis (performance / énergie). Des études montrent qu’une estimation précoce de la consommation – i.e. au niveau comportemental – permet une meilleure diminution de l’énergie consommée par le système.L’outil EDPE (Early Design Power Estimation), objet de cette thèse, propose en réponse à ce besoin, une procédure permettant la caractérisation énergétique précoce d’une architecture de type MPSoC (MultiProcessor System on Chip) dans la phase de prototypage virtuel en System C. EDEP s’appuie sur des modèles de consommation par composant pour en déduire l’énergie dissipée par le système global lorsque le système est simulé au niveau CABA(Cycle Accurate Byte Accurate) ou encore TLM (Transaction Level Model). Les modèles proposés par EDPE, ont été intégrés dans la bibliothèque de prototypage virtuel SoClib. Ainsi, pendant la phase d’exploration architecturale, le concepteur dispose en plus des caractéristiques temporelles et spatiales de son circuit, d’une estimation précise de sa consommation énergétique.L’élaboration de modèles de consommation pour les différents composants matériels d’un système, à l’aide d’EDPE, est simple, homogène et facilement généralisable.Les résultats obtenus montrent la capacité d’EDPE à prédire la consommation énergétique de différentes applications logicielles déployées sur une même architecture matérielle de manière précise et rapide
Technological trends towards high-level integration combined with the increasing operating frequencies, made embedded systems design become more and more complex.The increase in number of computing resources in integrated circuit (IC) led toover-constrained systems.In fact, SoC (System on Chip) designers must reduce overall system costs, including board space, power consumption and development time.Although many researches have developed methodologies to deal with the emerging requirements of IC design, few of these focused on the power consumption constraint.While the highest accuracy is achieved at the lowest level, estimation time increases significantly when we move down to lower levels.Early power estimation is interesting since it allows to widely explore the architectural design space during the system level partitioning and to early adjust architectural design choices.EDPE estimates power consumption at the system levels and especially CABA (Cycle Accurate Bit Accurate) and TLM (Transaction Level Modelling) levels.The EDPE have been integrated into SoCLib library.The main goal of EDPE (Early Design Power Estimation) is to compare the power consumption of different design partitioning alternatives and chooses the best trade-off power/ performance.Experimental results show that EDPE (Early Design Power Estimation) method provides fast, yet accurate, early power estimation for MPSoCs (MultiprocessorSystem on Chip).EDPE uses few parameters per hardware components and is based on homogeneous and easy characterization method.EDPE is easily generalized to any virtual prototyping library

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Hong, Chuan. « Towards the development of a reliable reconfigurable real-time operating system on FPGAs ». Thesis, University of Edinburgh, 2013. http://hdl.handle.net/1842/8948.

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In the last two decades, Field Programmable Gate Arrays (FPGAs) have been rapidly developed from simple “glue-logic” to a powerful platform capable of implementing a System on Chip (SoC). Modern FPGAs achieve not only the high performance compared with General Purpose Processors (GPPs), thanks to hardware parallelism and dedication, but also better programming flexibility, in comparison to Application Specific Integrated Circuits (ASICs). Moreover, the hardware programming flexibility of FPGAs is further harnessed for both performance and manipulability, which makes Dynamic Partial Reconfiguration (DPR) possible. DPR allows a part or parts of a circuit to be reconfigured at run-time, without interrupting the rest of the chip’s operation. As a result, hardware resources can be more efficiently exploited since the chip resources can be reused by swapping in or out hardware tasks to or from the chip in a time-multiplexed fashion. In addition, DPR improves fault tolerance against transient errors and permanent damage, such as Single Event Upsets (SEUs) can be mitigated by reconfiguring the FPGA to avoid error accumulation. Furthermore, power and heat can be reduced by removing finished or idle tasks from the chip. For all these reasons above, DPR has significantly promoted Reconfigurable Computing (RC) and has become a very hot topic. However, since hardware integration is increasing at an exponential rate, and applications are becoming more complex with the growth of user demands, highlevel application design and low-level hardware implementation are increasingly separated and layered. As a consequence, users can obtain little advantage from DPR without the support of system-level middleware. To bridge the gap between the high-level application and the low-level hardware implementation, this thesis presents the important contributions towards a Reliable, Reconfigurable and Real-Time Operating System (R3TOS), which facilitates the user exploitation of DPR from the application level, by managing the complex hardware in the background. In R3TOS, hardware tasks behave just like software tasks, which can be created, scheduled, and mapped to different computing resources on the fly. The novel contributions of this work are: 1) a novel implementation of an efficient task scheduler and allocator; 2) implementation of a novel real-time scheduling algorithm (FAEDF) and two efficacious allocating algorithms (EAC and EVC), which schedule tasks in real-time and circumvent emerging faults while maintaining more compact empty areas. 3) Design and implementation of a faulttolerant microprocessor by harnessing the existing FPGA resources, such as Error Correction Code (ECC) and configuration primitives. 4) A novel symmetric multiprocessing (SMP)-based architectures that supports shared memory programing interface. 5) Two demonstrations of the integrated system, including a) the K-Nearest Neighbour classifier, which is a non-parametric classification algorithm widely used in various fields of data mining; and b) pairwise sequence alignment, namely the Smith Waterman algorithm, used for identifying similarities between two biological sequences. R3TOS gives considerably higher flexibility to support scalable multi-user, multitasking applications, whereby resources can be dynamically managed in respect of user requirements and hardware availability. Benefiting from this, not only the hardware resources can be more efficiently used, but also the system performance can be significantly increased. Results show that the scheduling and allocating efficiencies have been improved up to 2x, and the overall system performance is further improved by ~2.5x. Future work includes the development of Network on Chip (NoC), which is expected to further increase the communication throughput; as well as the standardization and automation of our system design, which will be carried out in line with the enablement of other high-level synthesis tools, to allow application developers to benefit from the system in a more efficient manner.

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Iqbal, Arshad. « VoIP Server HW/SW Codesign for Multicore Computing ». Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-94203.

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Modern technologies are growing and Voice over Internet Protocol (VoIP) technology is able to function in heterogeneous networks. VoIP gained wide popularity because it offers cheap calling rates compared to traditional telephone system and the number of VoIP subscribers has increased significantly in recent years. End users need reliable and acceptable call quality in real time communication with best Quality of Service (QoS). Server complexity is increasing to handle all client requests simultaneously and needs huge processing power. VoIP Servers will increase processing power but the engineering tradeoff needs to be considered e.g. increasing hardware will increase hardware complexity, energy consumption, network management, space requirement and overall system complexity. Modern System-on-Chip (SoC) uses multiple core technology to resolve the complexity of hardware computation. With enterprises needing to reduce overall costs while simultaneously improving call setup time, the amalgamation of VoIP with SoC can play a major role in the business market. The proposed VoIP Server model with multiple processing capabilities embedded in it is tailored for multicore hardware to achieve the required result. The model uses SystemC-2.2.0 and TLM-2.0 as a platform and consists of three main modules. TLM is built on top of SystemC in an overlay architectural fashion. SystemC provides a bridge between software and hardware co-design and increases HW & SW productivity, driven by fast concurrent programming in real time. The proposed multicore VoIP Server model implements a round robin algorithm to distribute transactions between cores and clients via Load Balancer. Primary focus of the multicore model is the processing of call setup time delays on a VoIP Server. Experiments were performed using OpenSIP Server to measure Session Initiation Protocol (SIP) messages and call setup time processing delays. Simulations were performed at the KTH Ferlin system and based on the theoretical measurements from the OpenSIP Server experiments. Results of the proposed multicore VoIP Server model shows improvement in the processing of call setup time delays.

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Terosiet, Medhi. « Conception d'un oscillateur robuste contrôlé numériquement pour l'horlogerie des SoCs ». Phd thesis, Université Pierre et Marie Curie - Paris VI, 2012. http://tel.archives-ouvertes.fr/tel-00836916.

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L'intégration d'un plus grand nombre de fonctions sur des circuits intégrés plus rapides à chaque nouvelle génération. Malheureusement, elles ont rendu la tâche des concepteurs plus difficile, avec notamment la montée de la puissance consommée et des temps de propagation des signaux à travers la puce. La distribution de l'horloge, assurant le synchronisme des opérations du circuit, en est l'élément le plus symptomatique. La génération distribuée de l'horloge apparaît comme une alternative aux solutions classiques. Elle repose sur la mise en place d'un réseau de N oscillateurs géographiquement distribués sur l'ensemble de la puce. Chaque oscillateur génère localement une horloge pour la zone de la puce dans laquelle il se trouve. La phase d'une horloge est accordée sur celle de ces proches voisines. Ainsi, l'horloge n'a plus à parcourir de long chemin. Toutefois, les performances du circuit d'horloge sont liées, non pas à un, mais à N oscillateurs évoluant dans un environnement hostile (variations de l'alimentation, de la température, etc.). Aussi, les travaux de cette thèse portent sur la conception d'un oscillateur contrôlé numériquement. Plus précisément, notre problématique est : " Comment concevoir un DCO (Digitally Controlled Oscillator) robuste soumis à l'environnement hostile d'un SoC en technologie CMOS submicronique ? ". Pour répondre à cette question, nous proposons, dans un premier temps, la modélisation d'une topologie d'oscillateur contrôlé numériquement ; le but étant de déterminer sa pertinence quant à notre application d'horlogerie. Comme cette dernière est émergente, il n'y a à l'heure actuelle aucune théorie la caractérisant. A travers notre analyse, nous mettons en évidence ses faiblesses et la nécessité de lui adjoindre des circuits de protection. De ce fait, les performances du circuit d'horloge ne sont plus seulement dépendantes de l'oscillateur, mais aussi des dispositifs mis en place pour le protéger des agressions des circuits environnants. Ce constat a motivé le développement d'une alternative qui ne serait pas soumise aux mêmes contraintes. Nous proposons finalement un oscillateur contrôlé numériquement robuste à la fois contre les variations de l'alimentation et de la température. Cet oscillateur est conçu à partir de blocs analogiques connus et bien décrits par la littérature. Pour limiter l'influence de la tension d'alimentation et de la température à laquelle évolue l'oscillateur, nous tirons profit des effets de canal court propres aux technologies submicroniques.

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Reehal, Gursharan Kaur. « Designing Low Power and High Performance Network-on-Chip Communication Architectures for Nanometer SoCs ». The Ohio State University, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=osu1340022240.

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Samii, Soheil. « Power Modeling and Scheduling of Tests for Core-based System Chips ». Thesis, Linköping University, Department of Computer and Information Science, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2863.

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The technology today makes it possible to integrate a complete system on a single chip, called "System-on-Chip'' (SOC). Nowadays SOC designers use previously designed hardware modules, called cores, together with their user defined logic (UDL), to form a complete system on a single chip. The manufacturing process may result in defect chips, for instance due to the base material, and therefore testing chips after production is important in order to ensure fault-free chips.

The testing time for a chip will affect its final cost. Thus it is important to minimize the testing time for each chip. For core-based SOCs this can be done by testing several cores at the same time, instead of testing the cores sequentially. However, this will result in a higher activity in the chip, hence higher power consumption. Due to several factors in the manufacturing process there are limitations of the power consumption for a chip. Therefore, the power limitations should be carefully considered when planning the testing of a chip. Otherwise it can be damaged during test, due to overheating. This leads to the problem of minimizing testing time under such power constraints.

In this thesis we discuss test power modeling and its application to SOC testing. We present previous work in this area and conclude that current power modeling techniques in SOC testing are rather pessimistic. We therefore propose a more accurate power model that is based on the analysis of the test data. Furthermore, we present techniques for test pattern reordering, with the objective of partitioning the test power consumption into low parts and high parts.

The power model is included in a tool for SOC test architecture design and test scheduling, where the scheduling heuristic is designed for SOCs with fixed- width test bus architectures. Several experiments have been conducted in order to evaluate the proposed approaches. The results show that, by using the presented power modeling techniques in test scheduling algorithms, we will get lower testing times and thus lower test cost.

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Flórez, Martha Johanna Sepúlveda. « Projeto de estruturas de comunicação intrachip baseadas em NoC que implementam serviços de QoS e segurança ». Universidade de São Paulo, 2011. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-04112011-140055/.

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Os atuais sistemas eletrônicos desenvolvidos na forma de SoCs (Sistemas-sobre-Silício) são caracterizados pelo incremento de informação crítica que é capturada, armazenada e processada. Com a introdução dos SoCs nos sistemas distribuídos que promovem o compartilhamento dos recursos, a segurança vem se transformando num requisito de projeto extremamente importante. Os atuais SoCs são alvo de ataques. O desafio consiste em projetar um SoC seguro que satisfaça os requisitos de segurança e desempenho, próprios para cada aplicação. A estrutura de comunicação está se tornando o coração do SoC. Esta possui um impacto significativo no desempenho do sistema. A inclusão de serviços de segurança na estrutura de comunicação é vantajosa devido à sua capacidade de: 1) monitorar a informação transmitida; 2) detectar violações; 3) bloquear ataques; e 4) fornecer informações para diagnóstico e ativação de mecanismos de recuperação e defesa. O presente trabalho propõe a implementação do conceito de QoSS (Qualidade do Serviço de Segurança) no projeto da estrutura de comunicação baseada em redes intrachip (NoCs, Network-on-Chip). QoSS permite a inclusão da segurança como uma dimensão de QoS (Quality-of-Sevice), admitindo a existência de diferentes níveis de proteção. A adoção do QoSS no projeto das NoCs permite a exploração do espaço de projeto das NoCs levando em consideração o compromisso entre a segurança do sistema e o desempenho do sistema. A inclusão do QoSS na NoC é realizada através de uma metodologia que inclui 5 etapas: definição, descrição, implementação, avaliação e otimização. Como resultado é obtido um conjunto de NoCsQoSS que satisfazem os requisitos de segurança e desempenho do sistema. Criamos neste trabalho o ambiente de simulação APOLLO que fornece suporte na rápida exploração do espaço de soluções a partir de modelos SystemC-TLM do SoC. Neste trabalho, apresentamos três estudos de caso que utilizam a nossa metodologia de projeto de NoCs com QoSS na implementação de políticas de segurança estática e dinâmica. Os serviços de segurança de controle de acesso e autenticação foram implementados de duas formas: na interface da rede e no roteador. Realizamos a avaliação da eficácia e eficiência das NoCs resultantes sob diferentes condições de ataques e de tráfego, resultado da variação topológica do tráfego, natureza e tipo de tráfego. Mostramos que a implementação da segurança no roteador é mais eficiente que a implementação na interface da rede em termos de latência e potência sob todas as diferentes condições de tráfego. Porém, a utilização na interface permite a inclusão das características da segurança na NoC de uma maneira mais simples. Desta forma para sistemas complexos a implementação na interface é vantajosa.
As embedded electronic systems are pervading our lives, security is emerging as an extremely important design requirement. Due to the increasing complexity, intrinsic embedded constraints and strict requirements, security and performance are considered challenging tasks. Most of the current electronic systems embedded in a SoC (System-on-Chip) are used to capture, store, manipulate and access sensitive data and perform several critical functions without security guarantee. The challenge is to provide SoC security that allows a trustworthy system that meets the security and performance requirements. As security requirements vary dramatically for different applications, differentiated security services are necessary. The SoC communication structure is becoming the heart of the SoC. It has a significant impact on the overall system performance. The security services integration at the communication structure take advantage of its wide system visibility and critical role in enabling the system operation. It is able to: 1) monitor data transfer; 2) detect attacks; 3) block attacks; and 4) supply information for trigger suitable recovery mechanisms. This work proposes the implementation of the QoSS (Quality-of-Security-Service) concept at the NoC-based communication structure design. QoSS is a novel concept for data protection that introduces security as a dimension of QoS. In contrast with previous works, the different security levels deployment allow a best trade-of the system security and performance requirements. The QoSS integration is carried out trough a 5 step methodology: definition, description, implementation, evaluation and optimization. As a result a set of NoCs-QoSS that satisfies the security and performance requirements are obtained. We use the framework APOLLO that integrates a set of tools, allowing the fast exploration of the huge NoC design space. In this work we present 2 study cases that uses our methodology in order to design a NoC-QoSS that supports static and a dynamic security policies and also satisfies the security and performance requirements. Two security services: Access Control and authentication are implemented at the NoC interface and at the NoC router. The final configurations are evaluated under different traffic and attack conditions. We show that the security implementation at the router is latency and power consumption efficient that the implementation at the network interface under all the traffic conditions. However, the security implementation at the network interface allows the integration of the security characteristics in a simpler way.

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Solanki, Jigar. « Approche générative conjointe logicielle-matérielle au développement du support protocolaire d’applications réseaux ». Thesis, Bordeaux, 2014. http://www.theses.fr/2014BORD0301/document.

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Les communications entre les applications réseaux sont régies par un ensemble de règles regroupées sous forme de protocoles. Les messages protocolaires sont gérés par une couche de l’application réseau connue comme étant la couche de support protocolaire. Cette couche peut être de nature logicielle, matérielle ou conjointe. Cette couche se trouve à la frontière entre le coeur de l’application et le monde extérieur. A ce titre, elle représente un composant névralgique de l’application. Les performances globales de l’application sont ainsi directement liées aux performances de la couche de support protocolaire associée.Le processus de développement de ces couches consiste à traduire une spécification du protocole, écrite dans un langage de haut niveau tel que ABNF dans un langage bas niveau, logiciel ou matériel. Avec l’avènement des systèmes embarqués, de plus en plus de systèmes sur puce proposent l’utilisation de ressources matérielles afin d’accroître les performances des applicatifs. Néanmoins, peu de processus de développement de couches de support protocolaire tirent parti de ces ressources, en raison notamment de l’expertise nécessaire dans ce domaine.Cette thèse propose une approche générative conjointe logicielle-matérielle au développement du support protocolaire d’applications réseaux, pour améliorer leur performance tout en restant ergonomique pour le développeur de l’application. Notre approche est basée sur l’exploitation d’un langage dédié, appellé Zebra pour générer les différents composants logiciels et matériels formant la couche de support. L’expertise nécessaire est déportée dans l’utilisation du langage Zebra et les composants matériels générés permettent d’accroître les performances de l’application.Les contributions de cette thèse sont les suivantes : Nous avons effectué une analyse des protocoles et applications réseaux. Cette analyse nous a permis d’identifier les composants pour lesquels il est possible d’obtenir des gains de performances.Nous avons conçu et exploité un langage dédié, Zebra, permettant de décrire les différentes entités de la couche de support protocolaire et générant les éléments logiciels et matériels la composant. Nous avons construit un système sur puce exécutant un système d’exploitation Linux afin d’étayer notre approche. Nous avons conçu des accélérateurs matériels déployables pour différents protocoles réseaux sur ce système et pilotables par les applicatifs. Afin de rendre l’accès aux accélérateurs matériels transparent pour les applications réseaux, nous avons développé un intergiciel gérant l’ensemble de ces accès. Cet intergiciel permet à plusieurs applications et/ou à plusieurs clients d’une même application d’utiliser les accélérateurs pour le traitement des messages protocolaires. Nous avons évalué les performances de notre approche dans des conditions réelles. Nous avons comparé ces performances à celles de couches de supports faisant référence dans le domaine. Nous avons constaté un gain de performance conséquent pour l’approche que nous proposons
Communications between network applications is achieved by using rulesets known as protocols. Protocol messages are managed by the application layer known as the protocol parsing layer or protocol handling layer. Protocol parsers are coded in software, in hardware or based on a co-design approach. They represent the interface between the application logic and the outside world. Thus, they are critical components of network applications. Global performances of network applications are directly linked to the performances of their protocol parser layers.Developping protocol parsers consists of translating protocol specifications, written in a high level language such as ABNF towards low level software or hardware code. As the use of embedded systems is growing, hardware ressources become more and more available to applications on systems on chip (SoC). Nonetheless, developping a network application that uses hardware ressources is challenging, requiring not only expertise in hardware design, but also a knowledge of the protocols involved and an understanding of low-level network programming.This thesis proposes a generative hardware-software co-design based approach to the developpement of network protocol message parsers, to improve their performances without increasing the expertise the developper may need. Our approach is based on a dedicated language, called Zebra, that generates both hardware and software elements that compose protocol parsers. The necessary expertise is deported in the use of the Zebra language and the generated hardware components permit to improve global performances.The contributions of this thesis are as follows : We provide an analysis of network protocols and applications. This analysis allows us to detect the elements which performances can be improved using hardware ressources. We present the domain specific language Zebra to describe protocol handling layers. Software and hardware components are then generated according to Zebra specifications. We have built a SoC running a Linux operating system to assess our approach.We have designed hardware accelerators for different network protocols that are deployed and driven by applications. To increase sharing of parsing units between several tasks, we have developped a middleware that seamlessly manages all the accesses to the hardware components. The Zebra middleware allows several clients to access the ressources of a hardware accelerator. We have conducted several set of experiments in real conditions. We have compared the performances of our approach with the performances of well-knownprotocol handling layers. We observe that protocol handling layers baded on our approach are more efficient that existing approaches

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Braunstein, Cécile. « Conception incrémentale, vérification de composants matériels et méthode d'abstraction pour la vérification de systèmes intégrés sur puce ». Paris 6, 2007. http://www.theses.fr/2007PA066577.

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Cette thèse traite de la vérification formelle par model checking de systèmes intégrés sur puce. Nous proposons d'abord une méthode de conception incrémentale pour la vérification d'un composant matériel. Cette méthode est un cadre de conception par ajouts successifs de nouveaux comportements. Nous avons montré que cette méthode assure la non-régression d'un composant tout au long de sa conception. D'autre part, cette méthode permet aussi de faire évoluer la spécification d'un composant en prenant en compte les différentes fonctionnalités ajoutées au cours de la conception. Nous avons ensuite particularisé cette approche pour la conception et la vérification d'architectures pipelines. Cette méthode a été utilisée avec succès pour laconception de convertisseurs de protocole. La vérification par model-checking d'un système intégré sur puce se confronte au problème d'explosion combinatoire. Les techniques d'abstractions sont des méthodes efficaces pour alléger ce problème. Nous exposons un algorithme d'abstraction basé sur la spécification de chaque composant. Cet algorithme construit une structure de Kripke représentant un sous-ensemble des formules CTL tirées de la spécification. Cette construction se place dans un contexte de raffinement d'abstraction guidé par l'étude du contre-exemple produit par le model checker. Les premières expérimentations que nous avons réalisées montrent un gain considérable en temps de vérification et un accroissement conséquent de la taille du système vérifié. Ces résultats nous confortent sur l'intérêt de cette méthode d'abstraction.

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Gupta, Vishal. « An accurate, trimless, high PSRR, low-voltage, CMOS bandgap reference IC ». Diss., Available online, Georgia Institute of Technology, 2007, 2007. http://etd.gatech.edu/theses/available/etd-07052007-073154/.

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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2008.
Ayazi, Farrokh, Committee Member ; Rincon-Mora, Gabriel, Committee Chair ; Bhatti, Pamela, Committee Member ; Leach, W. Marshall, Committee Member ; Morley, Thomas, Committee Member.

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Thèses sur le sujet « SOC [System-on-Chip Soc] »

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