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Thirtle, Michael R. "Seeing the lighthouse-- as simple as the ASBC? facilitating organizational change in the U.S. Air Force /". Santa Monica, CA : Rand, 1999. http://catalog.hathitrust.org/api/volumes/oclc/42905356.html.
Testo completo
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Fernandez, Tafur Ana Cecilia, Arroyo Jesús Humberto Diaz, Rueda Carlos Alfonso Farfan, Peña Berenice Eileen Saldaña e Pérez Milagros del Rosario Suyo. "ASAC". Bachelor's thesis, Universidad Peruana de Ciencias Aplicadas (UPC), 2018. http://hdl.handle.net/10757/626492.
Testo completoAbstract (sommario):
Ser dueño de un negocio puede ser por momentos agobiante. ASAC es una excelente opción que no sólo acompaña, sino que permite encontrar la solución a los problemas diarios desarrollando en nuestros clientes capacidades internas de gestión y ventajas competitivas fundamentadas en el conocimiento y el uso de la tecnología optimizando el tiempo dedicado a sus actividades.
ASAC asesora a personas que trabajan desde casa permitiéndoles desarrollar estrategias que les permitirán reducir costos alcanzando la rentabilidad esperada, mejorando procesos y resultados, preparando a los emprendedores para ser dueños de su tiempo y no un empleado de su propia empresa; los ayudará a reencontrarse con los sueños que los llevaron a emprender y abrir su propio negocio.Owning a business can be overwhelming at times. ASAC is an excellent option that not only accompanies, but also allows us to find the solution to daily problems by developing in our clients internal management skills and competitive advantages based on knowledge and the use of technology, optimizing the time dedicated to their activities. ASAC advises people who work from home, allowing them to develop strategies that will allow them to reduce costs, achieving the expected profitability, improving processes and results, preparing entrepreneurs to be owners of their time and not an employee of their own company; will help them to rediscover the dreams that led them to start and open their own business.
Trabajo de investigación
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Lothian, Angus, Ivar Härnqvist, Adam Jakobsson, Arvid Westerlund, Felix Goding, Jacob Wahlman, Kevin Scott e Rasmus Karlsson. "B-ASIC - Better ASIC Toolbox : En verktygslåda som förenklar design och optimering av ASIC". Thesis, Linköpings universitet, Institutionen för datavetenskap, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-167069.
Testo completoAbstract (sommario):
Denna rapport behandlar ett arbete skriven av åtta studenter som läste kursen TDDD96 Kandidatprojekt i programvaruutveckling vid Linköpings universitet under vårterminen 2020. Projektets syfte var att utveckla en verktygslåda i Python och C++ för att konstruera signalbehandlade kretsar. Denna verktygslåda är tänkt att användas inom laborationer i kursen TSTE87 Applikationsspecfika integrerande kretsar vid Linköpings universitet och inom forskning för utveckling av ASIC:s. Projektet resulterade i produkten B-ASIC. B-ASIC är ett bibliotek för programmeringsspråket Python som är skrivet i Python med en underliggande modul i C++. B-ASIC används för design och optimering av ASIC:s. Produkten B-ASIC erbjuder ett grafiskt användargränssnitt där användaren kan interagera med biblioteket utan programmeringskunskaper inom Python. I rapporten beskrivs hur projektarbetet har anpassats för att vara till värde för kunden och hur utvecklingsprocessen har påverkat resultatet av produkten. Projektmedlemmarna har dessutom genomfört egna undersökningar och dessa finns att läsa i slutet av rapporten.
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Arumugam, Prakash. "Investigations into ASIC desensitization". Connect to resource, 2006. http://hdl.handle.net/1811/6036.
Testo completoAbstract (sommario):
Thesis (Honors)--Ohio State University, 2006.Title from first page of PDF file. Document formattted into pages: contains 16 p.; also includes graphics. Includes bibliographical references (p. 16). Available online via Ohio State University's Knowledge Bank.
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Back, Robin. "Optimeringsmetoder för ASMC-strukturer". Thesis, KTH, Lättkonstruktioner, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-180274.
Testo completoAbstract (sommario):
Thin metal sheets have for long been the dominant structural components in automotive bodies, but as environmental concerns mount new materials are needed to reduce mass. Advanced Sheet Moulding Compounds (ASMC) is a carbon fibre composite with short fibres and has been put forward as an alternative. It is both light and has good durability and can be formed in a mould similarly to steel sheets. A distinct advantage is that unlike for steel sheets the thickness in an ASMC component can be varied and stiffeners integrated. This creates great opportunities for optimisation, but as know-how in the industry is scarce a methodology is necessary. This master’s thesis describes a method developed for optimising structural components manufactured in ASMC by analysing a backplate mounted in a Body-In-White (BIW). The optimisation design process was first developed in a simplified model made to mimic a BIW without all the complexities therein. In this thesis free-size optimisation was done individually and coupled with adding uni-directional (UD) fibres and ribs to the backplate. This process was then verified in an accurate car body model and the process translated rather well to a more realistic model as favourable results were obtained. Optimisation resulted in more than 50% decrease in the component’s mass and body torsional stiffness could be increased by up to 7%. A step-by-step guide for this process is presented. Moving forward the design methodology needs to be verified and developed further for different structures and load cases. It is believed that the process detailed works well for many different structures as is, but improvements can be made and are ultimately necessary.Under lång tid har pressad metallplåt varit det dominerande strukturella materialet i bilkarosser, men i takt med att miljövänliga lösningar blir mer och mer viktiga så behövs nya material för att reducera vikt. Advanced Sheet Moulding Compounds (ASMC) är en kolfiber komposit med korta fibrer och har lagts fram som ett alternativ. Materialet är både lätt och har goda hållfasthetsegenskaper och kan formas i en gjutform i en process som liknar pressning av plåt. En stor fördel är att till skillnad från metallplåt så kan tjockleken i en ASMC komponent varieras och förstyvningar kan integreras. Detta skapar stora möjligheter för optimering, men då erfarenhet av dessa material i industrin är liten behövs metoder för detta. I detta examensarbete beskrivs en metod som utvecklats för optimering av ASMC komponenter via analys av en vridplåt monterad i en bil. För att undvika onödig komplexitet utvecklades optimeringsprocessen först i en förenklad modell som skulle härma en Body-In-White (BIW). Free-size optimering användes individuellt och tillsammans med att lägga in enkelriktade fibrer och förstyvningar. Processen verifierades sedan i en noggrann karossmodell, och den fungerade väl då gynnsamma resultat erhölls. Det visades att optimering av ryggplåten kan kraftigt reducera dess vikt och öka vridstyvheten i ett fordon. Optimering resulterade i mer än 50% minskning av komponents vikt och bilkroppens vridstyvhet kunde höjas med upp till 7%. En guide för processen som förklarar steg för steg hur optimering av ASMC ska utföras har presenterats. I framtiden bör metoden verifieras och utvecklas ytterligare för andra strukturer och last fall. Det förmodas att den beskrivna processen fungerar som den är, men förbättringar kan göras och behövs.
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Ghuman, Parminder, Salman Sheikh, Steve Koubek, Scott Hoy e Andrew Gray. "High Rate Digital Demodulator ASIC". International Foundation for Telemetering, 1998. http://hdl.handle.net/10150/609676.
Testo completoAbstract (sommario):
International Telemetering Conference Proceedings / October 26-29, 1998 / Town & Country Resort Hotel and Convention Center, San Diego, CaliforniaThe architecture of the High Rate (600 Mega-bits per second) Digital Demodulator (HRDD) ASIC capable of demodulating BPSK and QPSK modulated data is presented in this paper. The advantages of all-digital processing include increased flexibility and reliability with reduced reproduction costs. Conventional serial digital processing would require high processing rates necessitating a hardware implementation other than CMOS technology such as Gallium Arsenide (GaAs) which has high cost and power requirements. It is more desirable to use CMOS technology with its lower power requirements and higher gate density. However, digital demodulation of high data rates in CMOS requires parallel algorithms to process the sampled data at a rate lower than the data rate. The parallel processing algorithms described here were developed jointly by NASA’s Goddard Space Flight Center (GSFC) and the Jet Propulsion Laboratory (JPL). The resulting all-digital receiver has the capability to demodulate BPSK, QPSK, OQPSK, and DQPSK at data rates in excess of 300 Mega-bits per second (Mbps) per channel. This paper will provide an overview of the parallel architecture and features of the HRDR ASIC. In addition, this paper will provide an overview of the implementation of the hardware architectures used to create flexibility over conventional high rate analog or hybrid receivers. This flexibility includes a wide range of data rates, modulation schemes, and operating environments. In conclusion it will be shown how this high rate digital demodulator can be used with an off-the-shelf A/D and a flexible analog front end, both of which are numerically computer controlled, to produce a very flexible, low cost high rate digital receiver.
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Ramsten, Johannes, e Markus Klum. "Implementation av fältbuss ASIC i FPGA". Thesis, Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-4523.
Testo completoAbstract (sommario):
HMS Industrial Networks AB is in need of changing a communications solution that iscurrently based on an ASIC. This will be achieved by moving the communications solution toa FPGA with the help of the programming language VHDL. By doing this, it is possible toreduce the need for specific circuits, get a more flexible platform and thus get a cheapersolution.
This report describes a solution for how to move a network protocol from an ASIC to anFPGA. The report shows that the network slave device is working under the guidelines forthis project. This means that it is quite realistic to implement a fieldbus protocol on an FPGA,using VHDL and to maintain the same functionality as the earlier communications solution.
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Harrison, Andrew. "ASIC based recorders of electrophysiological signals". Thesis, University of Nottingham, 1995. http://eprints.nottingham.ac.uk/13305/.
Testo completoAbstract (sommario):
The ability of application specific integrated circuits (ASICs) to minimise the size and power consumption of electronic circuitry, makes their application to the design of ambulatory monitoring equipment, an attractive option. To this end, a multi-purpose mixed analogue and digital ASIC has been fabricated and incorporated into both a long-term recorder of adult heart rate (HR) and a recorder of electrophysiological signals. The adult HR recorder has been employed in a study of long-term daily HR patterns, which verified the ambulatory nature of this instrument, as well as its suitability for investigating HR variability. The electrophysiological signal recorder uses the ASIC to amplify, filter and digitise signals, which are then stored directly into static RAM. The analogue front-end of this instrument is flexible in terms of gain, bandwidth and sampling frequency allowing it be applied to a whole range of signals. This instrument has been used to record the antepartum fetal HR, as part of the development of an ambulatory, ASIC based recorder of fetal HR (FHR). These recordings have shown that a usable signal can be obtained from a mother in her home environment, whilst in various postures. The electrophysiological signal recorder has also been used to record the electrohysterogram (EHG), which is the name given to the electrical activity of the uterus, from abdominal electrodes during labour. A strong correlation was found to exist between tocographs derived from the EHG and tocographs produced by conventional means.
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Dobson, Jonathan M. "ASIC implementations of the Viterbi Algorithm". Thesis, University of Edinburgh, 1999. http://hdl.handle.net/1842/13669.
Testo completoAbstract (sommario):
The Viterbi Algorithm is a popular method for decoding convolutional codes, receiving signals in the presence of intersymbol-interference, and channel equalization. In 1981 the European Telecommunications Administration (CEPT) created the Groupe Special Mobile (GSM) Committee to devise a unified pan-European digital mobile telephone standard. The proposed GSM receiver structure brings together Viterbi decoding and equilization. This thesis presents three VLSI designs of the Viterbi Algorithm with specific attention paid to the use of such modules within a GSM receiver. The first design uses a technique known as redundant number systems to produce a high speed decoder. The second design uses complementary pass-transistor logic to produce a low-power channel equalizer. The third design is a low area serial equalizer. In describing the three designs, redundant number systems and complementary pass-transistor logic are examined. It is shown that while redundant number systems can offer significant speed advantages over twos complement binary, there are other representations that can perform equally well, if not better. It will also be shown that complementary pass-transistor logic can offer a small improvement for VLSI circuits in terms of power consumption.
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Perumalla, Anvesh Kumar. "A Genetic Algorithm for ASIC Floorplanning". Wright State University / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=wright1484236480221006.
Testo completo
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Hoffman, Joseph A. "VHDL modeling of ASIC power dissipation". Master's thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-10222009-124831/.
Testo completo
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Droste, Dirk. "Realisierung eines Wellenfrontsensors mit einem ASIC". [S.l. : s.n.], 1999. http://www.bsz-bw.de/cgi-bin/xvms.cgi?SWB8337986.
Testo completo
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Hussain, Waqar Muhammad. "Low Power Implantable ASIC forBio-Impedance Measurements". Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-105098.
Testo completoAbstract (sommario):
Electrical bio-impedance can give a lot of insight into the basic physiological parameters of human body and concentration of glucose is one of those vital parameters.In order to control diabetes mellitus, it is critically essential to maintain blood glucose concentrations within the normal physiological range to avoid diabetes related complications.Consequently, accurate in-vivo and in-vitro measurement of glucose concentration in physiological uids has long been a central goal of bio sensor research.The correlation between glucose levels in human body and bio-impedance is more potently described with invasive measurement solutions and implanting the entire system inside human body can be considered one such technique.Any implantable device needs to be miniature in size as well as consume as little power as possible and since these two factors trade-o directly or indirectly with the accuracy, the solution space of dierent presently existing measurement techniques were implored to find an alternative that can meet all the specied constraints .The resultant application specific integrated circuit (ASIC) is capable of doing electrical bio-impedance measurements in implantable equipment and can handle impedance levels residing in a large dynamic range with very low power consumption, having small size and high accuracy. The circuit is based on 150nm technology, consumes around 530W power and has a worst case accuracy of 94%.
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Khawaja, Jaleed Ejaz. "Asic gas sensors based on ratiometric principles". Thesis, University of Warwick, 2009. http://wrap.warwick.ac.uk/2230/.
Testo completoAbstract (sommario):
The wide-scale usage of VOCs in industrial processes requires monitoring the concentrations of these vapours to keep a safe operating environment. Most combustible hydrocarbons can be ignited as a gas-air mixture in the range of 0.5% to 15% by volume. This has led to the development of several portable air quality monitoring instruments. However, the high costs and lack of durability of these instruments has remained an issue to be addressed. This PhD thesis reports on the development and characterization of a novel low cost smart gas sensor technology adaptable for use in a portable instrument. The smart gas sensor devices have been developed to target four different VOCs in air. The smart gas sensor device combines a smart ASIC (SRL 194 designed at SRL, Warwick University) fabricated in standard 0.7 μm CMOS technology and two alkyl-dithiol based self-assembled gold nanoparticle chemoresistive sensors (fabricated at Sony Deutschland GmbH) in a ratiometric array to offer a robust system which can address the common mode variations found in polymer based gas sensor systems. The ratiometric ASIC sensor array architecture allows for the reduction of the baseline value’s dependence on environmental variations and the elimination of baseline drift due to long term application of DC voltage. Three ratiometric array arrangements - mono-type uni-variate with only one chemosensor per device, mono-type bi-variate with two chemosensors of the same film material per device and duo-type with a polar and a non-polar chemosensor per device and their variations were characterized in an automated FIA test station against exposure to methanol, ethanol, propan-1-ol, and toluene at 30°C and 0-5% rh. It was determined that the devices’ response output to VOC analytes was entirely dependent on the variation of the resistance ratio of the chemoresistive sensors in the ratiometric sensor array. The effects of variations of the temperature and rh on the smart sensor output were calibrated. The mono-type devices gave a high magnitude response to the vapours whereas the duo-type arrangement offered a high degree of discrimination between the test analytes with little post-processing steps. Three different alkyl-dithiol chemoresistive sensor films on gold electrodes were successfully used as the VOC vapour sensitive elements in each arrangement. The effects of using a silicone sealant gel as a partitioning layer were characterized and it was observed that at vapour concentrations less than 3000 ppm the silicone encapsulated chemosensor devices reported a larger response to the VOC analytes as compared to those without the silicone. The test devices reported promising response repeatability and reproducibility with excellent return to baseline properties, a negligible hysteresis and an error margin of under 10%. Ideal operating temperature was determined to be 40°C at which rh variations were found to be minimal. The test devices were found to be robust with little variation in the quality of the device output over the course of 18 months. The novel research demonstrated that it is possible to get high level of diversification between analytes from a low cost and robust gas sensor system for monitoring VOCs. The work carried out here has opened the opportunity to develop highly integrated programmable hand-held gas sensor and e-nose systems for environmental monitoring use in health and safety applications.
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GuzmaÌn, JesuÌs GarciÌa. "Smart ratiometric ASIC chip for VOC monitoring". Thesis, University of Warwick, 2005. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.422141.
Testo completo
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Le, Thai Q. (Thai Quoc) Carleton University Dissertation Engineering Electrical. "Application specific integrated circuit (ASIC) hardwired microcontroller". Ottawa, 1991.
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Bryksin, Vladyslav Sergeevich. "ASIC life extension through hardware patch interfaces". Diss., [La Jolla] : University of California, San Diego, 2009. http://wwwlib.umi.com/cr/ucsd/fullcit?p1464873.
Testo completoAbstract (sommario):
Thesis (M.S.)--University of California, San Diego, 2009.Title from first page of PDF file (viewed July 2, 2009). Available via ProQuest Digital Dissertations. Includes bibliographical references (p. 46-47).
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Paschou, Michail. "ASIC implementation of LSTM neural network algorithm". Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-254290.
Testo completoAbstract (sommario):
LSTM neural networks have been used for speech recognition, image recognition and other artificial intelligence applications for many years. Most applications perform the LSTM algorithm and the required calculations on cloud computers. Off-line solutions include the use of FPGAs and GPUs but the most promising solutions include ASIC accelerators designed for this purpose only. This report presents an ASIC design capable of performing the multiple iterations of the LSTM algorithm on a unidirectional and without peepholes neural network architecture. The proposed design provides arithmetic level parallelism options as blocks are instantiated based on parameters. The internal structure of the design implements pipelined, parallel or serial solutions depending on which is optimal in every case. The implications concerning these decisions are discussed in detail in the report. The design process is described in detail and the evaluation of the design is also presented to measure accuracy and error of the design output.This thesis work resulted in a complete synthesizable ASIC design implementing an LSTM layer, a Fully Connected layer and a Softmax layer which can perform classification of data based on trained weight matrices and bias vectors. The design primarily uses 16-bit fixed point format with 5 integer and 11 fractional bits but increased precision representations are used in some blocks to reduce error output. Additionally, a verification environment has also been designed and is capable of performing simulations, evaluating the design output by comparing it with results produced from performing the same operations with 64-bit floating point precision on a SystemVerilog testbench and measuring the encountered error. The results concerning the accuracy and the design output error margin are presented in this thesis report. The design went through Logic and Physical synthesis and successfully resulted in a functional netlist for every tested configuration. Timing, area and power measurements on the generated netlists of various configurations of the design show consistency and are reported in this report.LSTM neurala nätverk har använts för taligenkänning, bildigenkänning och andra artificiella intelligensapplikationer i många år. De flesta applikationer utför LSTM-algoritmen och de nödvändiga beräkningarna i digitala moln. Offline lösningar inkluderar användningen av FPGA och GPU men de mest lovande lösningarna inkluderar ASIC-acceleratorer utformade för endast dettaändamål. Denna rapport presenterar en ASIC-design som kan utföra multipla iterationer av LSTM-algoritmen på en enkelriktad neural nätverksarkitetur utan peepholes. Den föreslagna designed ger aritmetrisk nivå-parallellismalternativ som block som är instansierat baserat på parametrar. Designens inre konstruktion implementerar pipelinerade, parallella, eller seriella lösningar beroende på vilket anternativ som är optimalt till alla fall. Konsekvenserna för dessa beslut diskuteras i detalj i rapporten. Designprocessen beskrivs i detalj och utvärderingen av designen presenteras också för att mäta noggrannheten och felmarginal i designutgången. Resultatet av arbetet från denna rapport är en fullständig syntetiserbar ASIC design som har implementerat ett LSTM-lager, ett fullständigt anslutet lager och ett Softmax-lager som kan utföra klassificering av data baserat på tränade viktmatriser och biasvektorer. Designen använder huvudsakligen 16bitars fast flytpunktsformat med 5 heltal och 11 fraktions bitar men ökade precisionsrepresentationer används i vissa block för att minska felmarginal. Till detta har även en verifieringsmiljö utformats som kan utföra simuleringar, utvärdera designresultatet genom att jämföra det med resultatet som produceras från att utföra samma operationer med 64-bitars flytpunktsprecision på en SystemVerilog testbänk och mäta uppstådda felmarginal. Resultaten avseende noggrannheten och designutgångens felmarginal presenteras i denna rapport.Designen gick genom Logisk och Fysisk syntes och framgångsrikt resulterade i en funktionell nätlista för varje testad konfiguration. Timing, area och effektmätningar på den genererade nätlistorna av olika konfigurationer av designen visar konsistens och rapporteras i denna rapport.
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Mehrez, Fatima. "Design and test of a readout ASIC for a SiPM - based camera : ALPS (ASIC de lecture pour un photodétecteur SiPM)". Thesis, Université Grenoble Alpes (ComUE), 2015. http://www.theses.fr/2015GREAT131/document.
Testo completoAbstract (sommario):
Cette thèse est la R&D de l’électronique de front-end destinée à la camera de deuxième génération du télescope de grande taille LST de projet CTA, étant basée sur les détecteurs de type SiPM. Cette étude rassemble des équipes du LAPP, de l’université de Padoue, de l’INFN et du MPI de Munich. La première partie de cette thèse porte sur les tests de caractérisations d’une matrice de 16 SiPMs fabriquée par Hamamatsu. Les résultats de ces tests ont souligné les avantages qui pourraient être apportés par l’utilisation de tels détecteurs. Un cahier des charges pour l’électronique a été défini à l’issue de ces tests. Notamment, une nécessité de corriger la dispersion en gain entre les 16 pixels qui a été trouvée d’environ 10%. La seconde partie est la conception d’un circuit intégré (ASIC) qui pourrait lire les signaux des pixels -SiPM avec la moindre perturbation possible de fonctionnement du détecteur. Cet ASIC inclut des fonctions de contrôle (slow control) qui permettent l’ajustement de gain des pixels, l’amélioration de l’uniformité de gain et la possibilité de supprimer les canaux bruyants ou encore même le contournement du processus de contrôle de gain. Ces fonctionnalités peuvent unifier le gain de 16 canaux. Les sorties des 16 canaux seront sommées pour en faire deux signaux seulement à la sortie de l’ASIC. Ces deux signaux, un sur le haut gain et l’autre sur le bas gain seront fournis au système d’acquisition qui suivra l’ASIC. Une fonction de déclenchement génèrera un signal de trigger qui sera ainsi transmis au système d’acquisition. Cet ASIC a été réalisée avec la technologie AMS 0.35um BiCMOS. Les simulations ont montré une gamme dynamique linéairement couverte jusqu’à 2000 photoélectrons et la possibilité de mesurer le photoélectron unique grâce au bon rapport signal sur bruit électronique. Les tests au laboratoire confirment une grande partie de ces résultatsThis thesis is the R&D on front-end electronics for a second generation camera based on the SiPM detectors for the Large Size Telescope (LST) of the CTA project. It is a part of the SiPM collaboration involving the LAPP, the University of Padua, the INFN and the MPI in Munich. The first part of the thesis is the characterization of an array of 16 SiPMs from Hamamatsu. The study proves the advantages of using such detectors in the LST. It defines the specifications of the readout electronics that are the aim of this work. Especially that it should ameliorate the gain dispersion of the 16 pixels that was found of about 10%. The second part is the design of the readout ASIC. The scheme tends to measure the SiPMs’ signals with minimum disturbance of the detector. It integrates slow control facilities that adjust the detector’s gain, minimize the dispersion in gain and provide the possibility of deleting noisy channels or even completely jumping over the control process. These facilities could perfectly get rid of the gain dispersion. Outputs of the 16 pixels will be summed on both high gain and low gain so that only two signals are delivered to the acquisition system that follows. A trigger function will also generate a trigger signal to the acquisition system. The choice was made to realize this ASIC according to the rules of the AMS 0.35um BiCMOS technology. Simulation shows a linearly-covered dynamic range up to 2000 photoelectrons with good signal to noise ratio that allows the measurement of the single photoelectron. Laboratory tests confirm a great part of these results
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Ehliar, Andreas. "Performance driven FPGA design with an ASIC perspective". Doctoral thesis, Linköpings universitet, Datorteknik, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-16372.
Testo completoAbstract (sommario):
FPGA devices are an important component in many modern devices. This means that it is important that VLSI designers have a thorough knowledge of how to optimize designs for FPGAs. While the design flows for ASICs and FPGAs are similar, there are many differences as well due to the limitations inherent in FPGA devices. To be able to use an FPGA efficiently it is important to be aware of both the strengths and oweaknesses of FPGAs. If an FPGA design should be ported to an ASIC at a later stage it is also important to take this into account early in the design cycle so that the ASIC port will be efficient. This thesis investigates how to optimize a design for an FPGA through a number of case studies of important SoC components. One of these case studies discusses high speed processors and the tradeoffs that are necessary when constructing very high speed processors in FPGAs. The processor has a maximum clock frequency of 357~MHz in a Xilinx Virtex-4 devices of the fastest speedgrade, which is significantly higher than Xilinx' own processor in the same FPGA. Another case study investigates floating point datapaths and describes how a floating point adder and multiplier can be efficiently implemented in an FPGA. The final case study investigates Network-on-Chip architectures and how these can be optimized for FPGAs. The main focus is on packet switched architectures, but a circuit switched architecture optimized for FPGAs is also investigated. All of these case studies also contain information about potential pitfalls when porting designs optimized for an FPGA to an ASIC. The focus in this case is on systems where initial low volume production will be using FPGAs while still keeping the option open to port the design to an ASIC if the demand is high. This information will also be useful for designers who want to create IP cores that can be efficiently mapped to both FPGAs and ASICs. Finally, a framework is also presented which allows for the creation of custom backend tools for the Xilinx design flow. The framework is already useful for some tasks, but the main reason for including it is to inspire researchers and developers to use this powerful ability in their own design tools.
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Sadiq, Ejaz. "Short Message Network-On-Chip Interconnect for ASIC". Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-175761.
Testo completoAbstract (sommario):
The rise of large scale integration has resulted in large number of processing elements/cores on a single ASIC. Thus an efficient interconnect scheme between the different processing elements and interfaces is required. Bus based interconnect poses problems such as non-scalability. This thesis explores the Network-on-Chip (NOC) as a global interconnect scheme on a state of the art ASIC. Different On-chip interconnect techniques proposed by the academia/industry are summarized and Design space exploration of NOC schemes is performed. A Network-on-Chip interconnect, primarily utilized for short messaging service between the processing elements/nodes in the ASIC, is designed for Ericsson ASICs. Practical ASIC design issues such as non-uniform network topology (irregular mesh) and performance immunity of interconnect due to variations in the floorplan are addressed in the NOC design. The proposed Network-on-chip interconnect for Ericsson ASICs is evaluated in terms of varying traffic models, routing algorithms, NOC router FIFO depths and floor plans. The SystemC cycle accurate performance results of NOC are compared with the currently implemented Bus based solution for the Ericsson ASIC.
22
Han, Tony. "SWASAD Smith & Waterman-algorithm-specific ASIC design /". St. Lucia, Qld, 2001. http://www.library.uq.edu.au/pdfserve.php?image=thesisabs/absthe16391.pdf.
Testo completo
23
Dvořák, Vojtěch. "Implementace výpočtu FFT v obvodech FPGA a ASIC". Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2013. http://www.nusl.cz/ntk/nusl-220087.
Testo completoAbstract (sommario):
The aim of this thesis is to design the implementation of fast Fourier transform algorithm, which can be used in FPGA or ASIC circuits. Implementation will be done in Matlab and then this form of implementation will be used as a reference model for implementation of fast Fourier transform algorithm in VHDL. To verify the correctness ofdesign verification enviroment will be created and verification process wil be done. Program that will generate source code for various parameters of the module performing a fast Fourier transform will be created in the last part of this thesis.
24
DUTTA, MADHULIKA. "DESIGN OF AN INTEGRATED DETECTION SYSTEM FOR THE CHARACTERIZATION OF A BIOSENSOR ARRAY". University of Cincinnati / OhioLINK, 2003. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1054128572.
Testo completo
25
Olsson, Martin. "Portning och utökning av processor för ASIC och FPGA". Thesis, Linköping University, Department of Electrical Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-18250.
Testo completoAbstract (sommario):
In this master thesis, the possibilities of customizing a low-cost microprocessor with the purpose of replacing an existing microprocessor solution are investigated. A brief survey of suitable processors is carried out wherein a replacement is chosen. The replacement processor is then analyzed and extended with accelerators in order to match set requirements.
The result is a port of the processor Lattice Mico32 for the FPGA curcuit Xilinx Virtex-5 which replaces an earlier solution using Xilinx MicroBlaze. To reach the set requirements, accelerators for floating point arithmetics and FIR filtering have been developed. The toolchain for the processor has been modified to support the addition of accelerated floating point arithmetics.
A final evaluation of the presented solution shows that it fulfills the set requirements and constitutes a functional replacement for the previous solution.
26
Yesil, Soner. "A High-speed Asic Implementation Of The Rsa Cryptosystem". Master's thesis, METU, 2003. http://etd.lib.metu.edu.tr/upload/3/1124783/index.pdf.
Testo completoAbstract (sommario):
This thesis presents the ASIC implementation of the RSA algorithm, which is one of the most widely used Public Key Cryptosystems (PKC) in the world. In RSA Cryptosystem, modular exponentiation of large integers is used for both
encryption and decryption processes. The security of the RSA increases as the number of the bits increase. However, as the numbers become larger (1024-bit or higher) the challenge is to provide architectures, which can be implemented in hardware, operate at high clock speeds, use a minimum of resources and can be used
in real-time applications.
In this thesis, a semi-custom VLSI implementation of the RSA Cryptosystem is performed for both 512-bit and 1024-bit processes using 0.35µm AMI Semiconductor Standard Cell Libraries. By suiting the design into a systolic and regular architecture, the broadcasting signals and routing delays are minimized in the implementation. With this regular architecture, the results of 3ns clock period (627Kbps) using 87K gates (8.7mm2 with I/O pads) for the 512-bit implementation, and 4ns clock period (237Kps) using 132K gates (10.4mm2 with I/O pads) for the 1024-bit implementation have been achieved. These results are obtained for the worst-case conditions and they include the post-layout routing delays. The design is also verified in real time using the Xilinx V2000E FPGA on the Celoxica RC1000 Hardware. The 1024-bit VLSI implementation has been sent to IMEC for fabrication as a prototype chip through Europractice Multi-Project Wafer (MPW) runs.
27
Venditti, Michael B. "Receiver, transmitter, and ASIC design for optoelectronic-VLSI applications". Thesis, McGill University, 2003. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=84444.
Testo completoAbstract (sommario):
In modern digital systems, off-chip and intra-chip electrical interconnections suffer from a multitude of limitations as integrated circuits (ICs) continue to grow in size and processing capacity. Optical interconnects are capable of meeting the increasing I/O bandwidth needs in these systems. Optoelectronic-VLSI (OE-VLSI) technology incorporates optical I/O with ICs through the integration of arrays of optoelectronic devices with on-chip receiver and transmitter circuits. These optical I/Os are intended to replace or complement electrical interconnects for off-chip connections, and for connections between processing modules on the same chip or in a multi-chip module.The design of receivers, transmitters, and OE-VLSI application-specific integrated circuits (ASICs) are described from a system implementation perspective. Numerous techniques to overcome technological problems and allow the successful operation of large receiver and transmitter arrays are considered. The use of a fully differential optical and electrical architecture is strongly advocated. The testing of receiver and transmitter circuits and skew in highly parallel and synchronous digital systems employing optical receivers is also considered.
The major portion of this thesis details the design, construction, and optical and electrical testing of two OE-VLSI ASICs. The experiences obtained during the design and test of these ASICs, in conjunction with further analytical and simulation-based analyses, resulted in the conclusion that a fully differential optical and electrical architecture is optimal for OE-VLSI applications. The remainder of the thesis considers receiver and transmitter testing and the integration of testing methodologies at the ASIC level, and the management of skew in large receiver arrays.
28
Simpson, Zachary P. "Optimization of RSA Cryptography for FPGA and ASIC Applications". Thesis, University of North Texas, 2019. https://digital.library.unt.edu/ark:/67531/metadc1609146/.
Testo completoAbstract (sommario):
RSA cryptography is one of the most widely used cryptosystems in the world. FPGA/ASIC implementations for the classic RSA cryptosystem have high resource utilization due to the use of the Extended Euclid's algorithm for MOD inverse generation, the MOD exponent operation for encryption and decryption, and through non finite-field arithmetic. This thesis translates the RSA cryptosystem into the finite-field domain of arithmetic which greatly increases the range of encryption and decryption keys and replaces the MOD exponent with a multiplication. A new algorithm, the SPX algorithm, is presented and shown to outperform Euclid's algorithm, which is the most widely used mechanism to compute the GCD in FPGA implementations of RSA. The SPX algorithm is then extended to support the computation of the MOD inverse and supply decryption keys. Lastly, a finite-field RSA system is created and shown to support character encryption and decryption while being designed to be integrated into any larger system.
29
Zuo, Yongbo. "Fair Comparison of ASIC Performance for SHA-3 Finalists". Thesis, Virginia Tech, 2012. http://hdl.handle.net/10919/33446.
Testo completoAbstract (sommario):
In the last few decades, secure algorithms have played an irreplaceable role in the protection of private information, such as applications of AES on modems, as well as online bank transactions. The increasing application of secure algorithms on hardware has made implementations on ASIC benchmarks extremely important. Although all kinds of secure algorithms have been implemented into various devices, the effects from different constraints on ASIC implementation performance have never been explored before.
In order to analyze the effects from different constraints for secure algorithms, SHA-3 finalists, which includes Blake, Groestl, Keccak, JH, and Skein, have been chosen as the ones to be implemented for experiments in this thesis.
This thesis has first explored the effects of different synthesis constraints on ASIC performance, such as the analysis of performance when it is constrained for frequency, or maximum area, etc. After that, the effects of choosing various standard libraries were tested, for instance, the performance of UMC 130nm and IBM 130nm standard libraries have been compared. Additionally, the effects of different technologies have been analyzed, such as 65nm, 90nm, 130nm and 180nm of UMC libraries. Finally, in order to further understand the effects, experiments for post-layout analysis has been explored. While some algorithms remain unaffected by floor plan shapes, others have shown preference for a specific shape, such as JH, which shows a 12% increase in throughput/area with a 1:2 rectangle compared to a square.
Throughout this thesis, the effects of different ASIC implementation factors have been comprehensively explored, as well as the details of the methodology, metrics, and the framework of the experiments. Finally, detailed experiment results and analysis will be discussed in the following chapters.Master of Science
30
Gilda, Shubham. "ASIC design to monitor current for low frequency applications". University of Cincinnati / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1291390501.
Testo completo
31
Suikkanen, E. (Essi). "Detection algorithms and ASIC designs for MIMO–OFDM downlink receivers". Doctoral thesis, Oulun yliopisto, 2017. http://urn.fi/urn:isbn:9789526215013.
Testo completoAbstract (sommario):
Abstract Future wireless systems will require high data rate with low transmit and processing power consumption. A combination of multiple-input multiple-output (MIMO) transmission with orthogonal frequency division multiplexing (OFDM) is a promising approach for offering better performance in terms of the capacity and quality of service (QoS). The detector in the wireless receiver is one of the highest power consuming parts. In order to minimize the power consumption, it is desirable for the detector to be able to change the detection algorithm to suit the channel conditions. In this thesis work, we study the suitability of different MIMO detection algorithms for adaptive operation. The selective spanning with fast enumeration (SSFE), K-best list sphere detector (LSD), linear minimum mean square error (LMMSE), and successive interference cancellation (SIC) detectors are compared to each other in terms of communications performance in the 4 × 4 and 8 × 8 MIMO–OFDM systems. The impact of least squares (LS) and minimum mean square error (MMSE) channel estimation methods, mobile speed, and transmit precoding at the base station on detector algorithm selection is also considered. The SIC detector is shown to suffer from error propagation in poor channel conditions. The SSFE detector is unable to outperform the K-best LSD and is occasionally outperformed by the LMMSE detector. The LMMSE detector is able to outperform the K-best LSD on the low signal-to-noise (SNR) regime when the mobile speed is high and the spatial channel correlation is low or moderate; it is also found to be more robust against channel estimation errors. Because a realistic adaptive detector is expected to support only two detection algorithms, the K-best LSD and LMMSE are selected based on the performance results for application specific integrated circuit (ASIC) architecture design and further comparison. The chosen algorithms are evaluated by considering the performance and implementation results. The K-best LSD provides good performance under challenging channel conditions with the cost of high complexity and power consumption. The LMMSE detector is energy efficient but performs poorly in correlated channels. However, exceptions exist, and detailed results on when to use a simple detector and when to use a complex detector are providedTiivistelmä Tulevaisuuden langattomat tietoliikennejärjestelmät edellyttävät suurta datanopeutta ja vähäistä tehonkulutusta datan lähetyksessä ja käsittelyssä. Monitulo-monilähtötekniikan (MIMO) ja monikantoaaltomoduloinnin (OFDM) yhdistelmä (MIMO–OFDM) on lupaava lähestymistapa hyvän suorituskyvyn saavuttamiseksi, sekä kapasiteetin että luotettavuuden kannalta. Yksi langattoman vastaanottimen eniten tehoa kuluttavista osista on ilmaisin. Tehonkulutuksen minimoimiseksi tulisi ilmaisimen pystyä vaihtamaan ilmaisinalgoritmia radiokanavan olosuhteisiin sopivaksi. Tässä väitöskirjatyössä tarkastellaan erilaisten MIMO-ilmaisinalgoritmien sopivuutta mukautuvaan ilmaisuun. Listapalloilmaisimen (list sphere detector, LSD), valikoivan laajennuksen listailmaisimen (selective spanning with fast enumeration, SSFE), lineaarisen pienimmän keskineliövirheen ilmaisimen (linear minimum mean square error, LMMSE) ja peräkkäisen häiriönpoistoilmaisimen (successive interference cancellation, SIC) suorituskykyjä verrataan toisiinsa sekä 4 × 4 että 8 × 8 MIMO–OFDM järjestelmissä. Pienimmän neliösumman (LS) ja pienimmän keskineliövirheen (MMSE) kanavaestimointialgoritmien, vastaanottimen nopeuden ja lähetyksen esikoodauksen vaikutus ilmaisinalgoritmin valintaan otetaan huomioon vertailussa. Haastavissa kanavaolosuhteissa SIC-ilmaisin kärsii virheen etenemisestä. SSFE-ilmaisimen suorituskyky on huonompi kuin K-best LSD-ilmaisimen, ja joissakin tilanteissa huonompi kuin LMMSE-ilmaisimen. LMMSE-ilmaisin pystyy parempaan suorituskykyyn kuin K-best LSD-ilmaisin kun signaali-kohinasuhde (SNR) on pieni, vastaanottimen nopeus on suuri ja radiokanavan korrelaatio on matala tai kohtalainen. LMMSE-ilmaisin myös kestää epätarkat kanavaestimaatit paremmin kuin LSD-ilmaisin. Realistisessa vastaanottimessa mukautuva ilmaisin tukee vain kahta ilmaisinalgoritmia, ja sen takia K-best LSD and LMMSE-ilmaisimet valittiin suorituskykytulosten perusteella toteutettaviksi ASIC-teknologialla. Valittuja ilmaisinalgoritmeja arvioidaan sekä suorituskyvyn että toteutustulosten perusteella. K-best LSD-ilmaisimella on hyvä suorituskyky haastavissa kanavaolosuhteissa, mutta toteutus on monimutkainen ja tehonkulutus korkea. LMMSE-ilmaisin on energiatehokas, mutta suorituskyky on huono korreloivissa kanavissa. Poikkeuksia näihin tilanteisiin kuitenkin esiintyy, ja työssä esitetään suositus milloin yksinkertaista ilmaisinta voidaan käyttää tehonkulutuksen minimoimiseksi ja milloin taas monimutkainen ilmaisin on välttämätön luotettavan tiedonsiirron takaamiseksi
32
Dulipovici, Andrei. "Signatures des circuits ASIC - approche pour détermination des pannes systématiques". Mémoire, École de technologie supérieure, 2011. http://espace.etsmtl.ca/886/1/DULIPOVICI_Andrei.pdf.
Testo completoAbstract (sommario):
Ce mémoire explore diverses stratégies de dépistage des pannes systématiques dans les
circuits VLSI s’appuyant sur la notion de signatures construites à partir des erreurs détectées
par les bascules des circuits sous test. Faisant l'hypothèse que les noeuds d’un circuit et la
surface qu’ils occupent sont reliés à l’apparition des pannes dans une puce, on peut calculer
la probabilité d’une panne systématique et la signature de défectuosités spécifiques de cette
puce. En créant différentes signatures par l’utilisation des différentes informations, le projet
analyse l’apport des informations additionnelles, la signature reliée à la surface des noeuds
étant la plus élaborée. Au total, quatre types de signature ont été investiguées.
Cette approche typiquement DFM (Design for Manufacturability) fait intervenir des
paramètres de fabrication, la capacité parasite et les couches métalliques impliquées, ainsi
que des paramètres de conception comme les marges des règles appliquées pour l’exécution
des dessins des masques. Elle a nécessité le développement de divers utilitaires et scripts
complémentant les outils commerciaux traditionnellement utilisés dans la conception d’un
circuit intégré. Une analyse comparative des résultats obtenus pour déterminer la cause des
pannes systématiques avec les différentes signatures est présentée. Par rapport à la signature
de pondération constante (pannes équiprobables), les signatures pondérées par les capacités
parasites ou les couches métalliques apportent peu de différenciation principalement dû au
fait que les signaux dits globaux (ex. horloge, reset) sont exclus de l’analyse. Pour le dernier
type de signature, à la pondération des surfaces efficaces des polygones DRC, qui a été
présenté en trois variantes de signature, le volume du traitement est plus important. Les trois
variantes, obtenues grâce à une utilisation différente des résultats de Fastscan, ciblent plus
précisément les causes probables de la défaillance systématique offrant de l’aide
supplémentaire au débogage du circuit pour la deuxième et la troisième alternative.
33
Murphy, Julian. "Standard cell and full custom power-balanced logic : ASIC implementation". Thesis, University of Newcastle Upon Tyne, 2008. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.533690.
Testo completo
34
Auras, Dominik [Verfasser], Gerd [Akademischer Betreuer] Ascheid e Andreas [Akademischer Betreuer] Burg. "MIMO Detector ASIC Design / Dominik Auras ; Gerd Ascheid, Andreas Burg". Aachen : Universitätsbibliothek der RWTH Aachen, 2017. http://d-nb.info/116249963X/34.
Testo completo
35
Nygård, Skalman Jonas. "CO2 Sensor Core on FPGA : ASIC prototyping and cost estimates". Thesis, Mittuniversitetet, Avdelningen för elektronikkonstruktion, 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:miun:diva-35963.
Testo completoAbstract (sommario):
Demand of CO2 gas sensors is expected to continue to increase in the foreseeable future, due to an increasing awareness of air pollution and fossil fuel emissions. A truly low cost and accurate NDIR sensor has the potential of greatly benefiting the environment by an increased human awareness due to CO2 measurements. In the objective to reach these goals, a CO2 sensor core on an ASIC needs to be investigated. In this study an ASIC prototype design is tested on an FPGA and evaluated towards logic resource requirements, power analysis and estimated cost impacts towards a full ASIC. The results show that a potential ASIC implementation would have a very small cost impact on a full system design if the use of a preexisting ASIC design is utilized. Using a manufacturing process of 180 nm, the total logic implementation would require between 0.54-0.76 mm2. The cost impact of such a logic area would be around $0.025 USD per chip. The power consumption of the logical part would also be very small when compared to the various analog components of a full system design.
36
Green, Forrest Oliver Reece. "ALA ASIC : a standard cell library for Asynchronous Logic Automata". Thesis, Massachusetts Institute of Technology, 2010. http://hdl.handle.net/1721.1/61160.
Testo completoAbstract (sommario):
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010.Cataloged from PDF version of thesis.
Includes bibliographical references (p. 83-84).
This thesis demonstrates a hardware library with related tools and designs for Asynchronous Logic Automata (ALA) gates in a generic 90nm process development kit that allows a direct one-to-one mapping from software to hardware. Included are basic design tools to enable writing ALA software, the necessary hardware designs for implementation, and simulation techniques for quickly verifying correctness and performance. This thesis also documents many of the hazards and opportunities for improving them including helpful variations to the ALA model, design tool needs, better simulation models, and hardware improvements. To embody software you could compile a hardware description language to an FPGA or synthesize it all the way to transistors. Alternatively, you could use your favorite high level language and run it on a standard processor. However, the widening gap between traditional models of computation and the reality of the underlying hardware has led to massive costs for design and fabrication as well as numerous issues for scalability and portability. Unlike any of these other approaches, ALA aligns computational and physical descriptions making it possible to use a direct one-to-one mapping to convert an ALA program to a circuit or other physical artifact that executes that program. No unpredictable fitters or compilers are needed and no extra expertise is needed for specific technologies. Similar to Mead-Conway design rules ALA designs trade flexibility for portability and ease of design. Unlike Mead- Conway design rules, ALA designs do not require any further verification-the design rule primitives are logical operations suitable for use in analysis at the algorithmic level. ALA separates many of the scaling issues that plague integrated circuit design by cleanly separating algorithm design from hardware engineering-improving design verification, tape-out costs (by reusing masks), yield, portability, and the ability to break designs across multiple chips. ALA designs are not limited to integrated circuits and could just as easily be implemented in microfluidics, magnetic logic, or a lattice of molecular logic gates. Although each of these technologies would require implementing a basic set of gates and tiling rules, hardware (or equivalently software) can be developed using the same deterministic noiseless digital abstraction using the same design in many different technologies.
by Forrest Oliver Reece Green.
M.Eng.
37
Zaveri, Jainish K. "Asic Design of RF Energy Harvester Using 0.13UM CMOS Technology". DigitalCommons@CalPoly, 2018. https://digitalcommons.calpoly.edu/theses/1940.
Testo completoAbstract (sommario):
Recent advances in wireless sensor nodes, data acquisition devices, wearable and implantable medical devices have paved way for low power (sub 50uW) devices. These devices generally use small solid state or thin film batteries for power supply which need replacement or need to be removed for charging. RF energy harvesting technology can be used to charge these batteries without the need to remove the battery from the device, thus providing a sustainable power supply. In other cases, a battery can become unnecessary altogether. This enables us to deploy wireless network nodes in places where regular physical access to the nodes is difficult or cumbersome.
This thesis proposes a design of an RF energy harvesting device able to charge commercially available thin film or solid-state batteries. The energy harvesting amplifier circuit is designed in Global Foundry 0.13um CMOS technology using Cadence integrated circuit design tools. This Application Specific Integrated Circuit (ASIC) is intended to have as small a footprint as possible so that it can be easily integrated with the above-mentioned devices. While a dedicated RF power source is a direct solution to provide sustainable power to the harvesting circuit, harvesting ambient RF power from TV and UHF cellular frequencies increases the possibilities of where the harvesting device can be placed. The biggest challenge for RF energy harvesting technology is the availability of adequate amount of RF power. This thesis also presents a survey of available RF power at various ultra-high frequencies in San Luis Obispo, CA.The idea is to determine the frequency band which can provide maximum RF power for harvesting and design a harvester for that frequency band.
38
Freeman, Michelle S. "ASC 842: Implementing the New Leasing Standard". Digital Commons @ East Tennessee State University, 2018. https://dc.etsu.edu/etsu-works/5771.
Testo completoAbstract (sommario):
With the updated leasing standard from the Financial Accounting Standards Board (FASB) going into effect, companies will need to understand the basic principles and new definition of a lease, as well as the types of leases. Then they will be able to account for them properly, and more information will be transparent to the users.
39
Bertilsson, Erik. "A Scalable Architecture for Massive MIMO Base Stations Using Distributed Processing". Thesis, Linköpings universitet, Datorteknik, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-133998.
Testo completoAbstract (sommario):
Massive MIMO is an emerging technology for future wireless systems that has received much attention from both academia and industry recently. The most prominent feature of Massive MIMO is that the base station is equiped with a large number of antennas. It is therefore important to create scalable architectures to enable simple deployment in different configurations. In this thesis, a distributed architecture for performing the baseband processing in a massive OFDM MU-MIMO system is proposed and analyzed. The proposed architecture is based on connecting several identical nodes in a K-ary tree. It is shown that, depending on the chosen algorithms, all or most computations can be performed in a distrbuted manner. Also, the computational load of each node does not depend on the number of nodes in the tree (except for some timing issues) which implies simple scalability of the system. It is shown that it should be enough that each node contains one or two complex multipliers and a few complex adders running at a couple of hundres MHz to support specifications similar to LTE. Additionally the nodes must communicate with each other over links with data rates in the order of some Gbps. Finally, a VHDL implementation of the system is proposed. The implementation is parameterized such that a system can be generated from a given specification.
40
Lin, Cheng-Hsien Kenny. "An ASIC application for DNA sequencing by Smith-Waterman algorithm (DNASSWA) /". [St. Lucia, Qld.], 2004. http://www.library.uq.edu.au/pdfserve.php?image=thesisabs/absthe18716.pdf.
Testo completo
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Mahnke, Torsten. "Low power ASIC design using voltage scaling at the logic level". [S.l. : s.n.], 2003. http://deposit.ddb.de/cgi-bin/dokserv?idn=970311974.
Testo completo
42
Demirci, Kemal Safak. "Chemical microsystem based on integration of resonant microsensor and CMOS ASIC". Diss., Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/41182.
Testo completoAbstract (sommario):
The main topic of this thesis is the development of a chemical microsystem based on integration of a silicon-based resonant microsensor and a CMOS ASIC for portable sensing applications. Cantilever and disk-shape microresonators have been used as mass-sensitive sensors. Based on the characteristics of the microresonators, CMOS integrated interface and control electronics have been implemented. The CMOS ASIC utilizes the self-oscillation method, which incorporates the microresonator in an amplifying feedback loop as the frequency determining element. In this manner, the ASIC includes a main feedback loop to sustain oscillation at or close to the fundamental resonance frequency of the microresonator. For stable oscillation, an automatic gain control loop regulates the oscillation amplitude by controlling the gain of the main feedback loop. In addition, an automatic phase control loop has been included to adjust the phase of the main feedback loop to ensure an operating point as close as possible to the resonance frequency, resulting in improved frequency stability. The CMOS chip has been interfaced to cantilever and disk-shape microresonators and short-term frequency stabilities as low as 3.4×10-8 in air have been obtained with a 1 sec gate time.
The performance of the implemented microsystem as a chemical sensor has been evaluated experimentally with microresonators coated with chemically sensitive polymer films. With a gas-phase chemical measurement setup constructed in this work, chemical measurements have been performed and different concentrations of VOCs, such as benzene, toluene and m-xylene have been detected with limits of detection of 5.3 ppm, 1.2 ppm and 0.35 ppm, respectively.
To improve the long-term stability in monitoring applications with slowly changing analyte signatures, a method to compensate for frequency drift caused by environmental disturbances has been implemented on the CMOS chip. This method uses a controlled stiffness modulation generated by a frequency drift compensation circuit to track the changes in the resonator's Q-factor in response to variations in the environmental conditions. The measured Q-factor is then used to compensate for the frequency drift using an initial calibration step. The feasibility of the proposed method has been verified experimentally by compensating for temperature-induced frequency drift during gas-phase chemical measurements.
43
McIntosh, James Alexander. "Implementation of an ASIC for detector instrumentation in nuclear physics applications". Thesis, University of Edinburgh, 1996. http://hdl.handle.net/1842/1781.
Testo completoAbstract (sommario):
A prototype ASIC (EFT1) for silicon strip detector instrumentation has been designed and tested. The ASIC design contains the electronics necessary for preamplification, shaping, hit detection, and data readout control. The specific ation of the ASIC makes it suitable for charged particle spectroscopy applications with the implementation of multiple channels on a single chip reducing the cost compared to expensive discrete instrumentation. The ASIC contains features which have not been implemented before, or are at least unusual, on integrated instrumentation such as the ability to select two gain ranges, the use of a flattop shaper to increase integral linearity and a current driven discriminator output with adjustable voltage to reduce crosstalk effects on sensitive inputs. The testing performed on the ASIC revealed errors that can be removed in further design of the chip which will be implemented using radiationhard silicon technology.
44
Ke, Chen-Maih, e 柯清邁. "ASIC implementationof DCT". Thesis, 2000. http://ndltd.ncl.edu.tw/handle/95414103571037761257.
Testo completoAbstract (sommario):
碩士義守大學
電子工程學系
88
With the significant property of high signal density, discrete cosine transform (DCT) has been applied in many fields of digital signal processing. The design of the DCT or IDCT chips need to consider several important factors such as the chip area, running frequency and delay time. In this paper, we develop an architectures for DCT computation and compared with architectures that other authors presented before. The ASIC implementation for these DCT architectures is carry out by using Verilog hardware description language to synthesis the cell-based and an Altera Flex 10 k chip.
45
Adarsha, Rao S. J. "Polymorphic ASIC : For Video Decoding". Thesis, 2013. http://hdl.handle.net/2005/3291.
Testo completoAbstract (sommario):
Video applications are becoming ubiquitous in recent times due to an explosion in the number of devices with video capture and display capabilities. Traditionally, video applications are implemented on a variety of devices with each device targeting a specific application. However, the advances in technology have created a need to support multiple applications from a single device like a smart phone or tablet. Such convergence of applications necessitates support for interoperability among various applications, scalable performance meet the requirements of different applications and a high degree of reconfigurability to accommodate rapid evolution in applications features. In addition, low power consumption requirement is also very stringent for many video applications.
The conventional custom hardware implementations of video applications deliver high performance at low power consumption while the recent MPSoC implementations enable high degree of interoperability and are useful to support application evolution. In this thesis, we combine the best features of custom hardware and MPSoC approaches to design a Polymorphic ASIC. A Polymorphic ASIC is an integrated circuit designed to meet the requirements of several applications belonging to a particular domain. A polymorphic ASIC consists of a fabric of computation, storage and communication resources, using which applications are composed dynamically. Although different video applications differ widely in the internal de-tails of operation, at the heart of almost every video application is a video codec (encoder and decoder). The requirements of scalability, high performance and low power consumption are very stringent for video decoding. Therefore this thesis focuses mainly on the architectural design of a Polymorphic ASIC for video decoding.
We present an unified software and hardware architecture (USHA) for Polymorphic ASIC. USHA is a tiled architecture which uses loosely coupled processor and hardware tiles that are software programmable and hardware reconfigurable respectively. The distinctive feature of Polymorphic ASIC is the static partitioning of the application and dynamic mapping of ap-plication processes onto the computational tiles. Depending on the application scenarios, a process may be mapped onto one of the hardware or processor tiles. Polymorphic ASIC incor-porates a network–on–chip (NoC) to achieve flexible communication across different tiles.
Formulation of a programming framework for Polymorphic ASIC requires an implementation model that captures the structure of video decoder applications as well as the properties of the Polymorphic ASIC architecture. We derive an implementation model based on a combination of parametric polyhedral process networks, stream based functions and windowed dataflow models of computation. The implementation model leads to a process network oriented compilation flow that achieves realization agnostic application partitioning and enables seamless migration across uniprocessor, multi–processor, semi hardware and full hardware configurations of a video decoder. The thesis also presents an application QoS aware scheduler that selects a decoder configuration that best meets the application performance requirements, thereby enabling dynamic performance scaling.
The memory hierarchy of Polymorphic ASIC makes use of an application specific cache. Through a combined analysis of miss rate and external memory bandwidth, we show that the degradation in decoder performance due to memory stall cycles depends on the properties of the video being decoded as well as the behavior of the external memory interface. Based on this observation, we present the design of a reconfigurable 2–D cache architecture which can adjust its parameters in accordance with the characteristics of the video stream being decoded.
We validate the Polymorphic ASIC using a proof–of–concept implementation on an FPGA. The performance of H.264 decoder on Polymorphic ASIC is evaluated for uniprocessor, multi processor, hardware accelerated and full hardware configurations. The scaling in performance delivered by these configurations shows that the Polymorphic ASIC enables the application to achieve super linear speedups [1]. The experimental results show that different implementations of a H.264 video decoder on the Polymorphic ASIC can deliver performance comparable to a wide spectrum of devices ranging from embedded processor like ARM 9 to MPSoCs like IBM Cell. We also present the energy consumption of various configurations of video decoders on Polymorphic ASIC and an application to configuration mapping aimed at minimizing the overall energy consumption of a Polymorphic ASIC.
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邱志豪. "An Economic Evaluator for ASIC Development". Thesis, 1998. http://ndltd.ncl.edu.tw/handle/51823616215903670442.
Testo completoAbstract (sommario):
碩士中華大學
電機工程研究所
86
Cost, quality, and time to market are the basic constraints of any design project. The costs developing a ASIC include design costs, production costs, and test costs. Costs of components are sensitive to competition. For example, changing cost by $1 may change list price by $3~$4. Without understanding the relationship of cost to list price the component designer may not understand the impact on list price of adding, deleting, or replacing components. The feature of eletronic products is high volume and short lifetime. The short lifetimes have made it increasingly important to get new products to market on time. If we are late to market we will have less time to sell our product. As a result we will sell less, we will make less profit and we may also lose market share. Thus, design schedule is a key factor in developing a new product or component. The traditional way of reducing schedules through increase in team size is ineffective an costly. But, sometime we must adopt this way to get new product to market earlier in order to make more profit. In this text we present a economic evaluator to facilitate the prediction of all costs influenced by the ASIC development. The cost model is integrated with a market model to evaluate the influence of a late project. The evaluator is intended for use by ASIC designers and project leaders, and the analysis can help when decisions about design schedule and costs need to be made for a project.
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周家弘. "Using ASBR Reactor to Produce Hydrogen". Thesis, 2001. http://ndltd.ncl.edu.tw/handle/54501465521805013547.
Testo completo
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Philipp, Torsten Scarbata Gerd. "Layoutsynthese von Datenwegstrukturen für den ASIC-Entwurf /". 1991. http://www.gbv.de/dms/ilmenau/toc/019694709.PDF.
Testo completo
49
He, Yi-Ru, e 何宜儒. "Buffer Insertion for ASIC and FPGA Designs". Thesis, 2007. http://ndltd.ncl.edu.tw/handle/51612808809154222102.
Testo completoAbstract (sommario):
碩士國立清華大學
資訊工程學系
95
With the technology process going into nanometer regime, the interconnect delay is a crucial determining factor of circuit performance in modern VSLI designs. Buffer insertion is one of the effective technique to improve the circuit performance. We explore two different problems related to buffer insertion in ASIC and FPGA designs in this thesis. In modern ASIC designs, a large number of buffers need to be inserted to a large number of nets to improve performance and/or signal integrity. These buffers increase the power consumption and occupy silicon area. So it is important to avoid over-buffering. Buffering spaces are more limited in the denser regions of a layout. Thus it is also necessary to reserve the more premium buffering spaces in the denser regions until they are absolutely needed during physical synthesis. We present a buffer insertion algorithm with consideration of both power dissipation and design density under a given timing constraint for ASIC designs. We propose two formulations for this multi-objective problem and a heuristic solver using Lagrangian relaxation technique. In FPGAs, signals passing through a long wire do not always exit at the end of the wire. Therefore, the expected delay other than end to end delay of the long wire should be optimized. We adopt a dynamic programming based approach to insert buffers to minimize the expected delay for FPGA designs and a Lagrangian relaxation based method to achieve low power and timing closure. Experiments for ASIC buffering show that our method can significantly improve the overall design density while achieving low power to obtain better timing closure. The experiments for FPGA buffering show that our method can improve the expected delay by up to 17% compared to the buffered interconnect which only considers end to end delay optimization.
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Mlynek, Mario Beierke Stefan. "Entwicklung und Validierung von ASIC-Testsystemen am Beispiel eines zu entwickelnden Rapid Prototyping Testsystems für einen RFIDAutomotive Reader ASIC /". 2008. http://www.gbv.de/dms/ilmenau/abs/564558451mlyne.txt.
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