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Letteratura scientifica selezionata sul tema "CONTINOUS TIME CIRCUITS"

Autore: Grafiati

Pubblicato: 11 settembre 2023

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Articoli di riviste sul tema "CONTINOUS TIME CIRCUITS"

1

Califano, Alfonso Maria, Laurent Bitker, Ian Baldwin, Nigel Fealy e Rinaldo Bellomo. "Circuit Survival during Continuous Venovenous Hemodialysis versus Continuous Venovenous Hemofiltration". Blood Purification 49, n. 3 (2020): 281–88. http://dx.doi.org/10.1159/000504037.

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Background: Continuous renal replacement therapy (CRRT) technique may affect circuit lifespan. A shorter circuit life may reduce CRRT efficacy and increase costs. Methods: In a before-and-after study, we compared circuit median survival time during continuous venovenous hemofiltration (CVVH) versus continuous venovenous hemodialysis (CVVHD). We performed log-rank mixed effects univariate analysis and Cox mixed effect regression modeling to define predictors of circuit lifespan. Results: We compared 197 CVVHD and 97 CVVH circuits in 39 patients. There was no overall difference in circuit lifespan. When no anticoagulation was used, median circuit survival time was shorter for CVVH circuits (5 h, 95% CI 3–7 vs. 10 h, 95% CI 8–13, p < 0.01). Moreover, CVVHD, lower platelets levels, and longer activated partial thromboplastin time independently predicted longer circuit median survival time. Conclusions: CVVHD is associated with longer circuit median survival time than CVVH when no anticoagulation is used and is an independent predictor of circuit survival.

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2

Bierer, P., A. W. Holt, A. D. Bersten, J. L. Plummer e A. H. Chalmers. "Haemolysis Associated with Continuous Venovenous Renal Replacement Circuits". Anaesthesia and Intensive Care 26, n. 3 (giugno 1998): 272–75. http://dx.doi.org/10.1177/0310057x9802600307.

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Extracorporeal circuits can cause haemolysis resulting in an increase in plasma-free haemoglobin (PFHb). High pressures and clots within the circuit have been identified as factors increasing the likelihood of haemolysis. Continuous venovenous haemodiafiltration (CVVHD) is associated with high circuit pressures as the pump-driven circuit clots over a period of time. PFHb was measured during CVVHD to determine if circuit life, maximum circuit pressure or the clotting of the haemofilter was associated with evidence of haemolysis. Circuit life up to 50 hours, circuit pressures or haemofilter clotting had no significant effect on PFHb. There was a small rise in PFHb in the circuits lasting beyond 50 hours. CVVHD circuits can be run up to 50 hours without concern for haemolysis.

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3

PRAMOD, M., e T. LAXMINIDHI. "LOW POWER CONTINUOUS TIME COMMON MODE SENSING FOR COMMON MODE FEEDBACK CIRCUITS". Journal of Circuits, Systems and Computers 19, n. 03 (maggio 2010): 519–28. http://dx.doi.org/10.1142/s0218126610006268.

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Continuous common mode feedback (CMFB) circuits having high input impedance and low distortion are proposed. The proposed circuits are characterized for 0.18 μm CMOS process with 1.8 V supply. Simulation results indicate that the proposed common mode detector consumes no standby power and CMFB circuit consumes 27–34% less power than previous high swing CMFB circuits.

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4

Kaczorek, Tadeusz. "SINGULAR FRACTIONAL CONTINUOUS-TIME AND DISCRETE-TIME LINEAR SYSTEMS". Acta Mechanica et Automatica 7, n. 1 (1 marzo 2013): 26–33. http://dx.doi.org/10.2478/ama-2013-0005.

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Abstract New classes of singular fractional continuous-time and discrete-time linear systems are introduced. Electrical circuits are example of singular fractional continuous-time systems. Using the Caputo definition of the fractional derivative, the Weierstrass regular pencil decomposition and Laplace transformation the solution to the state equation of singular fractional linear systems is derived. It is shown that every electrical circuit is a singular fractional systems if it contains at least one mesh consisting of branches with only ideal supercondensators and voltage sources or at least one node with branches with supercoils. Using the Weierstrass regular pencil decomposition the solution to the state equation of singular fractional discrete-time linear systems is derived. The considerations are illustrated by numerical examples.

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5

Jiao, Su Min, Cai Hong Wang e Xue Mei Wang. "Large-Scale Analog Circuit Evolutionary Design Using a Real-Coded Scheme". Applied Mechanics and Materials 220-223 (novembre 2012): 2036–39. http://dx.doi.org/10.4028/www.scientific.net/amm.220-223.2036.

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Analog circuits are of great importance in electronic system design. Recent evolutionary design results are usually small-scale analog circuits. This paper proposes a real-coded mechanism and uses it in the large-scale analog circuit evolutionary design. The proposed scheme evolves the circuit topology and size to a uniformed continuous space, in which the circuit representation is closed and of causality. Experimental results show that the proposed scheme can work successfully on many analog circuits with different kinds of characteristics. Comparing with other evolutionary methods before, the proposed scheme performs better on large-scale problems of circuit synthesis with higher search efficiency, lower computational complexity, and less computing time.

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6

Kaczorek, T. "Positive time-varying continuous-time linear systems and electrical circuits". Bulletin of the Polish Academy of Sciences Technical Sciences 63, n. 4 (1 dicembre 2015): 837–42. http://dx.doi.org/10.1515/bpasts-2015-0095.

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AbstractThe positivity of time-varying continuous-time linear systems and electrical circuits are addressed. Necessary and sufficient conditions for the positivity of the systems and electrical circuits are established. It is shown that there exists a large class of positive electrical circuits with time-varying parameters. Examples of positive electrical circuits are presented.

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7

Lu, Weijun, Ning Bao, Tangren Zheng, Xiaorui Zhang e Yutong Song. "Memristor-Based Read/Write Circuit with Stable Continuous Read Operation". Electronics 11, n. 13 (27 giugno 2022): 2018. http://dx.doi.org/10.3390/electronics11132018.

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In recent years, computation-intensive applications, such as artificial intelligence, video processing and encryption, have been developing rapidly. On the other hand, the problems of “storage wall” and “power consumption wall” for the traditional storage and computing separated architectures limit the computing performance. The computational circuits and memory cells based on nonvolatile memristors are unified and become a competitive solution to this problem. However, there are various problems that prevent memristor-based circuits from entering practical applications, one of which is the memristor state deviation problem caused by continuous reading. In this paper, we study some circuits studied by predecessors on read/write circuit, compare the experimental results, analyze the reason for the resistance state deviation of memristor, and put forward a new parallel structure of memristor based on opposite polarity. The logic “1” and logic “0” are represented by the positive and negative voltage difference of two memristors with opposite polarity, which can effectively alleviate the problem of the resistance state deviation caused by continuous reading. A reading voltage of 2 V is applied to the four circuits at the same time, and continuous reading is carried out until the output voltage becomes stable. The voltage offset of the optimized circuit when reading logic “0” is reduced to 78 mV, which is significantly smaller than that of other circuits. In addition, when reading logic “1”, it has the effect of enhancing the information stored in the memristor.

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Baryshev, I. V., К. А. Scherbina, E. P. Msallam, M. А. Vonsovitch e A. V. Odokienko. "The experimental research of filtration quality of doppler signal spectral structure by modu-lated filter". Radiotekhnika, n. 191 (22 dicembre 2017): 150–57. http://dx.doi.org/10.30837/rt.2017.4.191.14.

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The comparative analysis of quantitative assessments of filtering by six performance indices of filter circuits of continuous-wave Doppler signal of 1st order PLL, 2nd order PLL, FLL with narrow-band filter circuit quadrature FM-detector based on synchronized oscillator with forced frequency tuning is carried out. The total average performance indices of the circuit with SG exceeded any of the compared indices by 1.5 times, with a tenfold increase in separate parameters. At the same time the method of indices calculation of filter circuits with SG is developed and simple calculation formulas are obtained.

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Tymoshchuk, Pavlo, e s. Shatny. "Hardware Implementation of Parallelized Fuzzy Adaptive Resonance Theory Neural Network". Computer Design Systems. Theory and Practice, n. 1 (2020): 1–11. http://dx.doi.org/10.23939/cds2019.01.001.

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A hardware implementation design of parallelized fuzzy Adaptive Resonance Theory neural network is described and simulated. Parallel category choice and resonance are implemented in the network. Continuous-time and discrete-time winner-take-all neural circuits identifying the largest of M inputs are used as the winner-take-all units. The continuous-time circuit is described by a state equation with a discontinuous right-hand side. The discrete-time counterpart is governed by a difference equation. Corresponding functional block-diagrams of the circuits include M feed-forward hard- limiting neurons and one feedback neuron, which is used to compute the dynamic shift of inputs. The circuits combine arbitrary finite resolution of inputs, high convergence speed to the winner-take-all operation, low computational and hardware implementation complexity, and independence of initial conditions. The circuits are also used for finding elements of input vector with minimal/maximal values to normalize them in the range [0,1].

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Maass, Wolfgang, Thomas Natschläger e Henry Markram. "Real-Time Computing Without Stable States: A New Framework for Neural Computation Based on Perturbations". Neural Computation 14, n. 11 (1 novembre 2002): 2531–60. http://dx.doi.org/10.1162/089976602760407955.

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A key challenge for neural modeling is to explain how a continuous stream of multimodal input from a rapidly changing environment can be processed by stereotypical recurrent circuits of integrate-and-fire neurons in real time. We propose a new computational model for real-time computing on time-varying input that provides an alternative to paradigms based on Turing machines or attractor neural networks. It does not require a task-dependent construction of neural circuits. Instead, it is based on principles of high-dimensional dynamical systems in combination with statistical learning theory and can be implemented on generic evolved or found recurrent circuitry. It is shown that the inherent transient dynamics of the high-dimensional dynamical system formed by a sufficiently large and heterogeneous neural circuit may serve as universal analog fading memory. Readout neurons can learn to extract in real time from the current state of such recurrent neural circuit information about current and past inputs that may be needed for diverse tasks. Stable internal states are not required for giving a stable output, since transient internal states can be transformed by readout neurons into stable target outputs due to the high dimensionality of the dynamical system. Our approach is based on a rigorous computational model, the liquid state machine, that, unlike Turing machines, does not require sequential transitions between well-defined discrete internal states. It is supported, as the Turing machine is, by rigorous mathematical results that predict universal computational power under idealized conditions, but for the biologically more realistic scenario of real-time processing of time-varying inputs. Our approach provides new perspectives for the interpretation of neural coding, the design of experiments and data analysis in neurophysiology, and the solution of problems in robotics and neurotechnology.

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Tesi sul tema "CONTINOUS TIME CIRCUITS"

1

Kwan, Jonathan Carleton University Dissertation Engineering Electrical. "Noise analysis and simulation of switched-capacitor circuits using a continuous time circuit simulator". Ottawa, 1988.

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2

Durham, Anna Mary. "Digitally tunable continuous-time filters for VLSI". Thesis, University of Southampton, 1992. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.315304.

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Vigoda, Benjamin William 1973. "Continuous-time analog circuits for statistical signal processing". Thesis, Massachusetts Institute of Technology, 2003. http://hdl.handle.net/1721.1/62962.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, School of Architecture and Planning, Program in Media Arts and Sciences, 2003.
Vita.
Includes bibliographical references (p. 205-209).
This thesis proposes an alternate paradigm for designing computers using continuous-time analog circuits. Digital computation sacrifices continuous degrees of freedom. A principled approach to recovering them is to view analog circuits as propagating probabilities in a message passing algorithm. Within this framework, analog continuous-time circuits can perform robust, programmable, high-speed, low-power, cost-effective, statistical signal processing. This methodology will have broad application to systems which can benefit from low-power, high-speed signal processing and offers the possibility of adaptable/programmable high-speed circuitry at frequencies where digital circuitry would be cost and power prohibitive. Many problems must be solved before the new design methodology can be shown to be useful in practice: Continuous-time signal processing is not well understood. Analog computational circuits known as "soft-gates" have been previously proposed, but a complementary set of analog memory circuits is still lacking. Analog circuits are usually tunable, rarely reconfigurable, but never programmable. The thesis develops an understanding of the convergence and synchronization of statistical signal processing algorithms in continuous time, and explores the use of linear and nonlinear circuits for analog memory. An exemplary embodiment called the Noise Lock Loop (NLL) using these design primitives is demonstrated to perform direct-sequence spread-spectrum acquisition and tracking functionality and promises order-of-magnitude wins over digital implementations. A building block for the construction of programmable analog gate arrays, the "soft-multiplexer" is also proposed.
by Benjamin Vigoda.
Ph.D.

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4

Shana'a, Osama K. "Circuit Implementation of a High-speed Continuous-time Current-mode Field Programmable Analog Array (FPAA)". PDXScholar, 1996. https://pdxscholar.library.pdx.edu/open_access_etds/5103.

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The growing interest in programmable analog circuits has led to the development of Field Programmable Analog Arrays (FPAAs). An FPAA consists of: 1) a programmable cell that can be reconfigured to perform several analog functions. 2) an architecture that interconnects a number of copies of the programmable cell. In this thesis, the full monolithic circuit implementation of the analog part of the programmable cell is presented. Chapter I gives an introduction to the idea of FPAA and introduces the FPAA architecture and the cell block diagram. Chapter II deals with the design and verification of a differential current-mode four-quadrant multiplier. The weighting-summing circuit with the normalizing stage is discussed in Chapter III. Chapter IV presents the design of a current-mode low-voltage programmable integratorgain circuit. Programmability was achieved by changing the bias current in the designed circuits; no analog switches were used in the signal path. This shows no effect on the performance of the circuits. The presented programming method, however, relies on the availability of a programmable current source with a storage capability. The design of this current source is discussed in chapter V. Conclusions are summarized in Chapter VI. The presented designs throughout the whole thesis were supported by detailed analytical derivations with the necessary SPICE simulations to verify the performance.

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Lewinski, Komincz Artur Juliusz. "High frequency and high dynamic range continuous time filters". Texas A&M University, 2003. http://hdl.handle.net/1969.1/5933.

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Many modern communication systems use orthogonal frequency division multiplexing (OFDM) and discrete multi-tone (DMT) as modulation schemes where high data rates are transmitted over a wide frequency band in multiple orthogonal subcarriers. Due to the many advantages, such as flexibility, good noise immunity and the ability to be optimized for medium conditions, the use of DMT and OFDM can be found in digital video broadcasting, local area wireless network (IEEE 802.11a), asymmetric digital subscriber line (ADSL), very high bit rate DSL (VDSL) and power line communications (PLC). However, a major challenge is the design of the analog frontend; for these systems a large dynamic range is required due to the significant peak to average ratio of the resulting signals. In receivers, very demanding high-performance analog filters are typically used to block interferers and provide anti-aliasing before the subsequent analog to digital conversion stage. For frequencies higher than 10MHz, Gm-C filter implementations are generally preferred due to the more efficient operation of wide-band operational transconductance amplifiers (OTA). Nevertheless, the inherent low-linearity of open-loop operated OTA limits the dynamic range. In this dissertation, three different proposed OTA linearity enhancement techniques for the design of high frequency and high dynamic range are presented. The techniques are applied to two filter implementations: a 20MHz second order tunable filter and a 30MHz fifth order elliptical low-pass filter. Simulation and experimental results show a spurious free dynamic range (SFDR) of 65dB with a power consumption of 85mW. In a figure of merit where SFDR is normalized to the power consumption, this filter is 6dB above the trend-line of recently reported continuous time filters.

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6

Dahir, Hadi Mohammed. "An investigation of continuous-time electronic filters for semiconductor integration". Thesis, University of Bradford, 1990. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.281119.

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Fabre, Nicolas. "Quantum information in time-frequency continuous variables". Thesis, Université de Paris (2019-....), 2020. http://www.theses.fr/2020UNIP7044.

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Cette thèse aborde l’encodage de degrés de liberté continus temps-fréquence de photon uniques. Les similitudes mathématiques avec les quadratures du champ électromagnétique amène à généraliser des protocoles exprimées dans ces variables dans notre encodage. On introduit un nouveau type de qubit robuste contre des erreurs du type déplacement dans l’espace des phases temps-fréquence. Un nouvel espace des phases doublement cylindriques est étudié et est une représentation particulièrement adaptée pour des états ayant une symétrie de translation. On étudie également comment construire une distribution de phase fonctionnelle permettant de décrire un état quantique possédant des degrés de libertés continus spectraux et en quadrature
This thesis tackles the time-frequency continuous variables degree of freedom encoding of single photons and examine the formal mathematical analogy with the quadrature continuous variables of the electromagnetic field. We define a new type of qubit which is robust against time-frequency displacement errors. We define a new double-cylinder phase space which is particularly adapted for states which have a translational symmetry. We also study how to build a functional phase space distribution which allows to describe a quantum state with spectral and quadrature continuous variables degrees of freedom

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Sumesaglam, Taner. "Automatic tuning of continuous-time filters". Diss., Texas A&M University, 2004. http://hdl.handle.net/1969.1/1055.

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Integrated high-Q continuous-time filters require adaptive tuning circuits that will correct the filter parameters such as center frequency and quality factor (Q). Three different automatic tuning techniques are introduced. In all of the proposed methods, frequencyand quality factor tuning loops are controlled digitally, providing stable tuning by activating only one loop at a given time. In addition, a direct relationship between passband gain and quality factor is not required, so the techniques can be applied to active LC filters as well as Gm-C filters. The digital-tuning method based on phase comparison was veriﬁed with 1% tuning accuracy at 5.5 MHz for Q of 20. It uses phase information for both Q and center-frequency tuning. The ﬁlter output phase is tuned to the known references, which are generated by a frequency synthesizer. The core tuning circuit consists of D ﬂip-ﬂops (DFF) and simple logic gates. DFFs are utilized to perform binary phase comparisons. The second method, high-order digital tuning based on phase comparison, is an extension of the previous technique to high-order analog filters without depending on the master-slave approach. Direct tuning of the overall filter response is achieved without separating individual biquad sections, eliminating switches and their parasitics. The tuning system was veriﬁed with a prototype 6th order bandpass ﬁlter at 19 MHz with 0.6 MHz bandwidth, which was fabricated in a conventional 0.5 [mu]m CMOS technology. Analysis of different practical limitations is also provided. Finally, the digital-tuning method based on magnitude comparison is proposed for second-order filters for higher frequency operations. It incorporates a frequency synthesizer to generate reference signals, an envelope detector and a switched comparator to compare output magnitudes at three reference frequencies. The theoretical analysis of the technique and the simulation results are provided.

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Tugui, Catalin Adrian. "Design Methodology for High-performance Circuits Based on Automatic Optimization Methods". Thesis, Supélec, 2013. http://www.theses.fr/2013SUPL0002/document.

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Ce travail de thèse porte sur le développement d’une méthodologie efficace pour la conception analogique, des algorithmes et des outils correspondants qui peuvent être utilisés dans la conception dynamique de fonctions linéaires à temps continu. L’objectif principal est d’assurer que les performances pour un système complet peuvent être rapidement investiguées, mais avec une précision comparable aux évaluations au niveau transistor.Une première direction de recherche a impliqué le développement de la méthodologie de conception basée sur le processus d'optimisation automatique de cellules au niveau transistor et la synthèse de macro-modèles analogiques de haut niveau dans certains environnements comme Mathworks - Simulink, VHDL-AMS ou Verilog-A. Le processus d'extraction des macro-modèles se base sur un ensemble complet d'analyses (DC, AC, transitoire, paramétrique, Balance Harmonique) qui sont effectuées sur les schémas analogiques conçues à partir d’une technologie spécifique. Ensuite, l'extraction et le calcul d'une multitude de facteurs de mérite assure que les modèles comprennent les caractéristiques de bas niveau et peuvent être directement régénéré au cours de l'optimisation.L'algorithme d'optimisation utilise une méthode bayésienne, où l'espace d’évaluation est créé à partir d'un modèle de substitution (krigeage dans ce cas), et la sélection est effectuée en utilisant le critère d’amélioration (Expected Improvement - EI) sujet à des contraintes. Un outil de conception a été développé (SIMECT), qui a été intégré comme une boîte à outils Matlab, employant les algorithmes d’extraction des macro-modèles et d'optimisation automatique
The aim of this thesis is to establish an efficient analog design methodology, the algorithms and the corresponding design tools which can be employed in the dynamic conception of linear continuous-time (CT) functions. The purpose is to assure that the performance figures for a complete system can be rapidly investigated, but with comparable accuracy to the transistor-level evaluations. A first research direction implied the development of the novel design methodology based on the automatic optimization process of transistor-level cells using a modified Bayesian Kriging approach and the synthesis of robust high-level analog behavioral models in environments like Mathworks – Simulink, VHDL-AMS or Verilog-A.The macro-model extraction process involves a complete set of analyses (DC, AC, transient, parametric, Harmonic Balance) which are performed on the analog schematics implemented on a specific technology process. Then, the extraction and calculus of a multitude of figures of merit assures that the models include the low-level characteristics and can be directly regenerated during the optimization process.The optimization algorithm uses a Bayesian method, where the evaluation space is created by the means of a Kriging surrogate model, and the selection is effectuated by using the expected improvement (EI) criterion subject to constraints.A conception tool was developed (SIMECT), which was integrated as a Matlab toolbox, including all the macro-models extraction and automatic optimization techniques

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Jiang, Yang. "Clock-jitter insensitive circuit techniques in continuous-time sigma-delta modulators". Thesis, University of Macau, 2012. http://umaclib3.umac.mo/record=b2590641.

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Più fonti

Libri sul tema "CONTINOUS TIME CIRCUITS"

1

M, Schmitt Neil, a cura di. Circuit analysis for engineers: Continuous and discrete time systems. New York: J. Wiley, 1985.

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2

Silva-Martinez, José. High-performance CMOS continuous-time filters. Boston: Kluwer Academic Publishers, 1993.

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3

Unbehauen, Rolf, e Andrzej Cichocki. MOS Switched-Capacitor and Continuous-Time Integrated Circuits and Systems. Berlin, Heidelberg: Springer Berlin Heidelberg, 1989. http://dx.doi.org/10.1007/978-3-642-83677-0.

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4

Mix, Dwight F. Circuit analysis for engineers: Continuous and discrete time systems. New York: Wiley, 1985.

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5

Andrzej, Cichocki, a cura di. MOS switched-capacitor and continuous-time integrated circuits and systems: Analysis and design. Berlin: Springer-Verlag, 1989.

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6

Unbehauen, Rolf. MOS Switched-Capacitor and Continuous-Time Integrated Circuits and Systems: Analysis and Design. Berlin, Heidelberg: Springer Berlin Heidelberg, 1989.

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7

Willingham, Scott D. Integrated video-frequency continuous-time filters: High-performance realizations in BiCMOS. Boston: Kluwer Academic Publishers, 1995.

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Saari, Ville. Continuous-Time Low-Pass Filters for Integrated Wideband Radio Receivers. Boston, MA: Springer US, 2012.

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9

Tsinghua University Tsinghua University Press e Weigang Zhang. In Continuous Time. de Gruyter GmbH, Walter, 2017.

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Tsinghua University Tsinghua University Press e Weigang Zhang. In Continuous Time. de Gruyter GmbH, Walter, 2017.

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Capitoli di libri sul tema "CONTINOUS TIME CIRCUITS"

1

Song, Bang-Sup. "Continuous-Time Analog Circuits". In System-level Techniques for Analog Performance Enhancement, 35–67. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-27921-3_2.

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2

Willingham, Scott D., e Ken Martin. "Distortion in Quasilinear Circuits". In Integrated Video-Frequency Continuous-Time Filters, 91–139. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2347-5_4.

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3

Bajdechi, Ovidiu, e Johan H. Huijsing. "Continuous-Time Circuit Design". In Systematic Design of Sigma-Delta Analog-to-Digital Converters, 75–96. Boston, MA: Springer US, 2004. http://dx.doi.org/10.1007/978-1-4020-7946-7_4.

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4

Gimeno Gasca, Cecilia, Santiago Celma Pueyo e Concepción Aldea Chagoyen. "Continuous-Time Linear Equalizers". In Analog Circuits and Signal Processing, 53–80. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-10563-5_3.

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5

Allstot, David J., e Rajesh H. Zele. "Current-Mode Continuous-Time Filters". In Analog Circuit Design, 227–35. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-1-4757-2353-3_12.

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Vancorenland, Peter, Philippe Coppejans e Michiel Steyaert. "Continuous-time Quadrature Modulator Receivers". In Analog Circuit Design, 387–410. Boston, MA: Springer US, 2002. http://dx.doi.org/10.1007/0-306-47951-6_17.

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Castello, R. "Low-Voltage Continuous-Time Filters". In Analog Circuit Design, 387–408. Boston, MA: Springer US, 2001. http://dx.doi.org/10.1007/978-1-4613-1443-1_18.

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Bolatkale, Muhammed, Lucien J. Breems e Kofi A. A. Makinwa. "Continuous-Time Delta-Sigma Modulator". In Analog Circuits and Signal Processing, 9–35. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-05840-5_2.

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9

Tsividis, Yannis. "Developments in Integrated Continuous Time Filters". In Analog Circuit Design, 129–47. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-1-4757-2353-3_7.

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Gimeno Gasca, Cecilia, Santiago Celma Pueyo e Concepción Aldea Chagoyen. "Theoretical Study of Continuous-Time Equalizers". In Analog Circuits and Signal Processing, 31–51. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-10563-5_2.

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Atti di convegni sul tema "CONTINOUS TIME CIRCUITS"

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Ke, Yi, Jan Craninckx e Georges Gielen. "Design strategy for Continous-Time Delta-Sigma based on power consideration for 4G radios". In 2007 International Symposium on Signals, Circuits and Systems. IEEE, 2007. http://dx.doi.org/10.1109/isscs.2007.4292642.

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2

Edler, Julius, Marcel Runge e Friedel Gerfers. "A Dynamic Body-Bias Linearization Technique Enabling Wide-Band GmC based Continous-Time Sigma-Delta Converters in 22 nm FD-SOI CMOS". In 2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2021. http://dx.doi.org/10.1109/mwscas47672.2021.9531807.

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3

Zhou, Liang, e Shantanu Chakrabartty. "A continuous-time varactor-based temperature compensation circuit for floating-gate multipliers and inner-product circuits". In 2015 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2015. http://dx.doi.org/10.1109/iscas.2015.7169196.

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4

Spencer e Sturm. "A continuous-time analog moment calculating circuit". In 1993 Symposium on VLSI Circuits. IEEE, 1988. http://dx.doi.org/10.1109/vlsic.1988.1037448.

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5

Jun-Gi Jo, Jinho Noh e Changsik Yoo. "A 20MHz bandwidth continuous-time". In 2010 IEEE Asian Solid-State Circuits Conference (A-SSCC). IEEE, 2010. http://dx.doi.org/10.1109/asscc.2010.5716627.

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6

Zare-Hoseini, H., I. Kale e C. S. Morling Richard. "A low-power continuous-time". In 2010 IEEE Asian Solid-State Circuits Conference (A-SSCC). IEEE, 2010. http://dx.doi.org/10.1109/asscc.2010.5716630.

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Sotiriadis, Paul P., e Robert Adams. "Continuous-time signal processing with time-variant delay". In 2009 IEEE International Symposium on Circuits and Systems - ISCAS 2009. IEEE, 2009. http://dx.doi.org/10.1109/iscas.2009.5117784.

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8

Gubbins, David, Bumha Lee, Pavan Kumar Hanumolu e Un-Ku Moon. "A continuous-time input pipeline ADC". In 2008 IEEE Custom Integrated Circuits Conference - CICC 2008. IEEE, 2008. http://dx.doi.org/10.1109/cicc.2008.4672050.

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Kaiser, A. "A Micropower CMOS Continuous-Time Lowpass Filter". In Fourteenth European Solid-State Circuits Conference. IEEE, 1988. http://dx.doi.org/10.1109/esscirc.1988.5468390.

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Carrillo, Juan M., Josh L. Ausin e J. Francisco Duque-Carrillo. "CMOS continuous-time CMFB circuit with improved linearity". In 2007 European Conference on Circuit Theory and Design (ECCTD 2007). IEEE, 2007. http://dx.doi.org/10.1109/ecctd.2007.4529531.

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Rapporti di organizzazioni sul tema "CONTINOUS TIME CIRCUITS"

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Wu, Pan. The Design of High-Frequency Continuous-Time Integrated Analog Signal Processing Circuits. Portland State University Library, gennaio 2000. http://dx.doi.org/10.15760/etd.1161.

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Casinovi, Giorgio. Development of Cad Tools for Power Estimation in Continuous-Time and Switched-Capacitor Analog Circuits. Fort Belvoir, VA: Defense Technical Information Center, settembre 1998. http://dx.doi.org/10.21236/ada373430.

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Casinovi, Giorgio. Development of CAD Tools for Power Estimation in Continuous-Time and Switched-Capacitor Analog Circuits. Fort Belvoir, VA: Defense Technical Information Center, settembre 1998. http://dx.doi.org/10.21236/ada375770.

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4

Shana'a, Osama. Circuit Implementation of a High-speed Continuous-time Current-mode Field Programmable Analog Array (FPAA). Portland State University Library, gennaio 2000. http://dx.doi.org/10.15760/etd.6979.

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Payment Systems Report - June of 2020. Banco de la República de Colombia, febbraio 2021. http://dx.doi.org/10.32468/rept-sist-pag.eng.2020.

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Abstract (sommario):

With its annual Payment Systems Report, Banco de la República offers a complete overview of the infrastructure of Colombia’s financial market. Each edition of the report has four objectives: 1) to publicize a consolidated account of how the figures for payment infrastructures have evolved with respect to both financial assets and goods and services; 2) to summarize the issues that are being debated internationally and are of interest to the industry that provides payment clearing and settlement services; 3) to offer the public an explanation of the ideas and concepts behind retail-value payment processes and the trends in retail payments within the circuit of individuals and companies; and 4) to familiarize the public, the industry, and all other financial authorities with the methodological progress that has been achieved through applied research to analyze the stability of payment systems. This edition introduces changes that have been made in the structure of the report, which are intended to make it easier and more enjoyable to read. The initial sections in this edition, which is the eleventh, contain an analysis of the statistics on the evolution and performance of financial market infrastructures. These are understood as multilateral systems wherein the participating entities clear, settle and register payments, securities, derivatives and other financial assets. The large-value payment system (CUD) saw less momentum in 2019 than it did the year before, mainly because of a decline in the amount of secondary market operations for government bonds, both in cash and sell/buy-backs, which was offset by an increase in operations with collective investment funds (CIFs) and Banco de la República’s operations to increase the money supply (repos). Consequently, the Central Securities Depository (DCV) registered less activity, due to fewer negotiations on the secondary market for public debt. This trend was also observed in the private debt market, as evidenced by the decline in the average amounts cleared and settled through the Central Securities Depository of Colombia (Deceval) and in the value of operations with financial derivatives cleared and settled through the Central Counterparty of Colombia (CRCC). Section three offers a comprehensive look at the market for retail-value payments; that is, transactions made by individuals and companies. During 2019, electronic transfers increased, and payments made with debit and credit cards continued to trend upward. In contrast, payments by check continued to decline, although the average daily value was almost four times the value of debit and credit card purchases. The same section contains the results of the fourth survey on how the use of retail-value payment instruments (for usual payments) is perceived. Conducted at the end of 2019, the main purpose of the survey was to identify the availability of these payment instruments, the public’s preferences for them, and their acceptance by merchants. It is worth noting that cash continues to be the instrument most used by the population for usual monthly payments (88.1% with respect to the number of payments and 87.4% in value). However, its use in terms of value has declined, having registered 89.6% in the 2017 survey. In turn, the level of acceptance by merchants of payment instruments other than cash is 14.1% for debit cards, 13.4% for credit cards, 8.2% for electronic transfers of funds and 1.8% for checks. The main reason for the use of cash is the absence of point-of-sale terminals at commercial establishments. Considering that the retail-payment market worldwide is influenced by constant innovation in payment services, by the modernization of clearing and settlement systems, and by the efforts of regulators to redefine the payment industry for the future, these trends are addressed in the fourth section of the report. There is an account of how innovations in technology-based financial payment services have developed, and it shows that while this topic is not new, it has evolved, particularly in terms of origin and vocation. One of the boxes that accompanies the fourth section deals with certain payment aspects of open banking and international experience in that regard, which has given the customers of a financial entity sovereignty over their data, allowing them, under transparent and secure conditions, to authorize a third party, other than their financial entity, to request information on their accounts with financial entities, thus enabling the third party to offer various financial services or initiate payments. Innovation also has sparked interest among international organizations, central banks, and research groups concerning the creation of digital currencies. Accordingly, the last box deals with the recent international debate on issuance of central bank digital currencies. In terms of the methodological progress that has been made, it is important to underscore the work that has been done on the role of central counterparties (CCPs) in mitigating liquidity and counterparty risk. The fifth section of the report offers an explanation of a document in which the work of CCPs in financial markets is analyzed and corroborated through an exercise that was built around the Central Counterparty of Colombia (CRCC) in the Colombian market for non-delivery peso-dollar forward exchange transactions, using the methodology of network topology. The results provide empirical support for the different theoretical models developed to study the effect of CCPs on financial markets. Finally, the results of research using artificial intelligence with information from the large-value payment system are presented. Based on the payments made among financial institutions in the large-value payment system, a methodology is used to compare different payment networks, as well as to determine which ones can be considered abnormal. The methodology shows signs that indicate when a network moves away from its historical trend, so it can be studied and monitored. A methodology similar to the one applied to classify images is used to make this comparison, the idea being to extract the main characteristics of the networks and use them as a parameter for comparison. Juan José Echavarría Governor

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