Letteratura scientifica selezionata sul tema "CONVENTIONAL CLOCK GATING"

PurposeThe purpose of this paper is to design a low power clock gating technique using Galeor approach by assimilated with replica path pulse triggered flip flop (RP-PTFF).Design/methodology/approachIn the present scenario, the inclination of battery for portable devices has been increasing tremendously. Therefore, battery life has become an essential element for portable devices. To increase the battery life of portable devices such as communication devices, these have to be made with low power requirements. Hence, power consumption is one of the main issues in CMOS design. To reap a low-power battery with optimum delay constraints, a new methodology is proposed by using the advantages of a low leakage GALEOR approach. By integrating the proposed GALEOR technique with conventional PTFFs, a reduction in power consumption is achieved.FindingsThe design was implemented in mentor graphics EDA tools with 130 nm technology, and the proposed technique is compared with existing conventional PTFFs in terms of power consumption. The average power consumed by the proposed technique (RP-PTFF clock gating with the GALEOR technique) is reduced to 47 per cent compared to conventional PTFF for 100 per cent switching activity.Originality/valueThe study demonstrates that RP-PTFF with clock gating using the GALEOR approach is a design that is superior to the conventional PTFFs.

In this paper, a new low power design method of the FIR filter for image processing is proposed. Because the correlation between adjacent pixels is very high in image data, the clock gating technique can be a good candidate for low power strategy. However, the conventional clock gating strategy that is applied independently to every flip-flop of the filter give rise to too much additional area overhead and couldn't get a good result in the power reduction. In our method, each tap register, which is used to delay the input data in the filter, is partitioned into two sub-registers according to the correlation characteristic of its input space. For the sub-register which highly correlated data is inputted into, the dynamic power consumption is reduced by diminishing switching activity of the clock signal. We can also reduce the additional hardware overhead by propagating the clock gating control signal of the first tap register to other tap registers. To identify the efficiency of the proposed design method, we perform the experiments on some filters that are designed in VHDL. The power estimation tool says that the proposed method can reduce the power dissipation of the filter by more than 18% compared to the conventional filter design methods.

The present methodology of clock distribution inside high-performance central processing unit chip offers current to ramp linearly or exponentially when the chip comes out of sleep mode to active mode or when the clock starts driving a chip to operate. This linear current ramp leads to power and ground noise due to [Formula: see text]d[Formula: see text]/d[Formula: see text]. In this paper, we have shown that for a given power delivery network (PDN), it is possible to generate a current profile (current versus time), by controlling the current on all the complementary metal oxide semiconductor gates of the clock generation circuits. In our methodology, the time for the chip to reach the maximum saturation current is same when compared with the present linear current ramp methodology. We have also developed a new “optimizer program” to show the existence of a unique single current profile solution, which is different from the present methodology. The proposed method requires understanding of how the minimum value of the power supply voltage (supposed to be always 1[Formula: see text]V for the device) gets changed, when various gates in a clock tree are turned ON at different times ([Formula: see text], parameters of the problem) with different values of current ([Formula: see text], other parameters of the problem). Basically, an ensemble of “[Formula: see text]” number of transistors will be turned ON at time [Formula: see text] while it will pump the total current [Formula: see text]. This understanding generates the derivative function of the minimum noise point with respect to these said parameters, which in turn generates a new set of parameters to optimize the noise point. We have found that this optimizer program works and also converges for the generation of minimum power and ground noise, which is 40% lesser than the conventional approach.

Optimization for power is one of the most important design objectives in modern digital signal processing (DSP) applications. The digital finite duration impulse response (FIR) filter is considered to be one of the most essential components of DSP, and consequently a number of extensive works had been carried out by researchers on the power optimization of the filters. Data-driven clock gating (DDCG) and multibit flip-flops (MBFFs) are two low-power design methods that are used and often treated separately. The combination of these methods into a single algorithm enables further power saving of the FIR filter. The experimental results show that the proposed FIR filter achieves 25% and 22% power consumption reduction compared to that using the conventional design.

To adapt to varied working situations, the latest biomedical imaging applications require low energy consumption, high performance, and extensive energy-performance scalability. State-of-the-art electronics with higher sensitivity, higher counting rate, and finer time resolution are required to create higher precision, higher temporal resolution, and maximum contrast biomedical images. In recent days, the system’s power consumption is important critically in modern VLSI circuits particularly for the low power application. In order to decrease the power, a power optimization technique must be used at various design levels. The low power use of logic cells is a proficient technique for decreasing the circuit level power. Dual Feedback edge triggered Flip Flop (DFETFF) is considered for biomedical imaging applications in the proposed system. Initially, the high dynamic range voltage is given as input signal. The comparator output is then retried at the comparator end. The integration capacitor is employed for storing remaining voltage signal. The comparator voltage is then given to the capacitor reset block. In the proposed work, a capacitor-reset block that employs clock signal takes up a dual-feedbackedge-triggered Flip-flop as an alternative of a conventional type for reducing the final output signals errors. Dual feedback loops assure that feedback loops do not tri-state at the time of SET restoration, a scheme that could lead to SEUs in latches if a single delay component and a single feedback loop are used. In digital system, Clock gating is a competent method of lessening the overall consumption of power along with deactivating the clock signal selectively and is useful for controlling the usage of clock signal asynchronously in reference to input-signal current. The integration-control (Vint) signal is employed in controlling the integration time. On the termination of integration, the signal level phase is kept, also similar one is send to arrangement all through read period. As a result, the simulation was carried out after the design layout and the estimations of performance were made and are compared with traditional approaches to prove the proposed mechanism effectiveness for future biomedical applications.

The main aim of this approach is to improve the design model of filters for optimal circuit design. The objective of this proposed method is to improve the performance of VLSI circuit like area, power, and delay. In recent days, the filters are most applicable designs in DSP, medical diagnosis and arithmetic computations. In Digital Signal Processing and communication applications, the FIR filter plays an important role. The Finite Impulse Response is designed with number of adders, multipliers, subtraction units, transfer functions and delay elements. The VLSI circuits are applied in various applications, but the number adders and multipliers occupy the design space since it increases the area and delay factors. The main aim is to reduce the number of adders and multiplier by various computational algorithms. The existing research work uses carry save accumulator with ripple carry adder and binary multiplier. In proposed method, the enhanced Vedic multiplication logic and improved carry lookahead adder logic improves the result. In Vedic multiplication algorithm, the number of adder logic is minimized by adding speculative Brent-kung adder logic in it. The fastest adder in VLSI circuit is CLA (Carry look ahead adder logic), which is improved by utilizing the result of reduced power consumption and delay. In this proposed research work, the power optimization is done by using enhanced clock gating technique. Here, area, power, and delay factors are measured and it is compared with conventional FIR filter design. The proposed method improves the result in the way of area, power, and delay. The whole FIR filter structure is designed and power optimized by connecting with an enhanced clock gating technique. This proposed design and simulate by using Xilinx ISE 14.5 and it is synthesize by ModelSim.

Hybrid field programmable gate array (FPGA) implementation is proposed to improve the performance of visible image watermarking systems. The visible watermarking process is implemented as pixel by pixel operation under a spatial domain or vector operation in the frequency domain. The proposed approach is mainly designed for watermarking the images taken from digital cameras of various sizes. The padding technique is used for unequal sizes of the watermark image and original host image. The architecture data path consists of eight and six stages of pipeline capable of watermarking on the pixel-based operation and vector-based operation, respectively. The dual image watermarking architecture data path consists of a 13-stage pipeline. Pipeline and parallelism mechanisms are used to improve throughput. To improve the performance in discrete cosine transform operations at the frequency domain, the shift-add technique replaces the conventional multipliers. The clock gating technique is employed to reduce the power by preventing unnecessary switching in a path. Hardware implementation of the algorithm is tested in Intel Cyclone FPGA with the device of EP4CGX22CF19C6, with which the throughput achieved is 1.27[Formula: see text]Gbits/s with a total area utilization of 35[Formula: see text]digital signal processing (DSP) blocks, 378 look-up tables (LUTs) and 486 registers.

Power consumption, performance, and area utilization are critical considerations in VLSI design. This paper presents an analytical approach to optimize these metrics using a proposed clock gating technique. The objective is to achieve power-efficient and high-performance VLSI designs while minimizing the area overhead. The proposed clock gating technique utilizes a sophisticated control logic that selectively enables clock signals to the circuit components based on their activity. By dynamically controlling the clock distribution, unnecessary switching and power dissipation are reduced, resulting in significant power savings. The technique is analyzed and compared with conventional clock gating approaches in terms of power reduction and performance enhancement. Experimental results demonstrate the effectiveness of the proposed clock gating technique in reducing power consumption while maintaining the desired performance levels. The analysis reveals that the proposed technique outperforms conventional methods in terms of power savings, with minimal impact on performance. However, it is noted that the proposed clock gating technique may introduce a slight increase in area overhead due to the additional control logic.