Bibliografie tematiche / Cu dual damascene processes

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Letteratura scientifica selezionata sul tema "Cu dual damascene processes"

Autore: Grafiati

Pubblicato: 4 giugno 2021

Ultima modifica: 19 febbraio 2022

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Articoli di riviste sul tema "Cu dual damascene processes"

Tang, Jian She, Brian J. Brown, Steven Verhaverbeke, Han Wen Chen, Jim Papanu, Raymond Hung, Cathy Cai e Dennis Yost. "Aqueous Based Single Wafer Cu/Low-k Cleaning Process Characterization and Integration into Dual Damascene Process Flow". Solid State Phenomena 103-104 (aprile 2005): 353–56. http://dx.doi.org/10.4028/www.scientific.net/ssp.103-104.353.

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As device features scale down to 90nm and Cu/low-k films are employed for back end interconnects, post etch and ash residue cleaning becomes increasingly challenging due to the higher aspect ratio of the features, tighter CD control requirements, sensitivity of the low-k films, and the requirement for high wet etch selectivity between CuxO and Cu. Traditional solvent based cleaning in wet benches has additional issues such as wafer cross-contamination and high disposal cost [1, 2]. We have developed a novel aqueous solution (AQ) based single wafer cleaning process to address these challenges. The results of physical characterization, process integration electrical data, and process integration reliability data such as electromigration (EM) and stress migration data are presented. The main conclusions can be summarized as follows: (1) The single wafer cleaning process developed on the Oasis™ system can clean post etch residues and simultaneously clean the wafer front side and backside metallic contaminants; (2) In terms CuxO and Cu wet etch selectivity, CD loss control, the Oasis™ aqueous single wafer clean process is superior to the bench solvent cleaning process; (3)The Oasis aqueous cleaning process shows no undercut below etchstop due to the very low Cu etch amount in one cleaning pass, therefore the electromigration and stress migration performance of the aqueous Oasis processed wafers is clearly better than that of the solvent bench processed wafers.

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Jung, Chung Kyung, Sung Wook Joo, Sang Wook Ryu, S. Naghshineeh, Yang Lee e Jae Won Han. "Improved Cleaning Process for Etch Residue Removal in an Advanced Copper/Low-k Device without the Use of DMAC (Dimethylacetamide)". Solid State Phenomena 187 (aprile 2012): 245–48. http://dx.doi.org/10.4028/www.scientific.net/ssp.187.245.

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Plasma dry etching processes are commonly used to fabricate sidewalls of trenches and vias for copper / low-k dual damascene devices. Typically, some polymers remain in the trench and at the via top and sidewall. Other particulate etch residues are may remained in the bottom and on the sidewalls of vias. Generally, the particulate consists of mixtures of copper oxide with polymers. The polymers on the sidewalls and the particulate residues at the bottom of vias must be removed prior to the next process step. Small amounts of polymer are intentionally left on the sidewalls of trenches and vias during the etching in order to achieve a vertical profile and to protect the low-k materials under the etching mask. Until now, the industry has relied mainly on organic solvent containing mixtures to clean etch / ash residues from such devices. The effectiveness of available residue removers varies with the specific process and also depends on which new integration materials are used. New materials typically include Cu, TaN, low-k dielectrics and others [1-. Solvent content is thought to aid the removal of polymer residues and particulates produced during plasma dry etching processes. Therefore, in the past we have used a residue remover which contains DMAC (dimethylacetamide). But the use of DMAC is banned in microelectronic fabrication facilities in Europe because of its toxicity. Thus we wanted to find and evaluate a DMAC-free residue remover for removing polymer residues while maintaining high selectivity to the copper and ILD films.

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Perng, Dung-Ching, Jia-Feng Fang e Jhin-Wei Chen. "Single mask dual damascene processes". Microelectronic Engineering 85, n. 3 (marzo 2008): 599–602. http://dx.doi.org/10.1016/j.mee.2007.11.003.

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Ogawa, E. T., Ki-Don Lee, V. A. Blaschke e P. S. Ho. "Electromigration reliability issues in dual-damascene Cu interconnections". IEEE Transactions on Reliability 51, n. 4 (dicembre 2002): 403–19. http://dx.doi.org/10.1109/tr.2002.804737.

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Heo, Jung Shik, Jun Hwan Oh, Hong Jae Shin e Nae In Lee. "Cu Dendrite Formation in Post Trench Etch Cleaning". Solid State Phenomena 145-146 (gennaio 2009): 331–33. http://dx.doi.org/10.4028/www.scientific.net/ssp.145-146.331.

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Copper has been widely used as the interconnect material for integrated circuits because of the good electrical conductivity and electron migration resistance. Copper dual damascene structure has been adapted due to the impossibility of etching the copper. For via first dual damascene (VFDD) integration, via is opened after trench etch. Generally, diluted HF cleaning after trench etch is used to remove both etch residues and carbon depletion layer of low-k material. In this study, we investigated the characteristics of copper dendritic formation occurred in post trench etch cleaning with single wafer spin tool (SWST).

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Pyun, Jung Woo, Won-Chong Baek, Lijuan Zhang, Jay Im, Paul S. Ho, Larry Smith e Gregory Smith. "Electromigration behavior of 60 nm dual damascene Cu interconnects". Journal of Applied Physics 102, n. 9 (novembre 2007): 093516. http://dx.doi.org/10.1063/1.2805425.

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Hu, C. K., L. Gignac, E. Liniger e R. Rosenberg. "Electromigration in On-Chip Single/Dual Damascene Cu Interconnections". Journal of The Electrochemical Society 149, n. 7 (2002): G408. http://dx.doi.org/10.1149/1.1482057.

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Kriz, J., C. Angelkort, M. Czekalla, S. Huth, D. Meinhold, A. Pohl, S. Schulte, A. Thamm e S. Wallace. "Overview of dual damascene integration schemes in Cu BEOL integration". Microelectronic Engineering 85, n. 10 (ottobre 2008): 2128–32. http://dx.doi.org/10.1016/j.mee.2008.05.034.

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Oates, A. S., e S. C. Lee. "Electromigration failure distributions of dual damascene Cu /low – k interconnects". Microelectronics Reliability 46, n. 9-11 (settembre 2006): 1581–86. http://dx.doi.org/10.1016/j.microrel.2006.07.038.

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Wu, ZhenYu, YinTang Yang, ChangChun Chai, YueJin Li, JiaYou Wang, Jing Liu e Bin Liu. "Temperature-dependent stress-induced voiding in dual-damascene Cu interconnects". Microelectronics Reliability 48, n. 4 (aprile 2008): 578–83. http://dx.doi.org/10.1016/j.microrel.2007.12.001.

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Più fonti

Tesi sul tema "Cu dual damascene processes"

Park, Seongho. "Materials, Processes, and Characterization of Extended Air-gaps for the Intra-level Interconnection of Integrated Circuits". Diss., Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/22598.

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Materials, Processes, and Characterization of Extended Air-gaps for the Intra-level Interconnection of Integrated Circuits Seongho Park 157 pages Directed by Dr. Paul A. Kohl and Dr. Sue Ann Bidstrup Allen The integration of an air-gap as an ultra low dielectric constant material in an intra-metal dielectric region of interconnect structure in integrated circuits was investigated in terms of material properties of a thermally decomposable sacrificial polymer, fabrication processes and electrical performance. Extension of the air-gap into the inter-layer dielectric region reduces the interconnect capacitance. In order to enhance the hardness of a polymer for the better process reliabilities, a conventional norbornene-based sacrificial polymer was electron-beam irradiated. Although the hardness of the polymer increased, the thermal properties degraded. A new high modulus tetracyclododecene-based sacrificial polymer was characterized and compared to the norbornene-based polymer in terms of hardness, process reliability and thermal properties. The tetracyclododecene-based polymer was harder and showed better process reliability than the norbornene-based sacrificial polymer. Using the tetracyclododecene-based sacrificial polymer, a single layer Cu/air-gap and extended Cu/air-gap structures were fabricated. The effective dielectric constant of the air-gap and extended air-gap structures were 2.42 and 2.17, respectively. This meets the requirements for the 32 nm node. Moisture uptake of the extended Cu/air-gap structure increased the effective dielectric constant. The exposure of the structure to hexamethyldisilazane vapor removed the absorbed moisture and changed the structure hydrophobic, improving the integration reliability. The integration processes of the air-gap and the extended air-gap into a dual damascene Cu metallization process has been proposed compared to state-of-the-art integration approaches.

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Chang, Choon Wai, Z. S. Choi, Carl V. Thompson, C. L. Gan, Kin Leong Pey, Wee Kiong Choi e N. Hwang. "The Influence of Adjacent Segment on the Reliability of Cu Dual Damascene Interconnects". 2005. http://hdl.handle.net/1721.1/7533.

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Three terminal âdotted-I’ interconnect structures, with vias at both ends and an additional via in the middle, were tested under various test conditions. Mortalities (failures) were found in right segments with jL value as low as 1250 A/cm, and the mortality of a dotted-I segment is dependent on the direction and magnitude of the current in the adjacent segment. Some mortalities were also found in the right segments under a test condition where no failure was expected. Cu extrusion along the delaminated Cu/Si₃N₄ interface near the central via region was believed to cause the unexpected failures. From the time-to-failure (TTF), it is possible to quantify the Cu/Si₃N₄ interfacial strength and bonding energy. Hence, the demonstrated test methodology can be used to investigate the integrity of the Cu dual damascene processes. As conventionally determined critical jL values in two-terminal via-terminated lines cannot be directly applied to interconnects with branched segments, this also serves as a good methodology to identify the critical effective jL values for immortality.
Singapore-MIT Alliance (SMA)

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Chao, Huang-Lin. "Electromigration enhanced kinetics of Cu-Sn intermetallic compounds in Pb free solder joints and Cu low-k dual damascene processing using step and flash imprint lithography". 2009. http://hdl.handle.net/2152/7607.

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This dissertation constitutes two major sections. In the first major section, a kinetic analysis was established to investigate the electromigration (EM), enhanced intermetallic compound (IMC) growth and void formation for Sn-based Pb-free solder joints to Cu under bump metallization (UBM). The model takes into account the interfacial intermetallic reaction, Cu-Sn interdiffusion, and current stressing. A new approach was developed to derive atomic diffusivities and effective charge numbers based on Simulated Annealing (SA) in conjunction with the kinetic model. The finite difference (FD) kinetic model based on this approach accurately predicted the intermetallic compound growth when compared to empirical observation. The ultimate electromigration failure of the solder joints was caused by extensive void formation at the intermetallic interface. The void formation mechanism was analyzed by modeling the vacancy transport under electromigration. The effects of current density and Cu diffusivity in Sn solder were also investigated with the kinetic model. The second major section describes the integration of Step and Flash Imprint Lithography (S-FIL®) into an industry standard Cu/low-k dual damascene process. The yield on a Back End Of the Line (BEOL) test vehicle that contains standard test structures such as via chains with 120 nm vias was established by electrical tests. S-FIL shows promise as a cost effective solution to patterning sub 45 nm features and is capable of simultaneously patterning two levels of interconnect structures, which provides a low cost BEOL process. The critical processing step in the integration is the reactive ion etching (RIE) process that transfers the multilevel patterns to the inter-level dielectrics (ILD). An in-situ, multistep etch process was developed that gives excellent pattern structures in two industry standard Chemical Vapor Deposited (CVD) low-k dielectrics. The etch process showed excellent pattern fidelity and a wide process window. Electrical testing was conducted on the test vehicle to show that this process renders high yield and consistent via resistance. Discussions of the failure behaviors that are characteristic to the use of S-FIL are provided.
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Chang, Choon Wai, C. L. Gan, Carl V. Thompson, Kin Leong Pey, Wee Kiong Choi e N. Hwang. "Mortality Dependence of Cu Dual Damascene Interconnects on Adjacent Segments". 2003. http://hdl.handle.net/1721.1/3835.

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Electromigration experiments have been carried out on straight interconnects that have single vias at each end, and are divided into two segments by a via in the center ("dotted-I" structures). For dotted-i structures in the second metal layer (M2) and with 25µm-long segments length, failures occurred even when the product of the current density and segment length (jL) was as low as 1250A/cm, even though via terminated 25µm-long lines are "immortal" when (jL)cr < 1500 A/cm. Moreover, we found the mortalities of the dotted-I segments to be dependent on the current density and current direction in the adjacent segment. These result suggest that there is not a definite value of jL product that defines true immortality in individual segments that are part of an interconnect tree, and that the critical value of jL for Cu dual damascene segments is dependent on the magnitude and direction of current flow in adjacent segments. Therefore, (jL)cr values determined in two-terminal via-terminated lines cannot be directly applied to interconnects with branched segments, but rather the magnitude as well as the direction of the current flow in the adjoining segments must be taken into consideration in determining the immortality of interconnect segments.
Singapore-MIT Alliance (SMA)

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Wei, F., S. P. Hau-Riege, C. L. Gan, Carl V. Thompson, J. J. Clement, H. L. Tay, B. Yu, M. K. Radhakrishnan, Kin Leong Pey e Wee Kiong Choi. "Length Effects on the Reliability of Dual-Damascene Cu Interconnects". 2002. http://hdl.handle.net/1721.1/3977.

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The effects of interconnect length on the reliability of dual-damascene Cu metallization have been investigated. As in Al-based interconnects, the lifetimes of Cu lines increase with decreasing length. However, unlike Al-based interconnects, no critical length exists, below which all Cu lines are âimmortal’. Furthermore, we found multi-modal failure statistics for long lines, suggesting multiple failure mechanisms. Some long Cu interconnect segments have very large lifetimes, whereas in Al segments, lifetimes decrease continuously with increasing line length. It is postulated that the large lifetimes observed in long Cu lines result from liner rupture at the bottom of the vias, which allows continuous flow of Cu between the two bond pads. As a consequence, the average lifetimes of short lines and long lines can be higher than those of lines with intermediate lengths.
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Baek, Won-chong. "Reliability study on the via of dual damascene Cu interconnects". Thesis, 2006. http://hdl.handle.net/2152/2656.

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Gan, C. L., Carl V. Thompson, Kin Leong Pey, Wee Kiong Choi, F. Wei, S. P. Hau-Riege, R. Augur, H. L. Tay, B. Yu e M. K. Radhakrishnan. "Investigation of the Fundamental Reliability Unit for Cu Dual-Damascene Metallization". 2002. http://hdl.handle.net/1721.1/3976.

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An investigation has been carried out to determine the fundamental reliability unit of copper dual-damascene metallization. Electromigration experiments have been carried out on straight via-to-via interconnects in the lower metal (M1) and the upper metal (M2), and in a simple interconnect tree structure consisting of straight via-to-via line with an extra via in the middle of the line (a "dotted-I"). Multiple failure mechanisms have been observed during electromigration testing of via-to-via Cu interconnects. The failure times of the M2 test structures are significantly longer than that of identical M1 structures. It is proposed that this asymmetry is the result of a difference in the location of void formation and growth, which is believed to be related to the ease of electromigration-induced void nucleation and growth at the Cu/Si₃N₄ interface. However, voids were also detected in the vias instead of in the Cu lines for some cases of early failure of the test lines. These early failures are suspected to be related to the integrity and reliability of the Cu via. Different magnitudes and directions of electrical current were applied independently in two segments of the interconnect tree structure. As with Al-based interconnects, the reliability of a segment in this tree strongly depends on the stress conditions of the connected segment. Beyond this, there are important differences in the results obtained under similar test conditions for Al-based and Cu-based interconnect trees. These differences are thought to be associated with variations in the architectural schemes of the two metallizations. The absence of a conducting electromigration-resistant overlayer in Cu technology allows smaller voids to cause failure in Cu compared to Al. Moreover, the Si₃N₄ overlayer that serves as an interlevel diffusion barrier provides sites for easy nucleation of voids and also provides a high diffusivity path for electromigration. The results reported here suggest that while segments are not the fundamental reliability unit for circuit-level reliability assessments for Al or Cu, vias, rather than trees, might be the appropriate fundamental units for the assessment of Cu reliability.
Singapore-MIT Alliance (SMA)

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Lee, Shou-Chung, e 李守忠. "Study of Low-k Dielectric Reliability of Cu Dual Damascene Interconnect". Thesis, 2011. http://ndltd.ncl.edu.tw/handle/36746950520209975701.

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博士
國立交通大學
電子研究所
99
This dissertation presents the modeling and characterization of low-k dielectric reliability of advanced Cu dual damascene interconnects. As the semiconductor integrated circuit continues shrink, the RC delay of interconnect has to decrease with the technology scaling for the need of speed and power consumption of advanced circuits. Since copper wire has been implemented to reduce R from 0.13um technology node, the major approach to further reduce RC delay is to use low-k dielectric material for advanced Cu interconnects. However, the reliability of low-k dielectric becomes a serious issue with the technology scaling. Both dielectric material scaling (lower dielectric constant) and interconnect geometrical size scaling will degrade the dielectric reliability. In this thesis, we investigated both the dielectric constant (k) and geometrical size dependence on the dielectric reliability. We develop a statistical model to accurately describe low-k failure distribution as a function of dielectric constant k and Cu line edge roughness (LER). In addition to the failure distribution modeling, we verified the field dependence of low-k breakdown by characterizing the geometrical variation effect on failure distributions. We show that both E- and ?呷-model are reasonable to describe the field dependence of low-k failures. It is well known that the low-k dielectric reliability degrade with the decreasing k-value because of the weakened dielectric breakdown strength. However, the fundamental understanding of this k-dependence is not clear in the semiconductor industry and there is no quantitative model to predict the dielectric reliability of Cu interconnects. In this thesis, we explained pore is acting as the local field enhancement region and will enhance the current conduction inside the dielectrics. The increasing porosity (decreasing k) will shorten the breakdown path and degrade low-k reliability based on the percolation theory. In addition to the k-scaling impact on low-k reliability, the Cu conductor line edge roughness (LER) has been an important issue from the reliability perspective. LER of Cu will cause a non-uniform dielectric thickness distribution between Cu wires and give a local high electric field region at the place of the small dielectric thickness and dominate dielectric failure time. We theoretically calculated this LER effect on dielectric failure time and determine the failure thickness as a function of test voltages. We show that the failure thickness occurs approximately at the place of minimum dielectric thickness under high voltage acceleration test conditions, while will shift to the nominal thickness at low-voltage use conditions because of the decreasing field acceleration effect. This analysis indicates that LER will dominate the failure distribution at high voltage test conditions but the intrinsic material property is relevant at low voltage use conditions. In this thesis, we demonstrate the de-convolution of LER and intrinsic low-k material properties from the acceleration failure distributions. We also show the shift in failure thickness will also introduce systematic errors for field acceleration model characterization if the stress electric field does not take this effect into account. We also analyzed the LER effect on failure distribution shape as a function of applied test voltages for various field dependence model of failures and concluded that E- or ?呷-model is reasonable to describe the field dependence of dielectric failures. Finally, combining the LER and porosity effect into a percolation theory, we show that Cu/low-k damascene interconnect is capable of approaching intrinsic performance of low-k dielectrics the with the process optimization. We model the intrinsic low-k reliability capability as a function of k. Our model show the low-k dielectric failure time will drop rapidly when k<2.3 (porosity > 30%) because the high density pores will connect to each other and form a high current path to enhance breakdown. This is the statistical nature for porous low-k dielectric breakdown and can be viewed as a fundamental limitation of porous low-k dielectrics.

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Huang, Cheng-Lin, e 黃震麟. "Study of Low-k Dielectric RC delay time of Cu Dual Damascene Interconnect". Thesis, 2013. http://ndltd.ncl.edu.tw/handle/90261802171882692825.

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Chang, Choon Wai, C. L. Gan, Carl V. Thompson, Kin Leong Pey e Wee Kiong Choi. "Observation of Joule Heating-Assisted Electromigration Failure Mechanisms for Dual Damascene Cu/SiO₂ Interconnects". 2003. http://hdl.handle.net/1721.1/3727.

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Failure mechanisms observed in electromigration (EM) stressed dual damascene Cu/SiO₂ interconnects trees were studied and simulated. Failure sites with âmelt patch’ or âcrater’ are common for test structures in the top metal layer, though the occurrence of such failure modes probably depends on the passivation layer thickness. Interconnects that were EM stressed for a short time and then stressed with increasing current to induce Joule heating in the line had similar failure sites to lines that were stressed to failure under standard EM conditions. This shows that some failure mechanisms during EM could be assisted by Joule heating effect.
Singapore-MIT Alliance (SMA)

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Capitoli di libri sul tema "Cu dual damascene processes"

Bär, E., W. Henke, S. List e J. Lorenz. "Integrated Three-Dimensional Topography Simulation and its Application to Dual-Damascene Processing". In Simulation of Semiconductor Processes and Devices 1998, 12–15. Vienna: Springer Vienna, 1998. http://dx.doi.org/10.1007/978-3-7091-6827-1_4.

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Tang, Jian She, Brian J. Brown, Steven Verhaverbeke, Han Wen Chen, Jim Papanu, Raymond Hung, Cathy Cai e Dennis Yost. "Aqueous Based Single Wafer Cu/Low-k Cleaning Process Characterization and Integration into Dual Damascene Process Flow". In Solid State Phenomena, 353–56. Stafa: Trans Tech Publications Ltd., 2005. http://dx.doi.org/10.4028/3-908451-06-x.353.

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Atti di convegni sul tema "Cu dual damascene processes"

Mukherjee-Roy, Moitreyee, Navab Singh, Sohan S. Mehta, Wai M. Chik, Chin Tiong Sim e Francis Cheong. "Evaluation of alignment target designs for Cu and low-K dual damascene processes". In Microlithography 2003, a cura di Daniel J. Herr. SPIE, 2003. http://dx.doi.org/10.1117/12.482800.

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Wang, Qi, Howard Gan, Linlin Zhao, Kevin Zheng, Emily Bei e Jay Ning. "Low-k breakdown improvement in 65nm dual-damascene Cu process". In 2008 9th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT). IEEE, 2008. http://dx.doi.org/10.1109/icsict.2008.4734786.

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Mukherjee-Roy, Moitreyee, Rakesh Kumar e Ganesh S. Samudra. "Evaluation of overlay measurement target designs for Cu dual-damascene process". In 26th Annual International Symposium on Microlithography, a cura di Neal T. Sullivan. SPIE, 2001. http://dx.doi.org/10.1117/12.436732.

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Motoyama, K., O. van der Straten, H. Tomizawa, J. Maniscalco e S. T. Chen. "Novel Cu reflow seed process for Cu/low-k 64nm pitch dual damascene interconnects and beyond". In 2012 IEEE International Interconnect Technology Conference - IITC. IEEE, 2012. http://dx.doi.org/10.1109/iitc.2012.6251656.

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Lee, Soo Gun, Hyeok-Sang Oh, Hong-Jae Shin, Jin-Gi Hong, Hyeon-Deok Lee e Hokyu Kang. "Evaluation of PECVD a-SiC:H as a Cu Diffusion Barrier Layer of Cu Dual Damascene Process". In 2000 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 2000. http://dx.doi.org/10.7567/ssdm.2000.a-2-6.

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Abe, M., K. Motoyama, Y. Kasama, K. Arita, F. Ito, H. Yamamoto, M. Tagami et al. "A robust 45 nm-node, dual damascene interconnects with high quality cu/barrier interface by a novel oxygen absorption process". In International Electron Devices Meeting 2005. IEEE, 2005. http://dx.doi.org/10.1109/iedm.2005.1609271.

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Deng, F. X., D. H. Zhang, H. Liao e H. Hu. "Advanced direct contact via (DCV) process with Ta/TaN/Ta tri-layer barrier for advanced BEOL dual damascene Cu interconnects". In 2010 17th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2010). IEEE, 2010. http://dx.doi.org/10.1109/ipfa.2010.5532243.

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Baek, Won-Chong. "Stressmigration studies on dual damascene Cu/oxide and Cu/low k interconnects". In STRESS-INDUCED PHENOMENA IN METALLIZATION: Seventh International Workshop on Stress-Induced Phenomena in Metallization. AIP, 2004. http://dx.doi.org/10.1063/1.1845856.

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Tsai, M. H., R. Augur, V. Blaschke, R. H. Havemann, E. T. Ogawa, P. S. Ho, W. K. Yeh, S. L. Shue, C. H. Yu e M. S. Liang. "Electromigration reliability of dual damascene Cu/CVD SiOC interconnects". In Proceedings of the IEEE 2001 International Interconnect Technology Conference. IEEE, 2001. http://dx.doi.org/10.1109/iitc.2001.930080.

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Pyun, J. W., W. C. Baek, D. Denning, A. Knorr, L. Smith, K. Pfeifer e P. S. Ho. "Electromigration Reliability of 60 nm Dual Damascene Cu Interconnects". In Proceedings of the IEEE 2006 International Interconnect Technology Conference. IEEE, 2006. http://dx.doi.org/10.1109/iitc.2006.1648659.

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