Letteratura scientifica selezionata sul tema "Flip-flop (electronics)"
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Articoli di riviste sul tema "Flip-flop (electronics)":
Mathis, Wolfgang. "100 years multivibrator-history, circuits and mathematical analysis". COMPEL - The international journal for computation and mathematics in electrical and electronic engineering 39, n. 3 (22 gennaio 2020): 725–37. http://dx.doi.org/10.1108/compel-10-2019-0411.
Lin, Dave Y. W., e Charles H. P. Wen. "A Delay-Adjustable, Self-Testable Flip-Flop for Soft-Error Tolerability and Delay-Fault Testability". ACM Transactions on Design Automation of Electronic Systems 26, n. 6 (28 giugno 2021): 1–12. http://dx.doi.org/10.1145/3462171.
Ragavendran, U., e M. Ramachandran. "Low Power and Low Complexity Flip-Flop Design using MIFGMOS". International Journal of Engineering & Technology 7, n. 3.1 (4 agosto 2018): 183. http://dx.doi.org/10.14419/ijet.v7i3.1.17233.
Guo, Wei Jia, Shu Bao Wang, Gui Jing Mei e Xiu Mei Zhang. "Swift Self-Starting Design of Sequential Logic Circuit Based on Karnaugh Map". Applied Mechanics and Materials 220-223 (novembre 2012): 1008–11. http://dx.doi.org/10.4028/www.scientific.net/amm.220-223.1008.
Rompis, Lianly. "A RANDOM COUNTER IN USING SHIFT REGISTER AND ENCODER". Jurnal Ilmiah Realtech 14, n. 1 (30 aprile 2018): 64–68. http://dx.doi.org/10.52159/realtech.v14i1.118.
Rahman, Aminur, Ian Jordan e Denis Blackmore. "Qualitative models and experimental investigation of chaotic NOR gates and set/reset flip-flops". Proceedings of the Royal Society A: Mathematical, Physical and Engineering Sciences 474, n. 2209 (gennaio 2018): 20170111. http://dx.doi.org/10.1098/rspa.2017.0111.
Prema, S., N. Karthikeyan e S. Karthik. "Ultra-Low Power and High Sensitivity of Joint Clock Gating Based Dual Feedback Edge Triggered Flip Flop for Biomedical Imaging Applications". Journal of Medical Imaging and Health Informatics 11, n. 12 (1 dicembre 2021): 3215–22. http://dx.doi.org/10.1166/jmihi.2021.3919.
Hassan, Ahmad, Jean-Paul Noël, Yvon Savaria e Mohamad Sawan. "Circuit Techniques in GaN Technology for High-Temperature Environments". Electronics 11, n. 1 (23 dicembre 2021): 42. http://dx.doi.org/10.3390/electronics11010042.
Wang, An Jing, e Yu Zhuo Fu. "Multi-Bit Flip-Flop Replacement Method Optimization and Synthesis Impact". Applied Mechanics and Materials 716-717 (dicembre 2014): 1239–43. http://dx.doi.org/10.4028/www.scientific.net/amm.716-717.1239.
Komshina, A., S. Telibaev e B. S. Mikhlin. "ASSEMBLING THE RS FLIP-FLOP ON CHIPS CONTAINING ELEMENTS OF "OR-NOT", "AND-NOT"". Informatics in school, n. 7 (17 novembre 2018): 17–25. http://dx.doi.org/10.32517/2221-1993-2018-17-7-17-25.
Tesi sul tema "Flip-flop (electronics)":
Yongyi, Yuan. "Investigation and implementation of data transmission look-ahead D flip-flops". Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2529.
This thesis investigates four D flip-flops with data transmission look-ahead circuits. Based on logical effort and power-delay products to resize all the transistor widths along the critical path in µm CMOS technology. The main goal is to verify and proof this kind of circuits can be used when the input data have low switching probabilities. From comparing the average energy consumption between the normal D flip-flops and D flip-flops with look-ahead circuits, D flip-flops with look-ahead circuits consume less power when the data switching activities are low.
Johansson, Kenny. "Low Complexity and Low Power Bit-Serial Multipliers". Thesis, Linköping University, Department of Electrical Engineering, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1751.
Bit-serial multiplication with a fixed coefficient is commonly used in integrated circuits, such as digital filters and FFTs. These multiplications can be implemented using basic components such as adders, subtractors and D flip-flops. Multiplication with the same coefficient can be implemented in many ways, using different structures. Other studies in this area have focused on how to minimize the number of adders/subtractors, and often assumed that the cost for D flip-flops is neglectable. That simplification has been proved to be far too great, and further not at all necessary. In digital devices low power consumption is always desirable. How to attain this in bit-serial multipliers is a complex problem.
The aim of this thesis was to find a strategy on how to implement bit-serial multipliers with as low cost as possible. An important step was achieved by deriving formulas that can be used to calculate the carry switch probability in the adders/subtractors. It has also been established that it is possible to design a power model that can be applied to all possible structures of bit- serial multipliers.
Hansson, Martin. "Low-Power Multi-GHz Circuit Techniques for On-chip Clocking". Licentiate thesis, Linköping : Linköping University, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-7545.
Jovanovic, Natalija. "Bascules et registres non-volatiles à base de ReRAM en technologies CMOS avancées". Thesis, Paris, ENST, 2016. http://www.theses.fr/2016ENST0023.
Non-volatile memories and flip-flops can improve the energy efficiency in battery-operated devices by eliminating the sleep-mode consumption, while maintaining the system state. Among emerging embedded NVM technologies, ReRAMs differentiate itself with a fast programming time, a simple CMOS-compatible structure and a good scalability. Previously proposed ReRAM-based non-volatile flip-flops (NVFF) have been implemented in 90nm or older CMOS nodes and suffer from CMOS reliability issues in scaled nodes due to high programming and forming voltages. This thesis makes the analysis of robust and reliable non-volatile design in 28nm CMOS node and below. It presents two novel thin-gate oxide CMOS design solutions for the programming of ReRAM devices. The programming circuits are applied in dual-voltage NVFF architecture which employs two ReRAM devices (2R). Alternative 1R NVFF architecture is also proposed in order to achieve higher density and lower consumption. With regard to the existing ReRAM technologies, given NVFF solutions are optimized for ReRAM programming conditions which improve endurance and minimize programming power. Statistical analysis of the FF core and its optimization was performed, to evaluate the best restore operation architectures which meet digital CMOS circuit design yield requirements. The NVFFs are implemented in 28nm CMOS FDSOI and benchmarked against a master slave flip-flop from a standard library and a data-retention flip-flop. Finally, to minimize the NVFF area overhead without impacting the robustness of \nv{} operations, multi-port non-volatile register file (NVRF) based on the 1R NVFF solution is proposed
Kocina, Filip. "Moderní metody modelování a simulace elektronických obvodů". Doctoral thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2017. http://www.nusl.cz/ntk/nusl-412585.
Jagirdar, Aditya. "Novel flip-flop designs tolerant to soft-errors and crosstalk effects". 2007. http://hdl.rutgers.edu/1782.2/rucore10001600001.ETD.16402.
Jadidi, Tayebeh. "In-silico Modeling of Lipid-Water Complexes and Lipid Bilayers". Doctoral thesis, 2013. https://repositorium.ub.uni-osnabrueck.de/handle/urn:nbn:de:gbv:700-2013102111709.
Libri sul tema "Flip-flop (electronics)":
Steel, Duncan G. Introduction to Quantum Nanotechnology. Oxford University Press, 2021. http://dx.doi.org/10.1093/oso/9780192895073.001.0001.
Capitoli di libri sul tema "Flip-flop (electronics)":
Kumari, Reshmi, Sneha Pandey, Swarnima e Surya Deo Choudhary. "Metastability Mitigation and Error Masking of High-Speed Flip-Flop". In Micro-Electronics and Telecommunication Engineering, 533–39. Singapore: Springer Singapore, 2022. http://dx.doi.org/10.1007/978-981-16-8721-1_52.
Srivastava, Pragya, Ramsha Suhail, Richa Yadav e Richa Srivastava. "Whistle-stop Low-power MCML technique to design Toggle Flip-Flop at nanoscale regime". In Recent Trends in Communication and Electronics, 460–66. London: CRC Press, 2021. http://dx.doi.org/10.1201/9781003193838-86.
Kotta, Satish, e Rajanbabu Mallavarapu. "Novel Design of Pulse Trigger Flip-Flop with High Speed and Power Efficiency". In Proceedings of 2nd International Conference on Micro-Electronics, Electromagnetics and Telecommunications, 239–46. Singapore: Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-4280-5_25.
"Latch and Flip-Flop". In Digital Electronics 2, 1–50. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2016. http://dx.doi.org/10.1002/9781119329756.ch1.
Crowe, John, e Barrie Hayes-Gill. "Flip-flops and flip-flop based circuits". In Introduction to Digital Electronics, 150–63. Elsevier, 1998. http://dx.doi.org/10.1016/b978-034064570-3/50008-3.
"HOW TO MAKE A D TYPE FLIP FLOP FROM BASIC GATES". In Computer Electronics, 179. Elsevier, 1985. http://dx.doi.org/10.1016/b978-0-434-98405-3.50023-x.
"Radiation hard circuit design: flip-flop and SRAM". In VLSI and Post-CMOS Electronics. Volume 2: Devices, circuits and interconnects, 249–78. Institution of Engineering and Technology, 2019. http://dx.doi.org/10.1049/pbcs073g_ch12.
"The impact of Negative Bias Temperature Instability (NBTI) effect on D flip-flop". In Electronics and Electrical Engineering, 265–70. CRC Press, 2015. http://dx.doi.org/10.1201/b18443-50.
Atti di convegni sul tema "Flip-flop (electronics)":
Kim, Min-su, Bai-Sun Kong, Chil-Gee Lee, Tae-Hyung Kim, Sung Bae Park e Young-Hyun Jun. "Nonoverlapping Cuspid-Pulsed Flip-Flop". In 2007 14th IEEE International Conference on Electronics, Circuits and Systems (ICECS '07). IEEE, 2007. http://dx.doi.org/10.1109/icecs.2007.4510954.
Nagesh, B., e B. S. Nikhil Chandra. "Designof Efficient Scan Flip-Flop". In 2021 International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT). IEEE, 2021. http://dx.doi.org/10.1109/rteict52294.2021.9573924.
Joachim, C., G. Treboux e H. Tang. "A model conformational flip-flop molecular switch". In Molecular electronics—Science and Technology. AIP, 1992. http://dx.doi.org/10.1063/1.42677.
Stipcevic, Mario. "Random flip-flop and its applications". In 2014 37th International Convention on Information and Communication Technology, Electronics and Microelectronics (MIPRO). IEEE, 2014. http://dx.doi.org/10.1109/mipro.2014.6859784.
Wang, Danni, Sumitha George, Ahmedullah Aziz, Suman Datta, Vijaykrishnan Narayanan e Sumeet K. Gupta. "Ferroelectric Transistor based Non-Volatile Flip-Flop". In ISLPED '16: International Symposium on Low Power Electronics and Design. New York, NY, USA: ACM, 2016. http://dx.doi.org/10.1145/2934583.2934603.
Sharma, Manisha, K. G. Sharma, Tripti Sharma, B. P. Singh e Neha Arora. "SET D-flip flop design for portable applications". In 2010 India International Conference on Power Electronics (IICPE). IEEE, 2011. http://dx.doi.org/10.1109/iicpe.2011.5728081.
Brindha, B., V. S. Kanchana Bhaaskaran, C. Vinoth, V. Kavinilavu e Samiappa Sakthikumaran. "Optimization of sense amplifier energy recovery flip-flop". In 2011 3rd International Conference on Electronics Computer Technology (ICECT). IEEE, 2011. http://dx.doi.org/10.1109/icectech.2011.5941614.
Sadrossadat, Sayed Alireza, Minoo Mirsaeedi, Kumaraswamy Ponnambalam e Mohab Anis. "Framework for statistical design of a flip-flop". In 2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009). IEEE, 2009. http://dx.doi.org/10.1109/icecs.2009.5410810.
Moradi, Farshad, Dag Wisland, Jens Kargaard Madsen e Hamid Mahmoodi. "Flip-flop design using novel pulse generation technique". In 2012 19th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2012). IEEE, 2012. http://dx.doi.org/10.1109/icecs.2012.6463633.
Sushma, R., e N. S. Murty. "Feedback Oriented XORed Flip-Flop Based Arbiter PUF". In 2018 Third International Conference on Electrical, Electronics, Communication, Computer Technologies and Optimization Techniques (ICEECCOT). IEEE, 2018. http://dx.doi.org/10.1109/iceeccot43722.2018.9001605.