Bibliografie tematiche / H.264/AVC video compression

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Letteratura scientifica selezionata sul tema "H.264/AVC video compression"

Autore: Grafiati

Pubblicato: 4 giugno 2021

Ultima modifica: 13 febbraio 2022

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Articoli di riviste sul tema "H.264/AVC video compression"

Sharabayko, M. P., e N. G. Markov. "H.264/AVC Video Compression on Smartphones". Journal of Physics: Conference Series 803 (gennaio 2017): 012141. http://dx.doi.org/10.1088/1742-6596/803/1/012141.

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Sun, Y., Y. Zhou, S. Sun, Z. Feng e Z. He. "Incremental rate control for H.264/AVC video compression". IET Image Processing 3, n. 5 (1 ottobre 2009): 286–98. http://dx.doi.org/10.1049/iet-ipr.2009.0037.

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Roszkowski, Mikołaj, Andrzej Abramowski, Michał Wieczorek e Grzegorz Pastuszak. "Architecture Design of The Hardware H.264/AVC Video Decoder". International Journal of Electronics and Telecommunications 56, n. 3 (1 settembre 2010): 291–300. http://dx.doi.org/10.2478/v10177-010-0039-7.

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Architecture Design of The Hardware H.264/AVC Video DecoderThe need for real-time video compression systems requires a particular design methodology to achieve high troughput devices. The paper describes the architecture of the H.264/AVC decoder able to support SDTV and HDTV resolutions. The design applies many optimization techniques to reduce the resource consumption and maximize the throughput. The archietcture is verified with the software reference model JM16 and synhesized for FPGA technology. The maximal working frequency is 100 MHz for Stratix II devices.

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Sullivan, G. J., e T. Wiegand. "Video Compression - From Concepts to the H.264/AVC Standard". Proceedings of the IEEE 93, n. 1 (gennaio 2005): 18–31. http://dx.doi.org/10.1109/jproc.2004.839617.

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Rad, Farhad, e Ali Broumandnia. "An Efficient Implementation of the Entire Transforms in the H.264/AVC Encoder using VHDL". International Journal of Reconfigurable and Embedded Systems (IJRES) 2, n. 3 (1 novembre 2013): 116. http://dx.doi.org/10.11591/ijres.v2.i3.pp116-121.

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The H.264/AVC standard achieves remarkable higher compression performance than the previous MPEG and H.26X standards. One of the computationally intensive units in the MPEG and H.26X video coding families is the Discrete Cosine Transform (DCT). In this paper, we propose an efficient implementation of the DCT, inverse DCTs and the Hadamard transforms in the H.264/AVC encoder using VHDL. The synthesis results indicate that our implementation of the entire transforms achieves lower power, delay and area consumption compared to the existing architectures in the H.264/AVC encoder.

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Sowmyayani, S., e P. Arockia Jansi Rani. "An Efficient Temporal Redundancy Transformation for Wavelet Based Video Compression". International Journal of Image and Graphics 16, n. 03 (luglio 2016): 1650015. http://dx.doi.org/10.1142/s0219467816500157.

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The objective of this work is to propose a novel idea of transforming temporal redundancies present in videos. Initially, the frames are divided into sub-blocks. Then, the temporally redundant blocks are grouped together thus generating new frames with spatially redundant temporal data. The transformed frames are given to compression in the wavelet domain. This new approach greatly reduces the computational time. The reason is that the existing video codecs use block matching methods for motion estimation which is a time consuming process. The proposed method avoids the use of block matching method. The existing H.264/AVC takes approximately one hour to compress a video file where as the proposed method takes only one minute for the same task. The experimental results substantially proved that the proposed method performs better than the existing H.264/AVC standard in terms of time, compression ratio and PSNR.

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Milicevic, Zoran, e Zoran Bojkovic. "An approach to selective intra coding and early inter skip prediction in H.264/AVC standard". Facta universitatis - series: Electronics and Energetics 21, n. 1 (2008): 107–19. http://dx.doi.org/10.2298/fuee0801107m.

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This paper presents selective intra coding and early inter skip fast mode decision algorithm for H.264/AVC and compares performance of H.264/AVC with prior standards. Video coding standard H.264/AVC provides gains in compression efficiency of up to 50% over a wide range of bit rates and video resolutions compared to previous standards. In order to achieve this, a robust rate-distortion optimization (RDO) technique is employed to select best coding mode and reference frame for each macroblock. Also, the original and modification test models are compared for combined skip and intra prediction method in H.264/AVC encoder, when ? pictures are analyzed. Experimental results show that the coding time is reduced by 35-42% through early identification of macroblocks that are likely to be skipped during the coding process and through reducing the number of candidate modes. .

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A. Suthar, Haresh. "VHDL Implementation of H.264 Video Coding Standard". International Journal of Reconfigurable and Embedded Systems (IJRES) 1, n. 3 (1 novembre 2012): 95. http://dx.doi.org/10.11591/ijres.v1.i3.pp95-102.

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<p>This Paper contains VHDL implementation of H.264 video coding standard, which is new video coding standard of the ITU-T Video Coding Experts Group and the ISO/IEC Moving Picture Experts Group. The main goal of the H.264/AVC standardization effort is to enhance compression performance and provision of a “network-friendly” video representation addressing “conversational” (video telephony) and “no conversational” (storage, broadcast, or streaming) applications.H.264 video coder standard is having fundamental blocks like transform and quantization, Intra prediction, Inter prediction and Context Adaptive Variable Length Coding (CAVLC). Each block is designed and integrated to one top module in VHDL.</p>

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Yan, Tao, Xiao Xiong Zhou, Wen Ting Luo, Ze Liang Liu e Pan Dong Zhang. "Multi-View Video Coding Based on Video Correction". Advanced Materials Research 989-994 (luglio 2014): 3714–17. http://dx.doi.org/10.4028/www.scientific.net/amr.989-994.3714.

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In order to enables the video to be displayed on a multitude of different terminals, Multi-view video coding (MVC) demands high compression rates as well as view scalability. A new the inter-view prediction structure with flexibility, MVC compatibility and view scalability is proposed. The proposed scheme first correct views. It then uses the position of the cameras and the relation of inter-views to divide all views into base view and enhancement views. Finally, the views quire by the viewers use scalable Multi-view Video Coding (SMVC). The main bitstream is the same as a H.264/AVC mono-sequence bitstream for H.264/AVC compatibility. The auxiliary bitstream come from enhancement views coding. We proposed SMVC scheme is tested with two Multi-view sequences to determine its flexibly view scalability, high coding efficiency and random access performance.

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Indoonundon, Deevya, Tulsi Pawan Fowdur e Sunjiv Soyjaudah. "A Concealment Aware UEP scheme for H.264 using RS Codes". Indonesian Journal of Electrical Engineering and Computer Science 6, n. 3 (1 giugno 2017): 671. http://dx.doi.org/10.11591/ijeecs.v6.i3.pp671-681.

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<p>H.264/AVC is currently the most widely adopted video coding standard due to its high compression capability and flexibility. However, compressed videos are highly vulnerable to channel errors which may result in severe quality degradation of a video. This paper presents a concealment aware Unequal Error Protection (UEP) scheme for H.264 video compression using Reed Solomon (RS) codes. The proposed UEP technique assigns a code rate to each Macroblock (MB) based on the type of concealment and a Concealment Dependent Index (CDI). Two interleaving techniques, namely Frame Level Interleaving (FLI) and Group Level Interleaving (GLI) have also been employed. Finally, prioritised concealment is applied in cases where error correction is beyond the capability of the RS decoder. Simulation results have demonstrated that the proposed framework provides an average gain of 2.96 dB over a scheme that used Equal Error Protection (EEP).</p>

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Più fonti

Tesi sul tema "H.264/AVC video compression"

Kannangara, Chaminda Sampath. "Complexity management of H.264/AVC video compression". Thesis, Robert Gordon University, 2006. http://hdl.handle.net/10059/643.

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The H. 264/AVC video coding standard offers significantly improved compression efficiency and flexibility compared to previous standards. However, the high computational complexity of H. 264/AVC is a problem for codecs running on low-power hand held devices and general purpose computers. This thesis presents new techniques to reduce, control and manage the computational complexity of an H. 264/AVC codec. A new complexity reduction algorithm for H. 264/AVC is developed. This algorithm predicts "skipped" macroblocks prior to motion estimation by estimating a Lagrange ratedistortion cost function. Complexity savings are achieved by not processing the macroblocks that are predicted as "skipped". The Lagrange multiplier is adaptively modelled as a function of the quantisation parameter and video sequence statistics. Simulation results show that this algorithm achieves significant complexity savings with a negligible loss in rate-distortion performance. The complexity reduction algorithm is further developed to achieve complexity-scalable control of the encoding process. The Lagrangian cost estimation is extended to incorporate computational complexity. A target level of complexity is maintained by using a feedback algorithm to update the Lagrange multiplier associated with complexity. Results indicate that scalable complexity control of the encoding process can be achieved whilst maintaining near optimal complexity-rate-distortion performance. A complexity management framework is proposed for maximising the perceptual quality of coded video in a real-time processing-power constrained environment. A real-time frame-level control algorithm and a per-frame complexity control algorithm are combined in order to manage the encoding process such that a high frame rate is maintained without significantly losing frame quality. Subjective evaluations show that the managed complexity approach results in higher perceptual quality compared to a reference encoder that drops frames in computationally constrained situations. These novel algorithms are likely to be useful in implementing real-time H. 264/AVC standard encoders in computationally constrained environments such as low-power mobile devices and general purpose computers.

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Bahari, Asral. "Low power architectures for MPEG-4 AVC/H.264 video compression". Thesis, University of Edinburgh, 2008. http://hdl.handle.net/1842/10695.

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Multimedia communication will be an important application in future wireless communication. The second-generation mobile communication systems already support basic multimedia services such as voice, text-messaging services and still-imaging communication. However, next generation wireless communication technology combined with advances in integrated circuit design and process fabrication technology will allow more data to be processed and transmitted through wireless channels. This will lift the current barriers and enable more demanding multimedia applications such as video telephony, video conferencing and video streaming. Video compression plays an important role in today's wireless communications. It allows raw video data to be compressed before it is sent through a wireless channel. However, video compression is compute-intensive and dissipates a significant amount of power. This is a major limitation in today's portable devices. Existing multimedia devices can only play video applications for a short time before the battery is depleted. This limits the user's entertainment experience and becomes a major bottleneck for the development of more attractive applications. The focus of this thesis is to design a low power video compression system for wireless communication. in this thesis, we propose techniques to minimise the power consumption at the algorithmic and architectural level. The low power is achieved by minimising the switching power between interacting modules that contribute to major the power consumption in H.264 standard. Motion estimation (ME) has been identified as the main bottleneck in MPEG video compression, including in the H.264 system where it takes up to 90% of the coding time. To reduce the power consumption in motion estimation hardware architecture, we have proposed a two-step algorithm that minimises the memory bandwidth and computational load of the ME. In this technique, the search is performed in low resolution mode at the first stage followed by high resolution mode in the second stage. This method reduces the total computation and memory access compared to the conventional method without significantly degrading the picture quality. The simulation results show that the proposed method gives good PSNR as compared to the conventional full search with PSNR drop < 0.5dB. An energy efficient hardware for implementing the proposed two-step method is suggested. The architecture is able to perform both low resolution and high resolution searches without significantly increasing the area overhead. With a unique pixel arrangement, the proposed method is able to perform at both low resolution and high resolution while still being able In to reduce the memory bandwidth. The results show that the proposed architecture is able to save up to 53% energy as compared to the conventional full search architecture.

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Brown, Michelle M. "Hardware study on the H.264/AVC video stream parser /". Online version of thesis, 2008. http://hdl.handle.net/1850/7766.

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Adams, Tanner Ryan. "Computationally Efficient Basic Unit Rate Control for H.264/AVC". University of Dayton / OhioLINK, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1386097674.

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Ramos, Fabio Luis Livi. "Arquitetura para o algoritmo CAVLC de codificação de entropia segundo o padrão H.264/AVC". reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2010. http://hdl.handle.net/10183/31120.

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A codificação de vídeo digital depende de uma série de etapas para ser alcançada a compressão de dados necessária para, então, o vídeo ser enviado ou armazenado em um meio. Existe uma série de padrões que se propõe a isso e dentre eles, o que apresenta o melhor desempenho em termos de compressão de dados e qualidade de vídeo até o presente momento é o H.264/AVC. Considerando então o padrão H.264/AVC, uma das etapas do seu processamento é a codificação de entropia, sendo que um dos algoritmos usados para esse fim é o CAVLC (Context-Based Adaptive Variable Length Coding). Esta técnica faz uso de uma série de características onde o código gerado pela seqüência de vídeo processada tende a assumir, para, então, gerar códigos menores para padrões do vídeo que tendem a aparecer mais freqüentemente em detrimento a padrões que são mais raros, fazendo para isso uso de código de comprimento variável que depende do contexto atual em que cada porção do código está sendo processada. Baseado nisso, este trabalho apresenta uma arquitetura para o algoritmo CAVLC segundo o padrão H.264/AVC, onde foi inserida uma nova técnica para diminuir o gargalo na etapa inicial do algoritmo, além de usar técnicas já conhecidas na literatura para diminuir os ciclos necessários para o processamento do componente, fazendo com que a arquitetura aqui apresentada tenha um ganho em relação aos demais trabalhos da literatura encontrados e comparados. Esse trabalho está inserido no esforço do grupo de TV Digital da UFRGS e pretende-se que, no futuro, esse módulo seja integrado aos demais módulos desenvolvidos no grupo para formar um codificador H.264/AVC completo.
The digital video encoding depends on different phases to reach the necessary data compression, so the video can be transmitted through or stored in the medium. There are a variety of compression standards that are designed to that purpose and, among them, the one that has the best performance currently is the H.264/AVC. Considering the H.264/AVC standard, one of the processing stages is the entropy encoding. CAVLC (Context-Based Adaptive Variable Length Coding) is one of the algorithms that can be used for that end. It can use many of the code particularities, generated by the video sequence being processed. This way, CAVLC can generate codes with less bits for portions of the video sequence that occur more often, and codes with more bits for rarer patterns of the video sequence, using variable code lengths that depend on the current context for each portion of the code being processed. Based on this, the present work presents a VLSI hardware architecture for the CAVLC algorithm, according to the H.264/AVC standard. The architecture introduces a new technique to decrease the bottleneck at the initial stage of the algorithm and, furthermore, well-known techniques already tested in works found in the literature, were also implemented, to save processing cycles at the other stages of the component. The present architecture is then able to achieve gains compared to the other works found in the literature. This work is inserted into the effort of the Digital TV Group at UFRGS and it is intended to be integrated with the others developed by the group to make a complete H.264/AVC encoder.

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Ernst, Eric Gerard. "Architecture design of a scalable adaptive deblocking filter for H.264/AVC /". Online version of thesis, 2007. http://hdl.handle.net/1850/5390.

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Porto, Roger Endrigo Carvalho. "Desenvolvimento arquitetural para estimação de movimento de blocos de tamanhos variáveis segundo padrão H.264/AVC de compressão de vídeo digital". reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2008. http://hdl.handle.net/10183/17348.

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Apesar de as capacidades de transmissão e de armazenamento dos dispositivos continuarem crescendo, a compressão ainda é essencial em aplicações que trabalham com vídeo. Com a compressão reduz-se significativamente a quantidade de bits necessários para se representar uma seqüência de vídeo. Dentre os padrões de compressão de vídeo digital, o mais novo é o H.264/AVC. Este padrão alcança as mais elevadas taxas de compressão se comparado com os padrões anteriores mas, por outro lado, possui uma elevada complexidade computacional. A complexidade computacional elevada dificulta o desenvolvimento em software de aplicações voltadas a definições elevadas de imagem, considerando a tecnologia atual. Assim, tornam-se indispensáveis implementações em hardware. Neste escopo, este trabalho aborda o desenvolvimento de uma arquitetura para estimação de movimento de blocos de tamanhos variáveis segundo o padrão H.264/AVC de compressão de vídeo digital. Esta arquitetura utiliza o algoritmo full search e SAD como critério de similaridade. Além disso, a arquitetura é capaz de gerar os 41 diferentes vetores de movimento referentes a um macrobloco e definidos pelo padrão. A solução arquitetural proposta neste trabalho foi descrita em VHDL e mapeada para FPGAs da Xilinx. Também foi desenvolvida uma versão standard cell da arquitetura. Considerando-se as versões da arquitetura com síntese direcionada para FPGA, os resultados mostraram que a arquitetura pode ser utilizada em aplicações voltadas para alta definição como SDTV ou HDTV. Para a versão standard cells da arquitetura os resultados indicam que ela pode ser utilizada para aplicações SDTV.
The transmission and storage capabilities of the digital communications and processing continue to grow. However, compression is still necessary in video applications. With compression, the amount of bits necessary to represent a video sequence is dramatically reduced. Amongst the video compression standards, the latest one is the H.264/AVC. This standard reaches the highest compression rates when compared to the previous standards. On the other hand, it has a high computational complexity. This high computational complexity makes it difficult the development of applications targeting high definitions when a software implementation running in a current technology is considered. Thus, hardware implementations become essential. Addressing the hardware architectures, this work presents the architectural design for the variable block-size motion estimation defined in the H.264/AVC standard. This architecture is based on full search motion estimation algorithm and SAD calculation. This architecture is able to produce the 41 motion vectors within a macroblock that are specified in the standard. The architecture designed in this work was described in VHDL and it was mapped to Xilinx FPGAs. Extensive simulations of the hardware architecture and comparisons to the software implementation of the same variable-size algorithm were used to validate the architecture. It was also synthesized to standard cells. Considering the synthesis results, the architecture reaches real time for high resolution videos, as HDTV when mapped to FPGAs. The standard cells version of this architecture is able to reach real time for SDTV resolution, considering a physical synthesis to 0.18µm CMOS.

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Depra, Dieison Antonello. "Algoritmos e desenvolvimento de arquitetura para codificação binária adaptativa ao contexto para o decodificador H.264/AVC". reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2009. http://hdl.handle.net/10183/26505.

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As inovações tecnológicas têm propiciado transformações nas formas de interação e, principalmente, na comunicação entre as pessoas. Os avanços nas áreas de tecnologia da informação e comunicações abriram novos horizontes para a criação de demandas até então não existentes. Nesse contexto, a utilização de vídeo digital de alta definição para aplicações de tempo real ganha ênfase. Entretanto, os desafios envolvidos na manipulação da quantidade de informações necessárias à sua representação, fomentam pesquisas na indústria e na academia para minimizar os impactos sobre a largura de banda necessária para transmissão e/ou no espaço para o seu armazenamento. Para enfrentar esses problemas diversos padrões de compressão de vídeo têm sido desenvolvidos sendo que, nesse aspecto, o padrão H.264/AVC é considerado o estado da arte. O padrão H.264/AVC introduz ganhos significativos na taxa de compressão, em relação a seus antecessores, porém esses ganhos vêem acompanhados pelo aumento na complexidade computacional das ferramentas aplicadas como, por exemplo, a Codificação Aritmética Binária Adaptativa ao Contexto (CABAC). A complexidade computacional relacionado ao padrão H.264/AVC é tal que torna impraticável sua execução em software (para operar em um processador de propósito geral, ao menos para nos disponíveis atuais) com a finalidade de realizar a codificação ou decodificação em tempo real para sequências de vídeo de alta definição. Esta dissertação apresenta uma arquitetura de hardware para o processo de decodificação do CABAC, conforme especificação do padrão H.264/AVC. Tendo o objetivo de contribuir para a resolução de alguns dos problemas relacionados à tarefa de decodificação de vídeo de alta definição em tempo real. Para isso, apresenta-se uma introdução sobre conceitos fundamentais da compressão de dados e vídeo digital, além da discussão sobre as principais características do padrão H.264/AVC. O conjunto de algoritmos presentes no CABAC e o fluxo de decodificação do CABAC são descritos em detalhes. Para fundamentar as decisões de projeto um vasto conjunto de experimentos foi realizado para analisar o comportamento do bitstream durante o processo de decodificação do CABAC. A arquitetura de hardware proposta e desenvolvida é apresentada em detalhes, tendo seu desempenho comparado com outras propostas encontradas na literatura. Os resultados obtidos mostram que a arquitetura desenvolvida é eficaz em seu objetivo, pois atinge a capacidade de processamento de vídeos em alta definição (HD1080p) em tempo real. Além disso, os experimentos realizados deram origem a observações inovadoras, que permitiram determinar os pontos chave para minimizar os gargalos inerentes ao conjunto de algoritmos que compõe o CABAC.
The technological innovations of recent decades have brought changes in the forms of human interaction especially in communication area. Advances in the areas of information technology and communications opened new horizons for creating demands non-existent so far. In this scenario the high-definition digital video for real-time applications has gained emphasis for this context. However, the challenges involved in handling the amount of information necessary for its representation, promoting research in industry and academia to minimize the impact on the bandwidth needed for transmission and / or the space for the storage. To address those problems several video compression standards have been developed and the H.264/AVC standard is the state-of-the-art. The H.264/AVC standard introduces significant gains in compression rate, compared to its predecessors. These gains are obtained by an increase in computational complexity of the techniques used, such as the CABAC. The computational requirements of H.264/AVC standard is so strong that make its implementation impractical in software (to operate on a general purpose processor) for the purpose of performing encoding or decoding in real time for high-definition video sequences. This dissertation presents a new CABAD architecture with the implementation in hardware intended to solve the problems related to the task of decoding high-definition video in real time. An introduction to fundamental concepts of data compression and digital video is presented, in addition to discussing the main features of the H.264/AVC standard. The set of algorithms the CABAC and of the CABAD decode flow are described in detail. A wide number of experiments were conducted to identify the static and dynamic behavior of the bitstream to support the design decisions. At the end the developed architecture is examined and compared with other proposals found in literature. The results show that the architecture developed is effective in its purpose to handle high-definition video (HD1080p) in real time. Furthermore, the experiments have led to innovative observations to determine the key points to minimize the bottlenecks inherent in the set of algorithms that make the CABAD.

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Silva, Leandro Max de Lima. "Implementação física de arquiteturas de hardware para a decodificação de vídeo digital segundo o padrão H.264/AVC". reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2010. http://hdl.handle.net/10183/27655.

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Abstract (sommario):

Recentemente, o Brasil adotou o padrão SBTVD (Sistema Brasileiro de TV Digital) para transmissão de TV digital. Este utiliza o CODEC (codificador e decodificador) de vídeo H.264/AVC, que é considerado o estado-da-arte no contexto de compressão de vídeo digital. Esta transição para o SBTVD requer o desenvolvimento de tecnologia para transmissão, recepção e decodificação de sinais, assim, o projeto Rede H.264 SBTVD foi iniciado e tem como um dos objetivos a produção de componentes de hardware para construção de um set-top box SoC (System on Chip) compatível com o SBTVD. No sentido de produzir IPs (Intellectual Property) para codificação e decodificação de vídeo digital segundo o padrão H.264/AVC, várias arquiteturas de hardware vêm sendo desenvolvidas no âmbito do projeto. Assim, o objetivo deste trabalho consiste na realização da implementação física em ASIC (Application-Specific Integrated Circuit) de algumas destas arquiteturas de hardware para decodificação de vídeo H.264/AVC, entre elas as arquiteturas parser e decodificação de entropia, predição intra-quadro e, por fim, quantização e transformadas inversas, que juntas formam uma versão funcional de um decodificador de vídeo H.264 chamado de decodificador intra-only. Além destas, também foi fisicamente implementada uma arquitetura para o módulo filtro redutor de efeito de bloco e arquiteturas para os perfis Main e High de um compensador de movimentos. Nesta dissertação de mestrado, é apresentada a metodologia de implementação standard-cells (ASIC) utilizada, assim como uma descrição detalhada de cada passo executado para se chegar ao leiaute de cada uma das arquiteturas. Também são apresentados os resultados das implementações e realizadas algumas comparações com outras implementações de arquiteturas descritas na literatura. A implementação do filtro possui 43,9K portas lógicas (equivalent-gates), 42mW de potência e possui a menor quantidade de memória interna, 12,375KB SRAM, quando comparada com outras implementações para a mesma resolução de vídeo, 1920x1080@30fps. As implementações para os perfis Main e High do compensador de movimento apresentam a melhor relação entre a quantidade de ciclos de relógio necessária para interpolar um macrobloco (MB), 304 ciclos/MB, e a quantidade de equivalent-gates de cada implementação, 98K e 102K, respectivamente. Já a implementação do decodificador H.264 intra-only possui 5KB SRAM, 11,4mW de potência e apresenta a menor quantidade de equivalent-gates, 150K, comparado com outras implementações de decodificadores H.264 com características similares.
Recently Brazil has adopted the SBTVD (Brazilian Digital Television System) for digital TV transmission. It uses the H.264/AVC video CODEC (coder and decoder), which is considered the state of the art in the context of digital video compression. This transition to the SBTVD standard requires the development of technology for transmitting, receiving and decoding signals, so a project called Rede H.264 was initiated with the objective of producing cutting edge hardware components to build a set-top box SoC (System on Chip) compatible with the SBTVD. In order to produce IPs (Intellectual Property) for encoding and decoding digital video according to the H.264/AVC standard, many hardware architectures have been developed under the project. Therefore, the objective of this work is to carry out the physical implementation flow for ASIC (Application-Specific Integrated Circuit) in some of these hardware architectures for H.264/AVC video decoding, including the architectures parser and entropy decoding, intra-prediction and inverse quantization and transforms, which together compound a working version of an H.264 video decoder called intra-only. Besides these architectures, it is also physically implemented an architecture for a deblocking filter module and architectures for motion compensation according the Main and High profiles. This master thesis presents the standard-cells (ASIC) implementation as well as a detailed description of each step necessary to outcome the layouts of each of the architecture. It also presents the results of the implementations and comparisons with other works in the literature. The implementation of the filter has 43.9K gates (equivalent-gates), 42mW of power consumption and it demands the least amount of internal memory, 12.375KB SRAM, when compared with other implementations for the same video resolution, 1920x1080@30fps. The implementations for the Main and High profiles of the motion compensator have the best relationship between the amount of required clock cycles to interpolate a macroblock (MB), 304 cycles/MB, and the equivalent-gate count of each implementation, 98K and 102K, respectively. Also, the implementation of the H.264 intra-only decoder has 5KB SRAM, 11.4 mW of power consumption and it has the least equivalent-gate count, 150K, compared with other implementations of H.264 decoders which have similar features.

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Thiele, Cristiano. "Desenvolvimento da arquitetura dos codificadores de entropia adaptativos CAVLC e CABAC do padrão H.264/AVC". reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2012. http://hdl.handle.net/10183/85463.

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Abstract (sommario):

Um codificador de entropia é responsável pela representação simbólica de dados de forma a representá-los com um menor número de bits. O H.264/AVC possui três codificadores de entropia: o Exponencial Golomb, o CAVLC que é o codificador de menor complexidade porém com um throughput maior de dados e o CABAC, com maior complexidade e com uma maior capacidade de compressão. A complexidade do codificador de entropia e a dependência dos dados sequenciais no bitstream original são os principais desafios para atender os requisitos de desempenho para compressão em tempo real. Por isso o desenvolvimento destas arquiteturas em hardware dedicado se faz necessário. Neste contexto, esta dissertação descreve os algoritmos que fazem parte da entropia do padrão H.264/AVC e as arquiteturas para estes codificadores entrópicos (Exponential Golomb, CAVLC e CABAC), além de uma arquitetura de hardware dedicada que integra todos estes a um montador final que atende às especificações da norma H.264/AVC. As arquiteturas foram escritas em VHDL e sintetizadas para dispositivos integrados FPGA. Em um dispositivo Virtex-5, este codificador de entropia completo suporta codificação de vídeos no nível 4.2 do padrão H.264/AVC (Full HD a 60 quadros por segundo). Esta arquitetura é a que apresenta o melhor desempenho de processamento dentre os melhores trabalhos relacionados, além de ser um codificador com todas as alternativas de codificação de entropia requeridas pela norma implementadas em um mesmo módulo.
An entropy encoder is responsible for the symbolic representation of a data stream so that the final representation contains less bits than the original. The H.264/AVC has three entropy coding schemes: the Exponential Golomb, the CAVLC encoder, that is less complex but with a higher data throughput, and the CABAC that is more complex while allowing for higher compression capability. The complexity of the entropy encoding and data dependencies on the original bitstream are the main challenges to meet the performance requirements for real-time compression. The development of these architectures in dedicated hardware is therefore necessary for high performance encoders. In this context, this work describes the algorithms that are part of the entropy encoders of the H.264/AVC standard, and the corresponding entropy coding architectures (Exponential Golomb, CAVLC and CABAC), plus a dedicated hardware architecture that integrates all of these encoders to a final bitstream assembler that is compliant to the aforementioned standard. The architectures were written in VHDL and synthesized into FPGA devices. In a Virtex-5 device, this full entropy encoder supports video encoding at level 4.2 of the H.264/AVC standard (Full HD at 60 frames per second). The developed architecture performs best among the most recent related architectures published, and has the unique feature of an encoder that implements in the same module all the alternative entropy encoders present in this standard for video compression.

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Più fonti

Libri sul tema "H.264/AVC video compression"

M, Le Thinh, Lian Yong e SpringerLink (Online service), a cura di. Entropy Coders of the H.264/AVC Standard: Algorithms and VLSI Architectures. Berlin, Heidelberg: Springer-Verlag Berlin Heidelberg, 2011.

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Richardson, Iain E. G. The H.264 advanced video compression standard. 2^a ed. Hoboken, N.J: Wiley, 2010.

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Richardson, Iain E. The H.264 Advanced Video Compression Standard. Chichester, UK: John Wiley & Sons, Ltd, 2010. http://dx.doi.org/10.1002/9780470989418.

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G, Richardson Iain E., a cura di. The H.264 advanced video compression standard. 2^a ed. Hoboken, N.J: Wiley, 2010.

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H.264 and MPEG-4 video compression: Video coding for next generation multimedia. Chichester: Wiley, 2003.

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Lee, Jae-Beom, e Hari Kalva. The VC-1 and H.264 Video Compression Standards for Broadband Video Services. Boston, MA: Springer US, 2008. http://dx.doi.org/10.1007/978-0-387-71043-3.

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Bernd, Girod, a cura di. Video coding with superimposed motion-compensated signals: Applications to H.264 and beyond. New York: Springer, 2011.

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Bernd, Girod, a cura di. Video coding with superimposed motion-compensated signals: Applications to H.264 and beyond. Boston: Kluwer Academic Publishers, 2004.

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Flierl, Markus. Video coding with superimposed motion-compensated signals: Applications to H.264 and beyond. Boston: Kluwer Academic Publishers, 2004.

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Hanzo, Lajos. Video compression and communications: From basics to H.261, H.263, H.264, MPEG2, MPEG4 for DVB and HSDPA-style adaptive turbo-transceivers. 2^a ed. Hoboken, NJ: J. Wiley & Sons, 2007.

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Capitoli di libri sul tema "H.264/AVC video compression"

Tian, Xiaohua, Thinh M. Le e Yong Lian. "Introduction to Video Compression". In Entropy Coders of the H.264/AVC Standard, 3–27. Berlin, Heidelberg: Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-14703-6_1.

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Karwowski, Damian. "Improved Adaptive Arithmetic Coding in MPEG-4 AVC/H.264 Video Compression Standard". In Advances in Intelligent and Soft Computing, 257–63. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-23154-4_29.

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Domański, Marek, Krzysztof Klimaszewski, Olgierd Stankiewicz, Jakub Stankowski e Krzysztof Wegner. "Efficient Transmission of 3D Video Using MPEG-4 AVC/H.264 Compression Technology". In Lecture Notes in Computer Science, 145–56. Berlin, Heidelberg: Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-13789-1_14.

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Lin, Youn-Long Steve, Chao-Yang Kao, Huang-Chih Kuo e Jian-Wen Chen. "Introduction to Video Coding and H.264/AVC". In VLSI Design for Video Coding, 1–9. Boston, MA: Springer US, 2009. http://dx.doi.org/10.1007/978-1-4419-0959-6_1.

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Lee, Kun-Bin. "Video Coding Using the H.264/AVC Standard". In Mobile Multimedia Broadcasting Standards, 435–60. Boston, MA: Springer US, 2009. http://dx.doi.org/10.1007/978-0-387-78263-8_15.

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Grois, Dan, Evgeny Kaminsky e Ofer Hadar. "Optimization Methods for H.264/AVC Video Coding". In The Handbook of MPEG Applications, 175–204. Chichester, UK: John Wiley & Sons, Ltd, 2010. http://dx.doi.org/10.1002/9780470974582.ch7.

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Tanwir, Savera, e Harry Perros. "Evaluation of Video Traffic Models for H.264 AVC Video". In VBR Video Traffic Models, 65–96. Chichester, UK: John Wiley & Sons, Ltd, 2014. http://dx.doi.org/10.1002/9781118931066.ch3.

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Spinsante, Susanna, Ennio Gambi e Damiano Falcone. "H.264/AVC Error Concealment for DVB-H Video Transmission". In Mobile Multimedia Broadcasting Standards, 461–84. Boston, MA: Springer US, 2009. http://dx.doi.org/10.1007/978-0-387-78263-8_16.

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Elarabi, Tarek, Ahmed Abdelgawad e Magdy Bayoumi. "Efficient MPEG-2 to H.264/AVC Transcoding". In Real-Time Heterogeneous Video Transcoding for Low-Power Applications, 23–34. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-06071-2_3.

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Lee, Joo-Kyong, e Ki-Dong Chung. "DCT Block Conversion for H.264/AVC Video Transcoding". In Euro-Par 2005 Parallel Processing, 919–27. Berlin, Heidelberg: Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/11549468_100.

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Atti di convegni sul tema "H.264/AVC video compression"

Martinian, Emin, Alexander Behrens, Jun Xin, Anthony Vetro e Huifang Sun. "Extensions of H.264/AVC for Multiview Video Compression". In 2006 International Conference on Image Processing. IEEE, 2006. http://dx.doi.org/10.1109/icip.2006.312963.

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Selvakumar, R. K., Krishnan Nallaperumal e A. Punithavathy. "Compound video image compression for H.264/AVC-INTRA". In 2008 International Conference on Computing, Communication and Networking (ICCCN). IEEE, 2008. http://dx.doi.org/10.1109/icccnet.2008.4787720.

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Agostini, Luciano, e Sergio Bampi. "FPGA Based Architectures for H. 264/AVC Video Compression Standard". In 2006 International Conference on Field Programmable Logic and Applications. IEEE, 2006. http://dx.doi.org/10.1109/fpl.2006.311361.

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Sheng, Kang, Xinyi Liao, Quanxin Zhang, Jiaqing Qu e Yu'an Tan. "Video Forensic of Fragmented Video Based on H.264/AVC Video Compression Standard". In 2014 International Conference on Mechatronics, Electronic, Industrial and Control Engineering. Paris, France: Atlantis Press, 2014. http://dx.doi.org/10.2991/meic-14.2014.111.

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Tung-Chien Chen, Yu-Han Chen, Ke-Chung Wu e Liang-Gee Chen. "Hybrid-mode embedded compression for H.264/AVC video coding system". In 2005 International Symposium on Intelligent Signal Processing and Communication Systems. IEEE, 2005. http://dx.doi.org/10.1109/ispacs.2005.1595395.

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Kamisli, Fatih, e Jae S. Lim. "Video compression with 1-D directional transforms in H.264/AVC". In 2010 IEEE International Conference on Acoustics, Speech and Signal Processing. IEEE, 2010. http://dx.doi.org/10.1109/icassp.2010.5495034.

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Chao, Jianshu, e Eckehard Steinbach. "SIFT feature-preserving bit allocation for H.264/AVC video compression". In 2012 19th IEEE International Conference on Image Processing (ICIP 2012). IEEE, 2012. http://dx.doi.org/10.1109/icip.2012.6466958.

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Diaz-Honrubia, Antonio J., Jose Luis Martinez, Pedro Cuenca e Hari Kalva. "A Fast Splitting Algorithm for an H.264/AVC to HEVC Intra Video Transcoder". In 2016 Data Compression Conference (DCC). IEEE, 2016. http://dx.doi.org/10.1109/dcc.2016.120.

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Poppe, C., S. De Bruyne, P. Lambert e R. Van de Walle. "Effect of H.264/AVC compression on object detection for video surveillance". In 2009 10th Workshop on Image Analysis for Multimedia Interactive Services (WIAMIS). IEEE, 2009. http://dx.doi.org/10.1109/wiamis.2009.5031449.

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Chen, Tzung-Her, Yan-Ting Wu e Yue-Rong Lin. "Medical Video Encryption Based on H.264/AVC with Near-Lossless Compression". In 2009 Fifth International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP). IEEE, 2009. http://dx.doi.org/10.1109/iih-msp.2009.139.

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