Tesi: "H.264/AVC video compression"

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Kannangara, Chaminda Sampath. "Complexity management of H.264/AVC video compression". Thesis, Robert Gordon University, 2006. http://hdl.handle.net/10059/643.

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The H. 264/AVC video coding standard offers significantly improved compression efficiency and flexibility compared to previous standards. However, the high computational complexity of H. 264/AVC is a problem for codecs running on low-power hand held devices and general purpose computers. This thesis presents new techniques to reduce, control and manage the computational complexity of an H. 264/AVC codec. A new complexity reduction algorithm for H. 264/AVC is developed. This algorithm predicts "skipped" macroblocks prior to motion estimation by estimating a Lagrange ratedistortion cost function. Complexity savings are achieved by not processing the macroblocks that are predicted as "skipped". The Lagrange multiplier is adaptively modelled as a function of the quantisation parameter and video sequence statistics. Simulation results show that this algorithm achieves significant complexity savings with a negligible loss in rate-distortion performance. The complexity reduction algorithm is further developed to achieve complexity-scalable control of the encoding process. The Lagrangian cost estimation is extended to incorporate computational complexity. A target level of complexity is maintained by using a feedback algorithm to update the Lagrange multiplier associated with complexity. Results indicate that scalable complexity control of the encoding process can be achieved whilst maintaining near optimal complexity-rate-distortion performance. A complexity management framework is proposed for maximising the perceptual quality of coded video in a real-time processing-power constrained environment. A real-time frame-level control algorithm and a per-frame complexity control algorithm are combined in order to manage the encoding process such that a high frame rate is maintained without significantly losing frame quality. Subjective evaluations show that the managed complexity approach results in higher perceptual quality compared to a reference encoder that drops frames in computationally constrained situations. These novel algorithms are likely to be useful in implementing real-time H. 264/AVC standard encoders in computationally constrained environments such as low-power mobile devices and general purpose computers.

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2

Bahari, Asral. "Low power architectures for MPEG-4 AVC/H.264 video compression". Thesis, University of Edinburgh, 2008. http://hdl.handle.net/1842/10695.

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Multimedia communication will be an important application in future wireless communication. The second-generation mobile communication systems already support basic multimedia services such as voice, text-messaging services and still-imaging communication. However, next generation wireless communication technology combined with advances in integrated circuit design and process fabrication technology will allow more data to be processed and transmitted through wireless channels. This will lift the current barriers and enable more demanding multimedia applications such as video telephony, video conferencing and video streaming. Video compression plays an important role in today's wireless communications. It allows raw video data to be compressed before it is sent through a wireless channel. However, video compression is compute-intensive and dissipates a significant amount of power. This is a major limitation in today's portable devices. Existing multimedia devices can only play video applications for a short time before the battery is depleted. This limits the user's entertainment experience and becomes a major bottleneck for the development of more attractive applications. The focus of this thesis is to design a low power video compression system for wireless communication. in this thesis, we propose techniques to minimise the power consumption at the algorithmic and architectural level. The low power is achieved by minimising the switching power between interacting modules that contribute to major the power consumption in H.264 standard. Motion estimation (ME) has been identified as the main bottleneck in MPEG video compression, including in the H.264 system where it takes up to 90% of the coding time. To reduce the power consumption in motion estimation hardware architecture, we have proposed a two-step algorithm that minimises the memory bandwidth and computational load of the ME. In this technique, the search is performed in low resolution mode at the first stage followed by high resolution mode in the second stage. This method reduces the total computation and memory access compared to the conventional method without significantly degrading the picture quality. The simulation results show that the proposed method gives good PSNR as compared to the conventional full search with PSNR drop < 0.5dB. An energy efficient hardware for implementing the proposed two-step method is suggested. The architecture is able to perform both low resolution and high resolution searches without significantly increasing the area overhead. With a unique pixel arrangement, the proposed method is able to perform at both low resolution and high resolution while still being able In to reduce the memory bandwidth. The results show that the proposed architecture is able to save up to 53% energy as compared to the conventional full search architecture.

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Brown, Michelle M. "Hardware study on the H.264/AVC video stream parser /". Online version of thesis, 2008. http://hdl.handle.net/1850/7766.

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4

Adams, Tanner Ryan. "Computationally Efficient Basic Unit Rate Control for H.264/AVC". University of Dayton / OhioLINK, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1386097674.

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5

Ramos, Fabio Luis Livi. "Arquitetura para o algoritmo CAVLC de codificação de entropia segundo o padrão H.264/AVC". reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2010. http://hdl.handle.net/10183/31120.

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A codificação de vídeo digital depende de uma série de etapas para ser alcançada a compressão de dados necessária para, então, o vídeo ser enviado ou armazenado em um meio. Existe uma série de padrões que se propõe a isso e dentre eles, o que apresenta o melhor desempenho em termos de compressão de dados e qualidade de vídeo até o presente momento é o H.264/AVC. Considerando então o padrão H.264/AVC, uma das etapas do seu processamento é a codificação de entropia, sendo que um dos algoritmos usados para esse fim é o CAVLC (Context-Based Adaptive Variable Length Coding). Esta técnica faz uso de uma série de características onde o código gerado pela seqüência de vídeo processada tende a assumir, para, então, gerar códigos menores para padrões do vídeo que tendem a aparecer mais freqüentemente em detrimento a padrões que são mais raros, fazendo para isso uso de código de comprimento variável que depende do contexto atual em que cada porção do código está sendo processada. Baseado nisso, este trabalho apresenta uma arquitetura para o algoritmo CAVLC segundo o padrão H.264/AVC, onde foi inserida uma nova técnica para diminuir o gargalo na etapa inicial do algoritmo, além de usar técnicas já conhecidas na literatura para diminuir os ciclos necessários para o processamento do componente, fazendo com que a arquitetura aqui apresentada tenha um ganho em relação aos demais trabalhos da literatura encontrados e comparados. Esse trabalho está inserido no esforço do grupo de TV Digital da UFRGS e pretende-se que, no futuro, esse módulo seja integrado aos demais módulos desenvolvidos no grupo para formar um codificador H.264/AVC completo.
The digital video encoding depends on different phases to reach the necessary data compression, so the video can be transmitted through or stored in the medium. There are a variety of compression standards that are designed to that purpose and, among them, the one that has the best performance currently is the H.264/AVC. Considering the H.264/AVC standard, one of the processing stages is the entropy encoding. CAVLC (Context-Based Adaptive Variable Length Coding) is one of the algorithms that can be used for that end. It can use many of the code particularities, generated by the video sequence being processed. This way, CAVLC can generate codes with less bits for portions of the video sequence that occur more often, and codes with more bits for rarer patterns of the video sequence, using variable code lengths that depend on the current context for each portion of the code being processed. Based on this, the present work presents a VLSI hardware architecture for the CAVLC algorithm, according to the H.264/AVC standard. The architecture introduces a new technique to decrease the bottleneck at the initial stage of the algorithm and, furthermore, well-known techniques already tested in works found in the literature, were also implemented, to save processing cycles at the other stages of the component. The present architecture is then able to achieve gains compared to the other works found in the literature. This work is inserted into the effort of the Digital TV Group at UFRGS and it is intended to be integrated with the others developed by the group to make a complete H.264/AVC encoder.

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Ernst, Eric Gerard. "Architecture design of a scalable adaptive deblocking filter for H.264/AVC /". Online version of thesis, 2007. http://hdl.handle.net/1850/5390.

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7

Porto, Roger Endrigo Carvalho. "Desenvolvimento arquitetural para estimação de movimento de blocos de tamanhos variáveis segundo padrão H.264/AVC de compressão de vídeo digital". reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2008. http://hdl.handle.net/10183/17348.

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Apesar de as capacidades de transmissão e de armazenamento dos dispositivos continuarem crescendo, a compressão ainda é essencial em aplicações que trabalham com vídeo. Com a compressão reduz-se significativamente a quantidade de bits necessários para se representar uma seqüência de vídeo. Dentre os padrões de compressão de vídeo digital, o mais novo é o H.264/AVC. Este padrão alcança as mais elevadas taxas de compressão se comparado com os padrões anteriores mas, por outro lado, possui uma elevada complexidade computacional. A complexidade computacional elevada dificulta o desenvolvimento em software de aplicações voltadas a definições elevadas de imagem, considerando a tecnologia atual. Assim, tornam-se indispensáveis implementações em hardware. Neste escopo, este trabalho aborda o desenvolvimento de uma arquitetura para estimação de movimento de blocos de tamanhos variáveis segundo o padrão H.264/AVC de compressão de vídeo digital. Esta arquitetura utiliza o algoritmo full search e SAD como critério de similaridade. Além disso, a arquitetura é capaz de gerar os 41 diferentes vetores de movimento referentes a um macrobloco e definidos pelo padrão. A solução arquitetural proposta neste trabalho foi descrita em VHDL e mapeada para FPGAs da Xilinx. Também foi desenvolvida uma versão standard cell da arquitetura. Considerando-se as versões da arquitetura com síntese direcionada para FPGA, os resultados mostraram que a arquitetura pode ser utilizada em aplicações voltadas para alta definição como SDTV ou HDTV. Para a versão standard cells da arquitetura os resultados indicam que ela pode ser utilizada para aplicações SDTV.
The transmission and storage capabilities of the digital communications and processing continue to grow. However, compression is still necessary in video applications. With compression, the amount of bits necessary to represent a video sequence is dramatically reduced. Amongst the video compression standards, the latest one is the H.264/AVC. This standard reaches the highest compression rates when compared to the previous standards. On the other hand, it has a high computational complexity. This high computational complexity makes it difficult the development of applications targeting high definitions when a software implementation running in a current technology is considered. Thus, hardware implementations become essential. Addressing the hardware architectures, this work presents the architectural design for the variable block-size motion estimation defined in the H.264/AVC standard. This architecture is based on full search motion estimation algorithm and SAD calculation. This architecture is able to produce the 41 motion vectors within a macroblock that are specified in the standard. The architecture designed in this work was described in VHDL and it was mapped to Xilinx FPGAs. Extensive simulations of the hardware architecture and comparisons to the software implementation of the same variable-size algorithm were used to validate the architecture. It was also synthesized to standard cells. Considering the synthesis results, the architecture reaches real time for high resolution videos, as HDTV when mapped to FPGAs. The standard cells version of this architecture is able to reach real time for SDTV resolution, considering a physical synthesis to 0.18µm CMOS.

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Depra, Dieison Antonello. "Algoritmos e desenvolvimento de arquitetura para codificação binária adaptativa ao contexto para o decodificador H.264/AVC". reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2009. http://hdl.handle.net/10183/26505.

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As inovações tecnológicas têm propiciado transformações nas formas de interação e, principalmente, na comunicação entre as pessoas. Os avanços nas áreas de tecnologia da informação e comunicações abriram novos horizontes para a criação de demandas até então não existentes. Nesse contexto, a utilização de vídeo digital de alta definição para aplicações de tempo real ganha ênfase. Entretanto, os desafios envolvidos na manipulação da quantidade de informações necessárias à sua representação, fomentam pesquisas na indústria e na academia para minimizar os impactos sobre a largura de banda necessária para transmissão e/ou no espaço para o seu armazenamento. Para enfrentar esses problemas diversos padrões de compressão de vídeo têm sido desenvolvidos sendo que, nesse aspecto, o padrão H.264/AVC é considerado o estado da arte. O padrão H.264/AVC introduz ganhos significativos na taxa de compressão, em relação a seus antecessores, porém esses ganhos vêem acompanhados pelo aumento na complexidade computacional das ferramentas aplicadas como, por exemplo, a Codificação Aritmética Binária Adaptativa ao Contexto (CABAC). A complexidade computacional relacionado ao padrão H.264/AVC é tal que torna impraticável sua execução em software (para operar em um processador de propósito geral, ao menos para nos disponíveis atuais) com a finalidade de realizar a codificação ou decodificação em tempo real para sequências de vídeo de alta definição. Esta dissertação apresenta uma arquitetura de hardware para o processo de decodificação do CABAC, conforme especificação do padrão H.264/AVC. Tendo o objetivo de contribuir para a resolução de alguns dos problemas relacionados à tarefa de decodificação de vídeo de alta definição em tempo real. Para isso, apresenta-se uma introdução sobre conceitos fundamentais da compressão de dados e vídeo digital, além da discussão sobre as principais características do padrão H.264/AVC. O conjunto de algoritmos presentes no CABAC e o fluxo de decodificação do CABAC são descritos em detalhes. Para fundamentar as decisões de projeto um vasto conjunto de experimentos foi realizado para analisar o comportamento do bitstream durante o processo de decodificação do CABAC. A arquitetura de hardware proposta e desenvolvida é apresentada em detalhes, tendo seu desempenho comparado com outras propostas encontradas na literatura. Os resultados obtidos mostram que a arquitetura desenvolvida é eficaz em seu objetivo, pois atinge a capacidade de processamento de vídeos em alta definição (HD1080p) em tempo real. Além disso, os experimentos realizados deram origem a observações inovadoras, que permitiram determinar os pontos chave para minimizar os gargalos inerentes ao conjunto de algoritmos que compõe o CABAC.
The technological innovations of recent decades have brought changes in the forms of human interaction especially in communication area. Advances in the areas of information technology and communications opened new horizons for creating demands non-existent so far. In this scenario the high-definition digital video for real-time applications has gained emphasis for this context. However, the challenges involved in handling the amount of information necessary for its representation, promoting research in industry and academia to minimize the impact on the bandwidth needed for transmission and / or the space for the storage. To address those problems several video compression standards have been developed and the H.264/AVC standard is the state-of-the-art. The H.264/AVC standard introduces significant gains in compression rate, compared to its predecessors. These gains are obtained by an increase in computational complexity of the techniques used, such as the CABAC. The computational requirements of H.264/AVC standard is so strong that make its implementation impractical in software (to operate on a general purpose processor) for the purpose of performing encoding or decoding in real time for high-definition video sequences. This dissertation presents a new CABAD architecture with the implementation in hardware intended to solve the problems related to the task of decoding high-definition video in real time. An introduction to fundamental concepts of data compression and digital video is presented, in addition to discussing the main features of the H.264/AVC standard. The set of algorithms the CABAC and of the CABAD decode flow are described in detail. A wide number of experiments were conducted to identify the static and dynamic behavior of the bitstream to support the design decisions. At the end the developed architecture is examined and compared with other proposals found in literature. The results show that the architecture developed is effective in its purpose to handle high-definition video (HD1080p) in real time. Furthermore, the experiments have led to innovative observations to determine the key points to minimize the bottlenecks inherent in the set of algorithms that make the CABAD.

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Silva, Leandro Max de Lima. "Implementação física de arquiteturas de hardware para a decodificação de vídeo digital segundo o padrão H.264/AVC". reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2010. http://hdl.handle.net/10183/27655.

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Recentemente, o Brasil adotou o padrão SBTVD (Sistema Brasileiro de TV Digital) para transmissão de TV digital. Este utiliza o CODEC (codificador e decodificador) de vídeo H.264/AVC, que é considerado o estado-da-arte no contexto de compressão de vídeo digital. Esta transição para o SBTVD requer o desenvolvimento de tecnologia para transmissão, recepção e decodificação de sinais, assim, o projeto Rede H.264 SBTVD foi iniciado e tem como um dos objetivos a produção de componentes de hardware para construção de um set-top box SoC (System on Chip) compatível com o SBTVD. No sentido de produzir IPs (Intellectual Property) para codificação e decodificação de vídeo digital segundo o padrão H.264/AVC, várias arquiteturas de hardware vêm sendo desenvolvidas no âmbito do projeto. Assim, o objetivo deste trabalho consiste na realização da implementação física em ASIC (Application-Specific Integrated Circuit) de algumas destas arquiteturas de hardware para decodificação de vídeo H.264/AVC, entre elas as arquiteturas parser e decodificação de entropia, predição intra-quadro e, por fim, quantização e transformadas inversas, que juntas formam uma versão funcional de um decodificador de vídeo H.264 chamado de decodificador intra-only. Além destas, também foi fisicamente implementada uma arquitetura para o módulo filtro redutor de efeito de bloco e arquiteturas para os perfis Main e High de um compensador de movimentos. Nesta dissertação de mestrado, é apresentada a metodologia de implementação standard-cells (ASIC) utilizada, assim como uma descrição detalhada de cada passo executado para se chegar ao leiaute de cada uma das arquiteturas. Também são apresentados os resultados das implementações e realizadas algumas comparações com outras implementações de arquiteturas descritas na literatura. A implementação do filtro possui 43,9K portas lógicas (equivalent-gates), 42mW de potência e possui a menor quantidade de memória interna, 12,375KB SRAM, quando comparada com outras implementações para a mesma resolução de vídeo, 1920x1080@30fps. As implementações para os perfis Main e High do compensador de movimento apresentam a melhor relação entre a quantidade de ciclos de relógio necessária para interpolar um macrobloco (MB), 304 ciclos/MB, e a quantidade de equivalent-gates de cada implementação, 98K e 102K, respectivamente. Já a implementação do decodificador H.264 intra-only possui 5KB SRAM, 11,4mW de potência e apresenta a menor quantidade de equivalent-gates, 150K, comparado com outras implementações de decodificadores H.264 com características similares.
Recently Brazil has adopted the SBTVD (Brazilian Digital Television System) for digital TV transmission. It uses the H.264/AVC video CODEC (coder and decoder), which is considered the state of the art in the context of digital video compression. This transition to the SBTVD standard requires the development of technology for transmitting, receiving and decoding signals, so a project called Rede H.264 was initiated with the objective of producing cutting edge hardware components to build a set-top box SoC (System on Chip) compatible with the SBTVD. In order to produce IPs (Intellectual Property) for encoding and decoding digital video according to the H.264/AVC standard, many hardware architectures have been developed under the project. Therefore, the objective of this work is to carry out the physical implementation flow for ASIC (Application-Specific Integrated Circuit) in some of these hardware architectures for H.264/AVC video decoding, including the architectures parser and entropy decoding, intra-prediction and inverse quantization and transforms, which together compound a working version of an H.264 video decoder called intra-only. Besides these architectures, it is also physically implemented an architecture for a deblocking filter module and architectures for motion compensation according the Main and High profiles. This master thesis presents the standard-cells (ASIC) implementation as well as a detailed description of each step necessary to outcome the layouts of each of the architecture. It also presents the results of the implementations and comparisons with other works in the literature. The implementation of the filter has 43.9K gates (equivalent-gates), 42mW of power consumption and it demands the least amount of internal memory, 12.375KB SRAM, when compared with other implementations for the same video resolution, 1920x1080@30fps. The implementations for the Main and High profiles of the motion compensator have the best relationship between the amount of required clock cycles to interpolate a macroblock (MB), 304 cycles/MB, and the equivalent-gate count of each implementation, 98K and 102K, respectively. Also, the implementation of the H.264 intra-only decoder has 5KB SRAM, 11.4 mW of power consumption and it has the least equivalent-gate count, 150K, compared with other implementations of H.264 decoders which have similar features.

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Thiele, Cristiano. "Desenvolvimento da arquitetura dos codificadores de entropia adaptativos CAVLC e CABAC do padrão H.264/AVC". reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2012. http://hdl.handle.net/10183/85463.

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Um codificador de entropia é responsável pela representação simbólica de dados de forma a representá-los com um menor número de bits. O H.264/AVC possui três codificadores de entropia: o Exponencial Golomb, o CAVLC que é o codificador de menor complexidade porém com um throughput maior de dados e o CABAC, com maior complexidade e com uma maior capacidade de compressão. A complexidade do codificador de entropia e a dependência dos dados sequenciais no bitstream original são os principais desafios para atender os requisitos de desempenho para compressão em tempo real. Por isso o desenvolvimento destas arquiteturas em hardware dedicado se faz necessário. Neste contexto, esta dissertação descreve os algoritmos que fazem parte da entropia do padrão H.264/AVC e as arquiteturas para estes codificadores entrópicos (Exponential Golomb, CAVLC e CABAC), além de uma arquitetura de hardware dedicada que integra todos estes a um montador final que atende às especificações da norma H.264/AVC. As arquiteturas foram escritas em VHDL e sintetizadas para dispositivos integrados FPGA. Em um dispositivo Virtex-5, este codificador de entropia completo suporta codificação de vídeos no nível 4.2 do padrão H.264/AVC (Full HD a 60 quadros por segundo). Esta arquitetura é a que apresenta o melhor desempenho de processamento dentre os melhores trabalhos relacionados, além de ser um codificador com todas as alternativas de codificação de entropia requeridas pela norma implementadas em um mesmo módulo.
An entropy encoder is responsible for the symbolic representation of a data stream so that the final representation contains less bits than the original. The H.264/AVC has three entropy coding schemes: the Exponential Golomb, the CAVLC encoder, that is less complex but with a higher data throughput, and the CABAC that is more complex while allowing for higher compression capability. The complexity of the entropy encoding and data dependencies on the original bitstream are the main challenges to meet the performance requirements for real-time compression. The development of these architectures in dedicated hardware is therefore necessary for high performance encoders. In this context, this work describes the algorithms that are part of the entropy encoders of the H.264/AVC standard, and the corresponding entropy coding architectures (Exponential Golomb, CAVLC and CABAC), plus a dedicated hardware architecture that integrates all of these encoders to a final bitstream assembler that is compliant to the aforementioned standard. The architectures were written in VHDL and synthesized into FPGA devices. In a Virtex-5 device, this full entropy encoder supports video encoding at level 4.2 of the H.264/AVC standard (Full HD at 60 frames per second). The developed architecture performs best among the most recent related architectures published, and has the unique feature of an encoder that implements in the same module all the alternative entropy encoders present in this standard for video compression.

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Baaklini, Elias Michel. "Optimisation des applications multimédia sur des processeurs multicœurs embarqués". Thesis, Valenciennes, 2014. http://www.theses.fr/2014VALE0004/document.

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L’utilisation de plusieurs cœurs pour l’exécution des applications mobiles sera l’approche dominante dans les systèmes embarqués pour les prochaines années. Cette approche permet en générale d’augmenter les performances du système sans augmenter la vitesse de l’horloge. Grâce à cela, la consommation d’énergie reste modérée. Toutefois, la concurrence entre les tâches doit être exploitée afin d’améliorer les performances du système dans les différentes situations où l’application peut s’exécuter. Les applications multimédias comme la vidéoconférence ou la vidéo haute définition, ont de nombreuses nouvelles fonctionnalités qui nécessitent des calculs complexes par rapport aux normes précédentes de codage vidéo. Ces applications créent une charge de travail très importante sur les systèmes multiprocesseurs. L’exploitation du parallélisme pour les applications multimédia, comme le codec vidéo H.264/AVC, peut se faire à différents niveaux : au niveau de données ou bien au niveau tâches. Dans le cadre de cette thèse de doctorat, nous proposons de nouvelles solutions pour une meilleure exploitation du parallélisme dans les applications multimédia sur des systèmes embarqués ayant une architecture parallèle symétrique (ou SMP pour Symmetric Multi-Processor). Des approches innovantes pour le décodeur H.264/AVC qui traitent des composantes de couleur et des blocs de l’image en parallèle sont proposées et expérimentées
Parallel computing is currently the dominating architecture in embedded systems. Concurrency improves the performance of the system rather without increasing the clock speed which affects the power consumption of the system. However, concurrency needs to be exploited in order to improve the system performance in different applications environments. Multimedia applications (real-Time conversational services such as video conferencing, video phone, etc.) have many new features that require complex computations compared to previous video coding standards. These applications have a challenging workload for future multiprocessors. Exploiting parallelism in multimedia applications can be done at data and functional levels or using different instruction sets and architectures. In this research, we design new parallel algorithms and mapping methodologies in order to exploit the natural existence of parallelism in multimedia applications, specifically the H.264/AVC video decoder. We mainly target symmetric shared-Memory multiprocessors (SMPs) for embedded devices such as ARM Cortex-A9 multicore chips. We evaluate our novel parallel algorithms of the H.264/AVC video decoder on different levels: memory load, energy consumption, and execution time

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Agostini, Luciano Volcan. "Desenvolvimento de Arquiteturas de Alto Desempenho dedicadas à compressão de vídeo segundo o Padrão H.264/AVC". reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2007. http://hdl.handle.net/10183/12425.

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Abstract (sommario):

A compressão de vídeo é essencial para aplicações que manipulam vídeos digitais, em função da enorme quantidade de informação necessária para representar um vídeo sem nenhum tipo de compressão. Esta tese apresenta o desenvolvimento de soluções arquiteturais dedicadas e de alto desempenho para a compressão de vídeos, com foco no padrão H.264/AVC. O padrão H.264/AVC é o mais novo padrão de compressão de vídeo da ITU-T e da ISO e atinge as mais elevadas taxas de compressão dentre todos os padrões de codificação de vídeo existentes. Este padrão também possui a maior complexidade computacional dentre os padrões atuais. Esta tese apresenta soluções arquiteturais para os módulos da estimação de movimento, da compensação de movimento, das transformadas diretas e inversas e da quantização direta e inversa. Inicialmente, são apresentados alguns conceitos básicos de compressão de vídeo e uma introdução ao padrão H.264/AVC, para embasar as explicações das soluções arquiteturais desenvolvidas. Então, as arquiteturas desenvolvidas para os módulos das transformadas diretas e inversas, da quantização direta e inversa, da estimação de movimento e da compensação de movimento são apresentadas. Todas as arquiteturas desenvolvidas foram descritas em VHDL e foram mapeadas para FPGAs Virtex-II Pro da Xilinx. Alguns dos módulos foram, também, sintetizados para standard-cells. Os resultados obtidos através da síntese destas arquiteturas são apresentados e discutidos. Para todos os casos, os resultados de síntese indicaram que as arquiteturas desenvolvidas estão aptas para atender as demandas de codecs H.264/AVC direcionados para vídeos de alta resolução.
Video coding is essential for applications based in digital videos, given the enormous amount of bits which are required to represent a video sequence without compression. This thesis presents the design of dedicated and high performance architectures for video compression, focusing in the H.264/AVC standard. The H.264/AVC standard is the latest ITU-T and ISO standard for video compression and it reaches the highest compression rates amongst all the current video coding standards. This standard has also the highest computational complexity among all of them. This thesis presents architectural solutions for the modules of motion estimation, motion compensation, forward and inverse transforms and forward and inverse quantization. Some concepts of video compression and an introduction to the H.264/AVC standard are presented and they serve as basis for the architectural developments. Then, the designed architectures for forward and inverse transforms, forward and inverse quantization, motion estimation and motion compensation are presented. All designed architectures were described in VHDL and they were mapped to Xilinx Virtex-II Pro FPGAs. Some modules were also synthesized into standard-cells. The synthesis results are presented and discussed. For all cases, the synthesis results indicated that the architectures developed in this work are able to meet the demands of H.264/AVC codecs targeting high resolution videos.

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Diniz, Claudio Machado. "Arquitetura de hardware dedicada para a predição intra-quadro em codificadores do padrão H.264/AVC de compressão de vídeo". reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2009. http://hdl.handle.net/10183/17801.

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Abstract (sommario):

A compressão de vídeo é essencial para aplicações de vídeo digital. Devido ao elevado volume de informações contidas em um vídeo digital, um processo de compressão é aplicado antes de ser armazenado ou transmitido. O padrão H.264/AVC é considerado o estado-da-arte em termos de compressão de vídeo, introduzindo um conjunto de ferramentas inovadoras em relação a padrões anteriores. Tais ferramentas possibilitam um ganho significativo em compressão, ao preço de um aumento na complexidade. A predição intra-quadro é uma das ferramentas inovadoras do padrão H.264/AVC, responsável por reduzir a redundância espacial do vídeo utilizando informações contidas em um único quadro para predição. A predição intra-quadro do H.264/AVC possibilita ganhos de compressão em comparação com os mais usados padrões de compressão de imagens estáticas, o JPEG e JPEG 2000, mas introduz complexidade no projeto do codificador de vídeo, especialmente quando se torna necessário atingir o desempenho para codificar vídeos de alta definição em tempo-real. Neste contexto, a presente dissertação apresenta a proposta e o desenvolvimento de uma arquitetura de hardware dedicada para a predição intra-quadro, presente nos codificadores compatíveis com o padrão H.264/AVC de compressão de vídeo. A arquitetura desenvolvida codifica vídeos de alta definição em tempo-real utilizando uma frequência de operação 46% menor que o melhor trabalho encontrado na literatura. A arquitetura desenvolvida será integrada, futuramente, em um codificador de vídeo em hardware compatível com o padrão H.264/AVC no perfil Main.
Video coding is essential in digital video applications, due to the extremely high data volume present in a digital video to be stored or transmitted through a physical link. H.264/AVC is the state-of-the-art video coding standard, introducing a set of novel features when compared to former standards. A significant gain in terms of bit-rate has been obtained but the increase of complexity of the codec when compared to other video coding standard is inevitable. Intra-frame Prediction is a novel feature introduced with H.264/AVC, which is responsible for reducing a video spatial redundancy using only information in the same frame for prediction. H.264/AVC intra-frame prediction can provide compression gains when compared with state-of-art still image coding standards, like JPEG and JPEG 2000, but introduces complexity and latency to video encoder design, mainly when high definition video coding is needed. In this context, this thesis presents the proposal and development of an intra-frame prediction dedicated hardware architecture for H.264/AVC compatible video encoder. The developed architecture achieved the performance to encode high definition video in real-time with 46% reduction in clock frequency compared with the best results found in the literature. In the future, the developed architecture can be integrated to a fully compatible H.264/AVC main profile hardware encoder.

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Dubois, Loïc. "Protection de vidéo comprimée par chiffrement sélectif réduit". Thesis, Montpellier 2, 2013. http://www.theses.fr/2013MON20169/document.

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De nos jours, les vidéos et les images sont devenues un moyen de communication très important. L'acquisition, la transmission, l'archivage et la visualisation de ces données visuelles, que ce soit à titre professionnel ou privé, augmentent de manière exponentielle. En conséquence, la confidentialité de ces contenus est devenue un problème majeur. Pour répondre à ce problème, le chiffrement sélectif est une solution qui assure la confidentialité visuelle des données en ne chiffrant qu'une partie des données. Le chiffrement sélectif permet de conserver le débit initial et de rester conforme aux standards vidéo. Ces travaux de thèse proposent plusieurs méthodes de chiffrement sélectif pour le standard vidéo H.264/AVC. Des méthodes de réduction du chiffrement sélectif grâce à l'architecture du standard H.264/AVC sont étudiées afin de trouver le ratio de chiffrement minimum mais suffisant pour assurer la confidentialité visuelle des données. Les mesures de qualité objectives sont utilisées pour évaluer la confidentialité visuelle des vidéos chiffrées. De plus, une nouvelle mesure de qualité est proposée pour analyser le scintillement des vidéos au cours du temps. Enfin, une méthode de chiffrement sélectif réduit régulé par des mesures de qualité est étudiée afin d'adapter le chiffrement en fonction de la confidentialité visuelle fixée
Nowadays, videos and images are major sources of communication for professional or personal purposes. Their number grow exponentially and the confidentiality of the content has become a major problem for their acquisition, transmission, storage, and display. In order to solve this problem, selective encryption is a solution which provides visual privacy by encrypting only a part of the data. Selective encryption preserves the initial bit-rate and maintains compliance with the syntax of the standard video. This Ph.D thesis offers several methods of selective encryption for H.264/AVC video standard. Reduced selective encryption methods, based on the H.264/AVC architecture, are studied in order to find the minimum ratio of encryption but sufficient to ensure visual privacy. Objective quality measures are used to assess the visual privacy of encrypted videos. In addition, a new quality measure is proposed to analyze the video flicker over time. Finally, a method for a reduced selective encryption regulated by quality measures is studied to adapt the encryption depending on the visual privacy fixed

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Martins, André Luis Del Mestre. "Projeto da arquitetura de hardware para binarização e modelagem de contextos para o CABAC do padrão de compressão de vídeo H.264/AVC". reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2011. http://hdl.handle.net/10183/28742.

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O codificador aritmético binário adaptativo ao contexto adotado (CABAC – Context-based Adaptive Binary Arithmetic Coding) pelo padrão H.264/AVC a partir de perfil Main é o estado-da-arte em termos de eficiência de taxa de bits. Entretanto, o CABAC ocupa 9.6% do tempo total de processamento e seu throughput é limitado pelas dependências de dados no nível de bit (LIN, 2010). Logo, atingir os requisitos de desempenho em tempo real nos níveis mais altos do padrão H.264/AVC se torna uma tarefa árdua em software, sendo necesário então, a aceleração do CABAC através de implementações em hardware. As arquiteturas de hardware encontradas na literatura para o CABAC focam no Codificador Aritmético Binário (BAE - Binary Arithmetic Encoder) enquanto que a Binarização e Modelagem de Contextos (BCM – Binarization and Context Modeling) fica em segundo plano ou nem é apresentada. O BCM e o BAE juntos constituem o CABAC. Esta dissertação descreve detalhadamente o conjunto de algoritmos que compõem o BCM do padrão H.264/AVC. Em seguida, o projeto de uma arquitetura de hardware específica para o BCM é apresentada. A solução proposta é descrita em VHDL e os resultados de síntese mostram que a arquitetura alcança desempenho suficiente, em FPGA e ASIC, para processar vídeos no nível 5 do padrão H.264/AVC. A arquitetura proposta é 13,3% mais rápida e igualmente eficiente em área que os melhores trabalhos relacionados nestes quesitos.
Context-based Adaptive Binary Arithmetic Coding (CABAC) adopted in the H.264/AVC main profile is the state-of-art in terms of bit-rate efficiency. However, CABAC takes 9.6% of the total encoding time and its throughput is limited by bit-level data dependency (LIN, 2010). Moreover, meeting real-time requirement for a pure software CABAC encoder is difficult at the highest levels of the H.264/AVC standard. Hence, speeding up the CABAC by hardware implementation is required. The CABAC hardware architectures found in the literature focus on the Binary Arithmetic Encoder (BAE), while the Binarization and Context Modeling (BCM) is a secondary issue or even absent in the literature. Integrated, the BCM and the BAE constitute the CABAC. This dissertation presents the set of algorithms that describe the BCM of the H.264/AVC standard. Then, a novel hardware architecture design for the BCM is presented. The proposed design is described in VHDL and the synthesis results show that the proposed architecture reaches sufficiently high performance in FPGA and ASIC to process videos in real-time at the level 5 of H.264/AVC standard. The proposed design is 13.3% faster than the best works in these items, while being equally efficient in area.

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Kthiri, Moez. "Étude et implantation d'algorithmes de compression vidéo optimisés H.264/AVC dans un environnement conjoint matériel et logiciel". Thesis, Bordeaux 1, 2012. http://www.theses.fr/2012BOR14505/document.

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La contribution de cette thèse concerne le développement et la conception d’un système multimédia embarqué basé sur l’approche de conception conjointe matérielle/logicielle (codesign). Il en résulte ainsi la constitution d’une bibliothèque de modules IP (Intellectual Property) pour les applications vidéo. Dans ce contexte, une plateforme matérielle de validation a été réalisée servant au préalable à l’évaluation de l’approche de conception en codesign pour l’étude d’algorithmes de traitement vidéo. Nous nous sommes ainsi intéressés en particulier à l’étude et à l’implantation de la norme de décompression vidéo H.264/AVC. Pour la validation fonctionnelle, l’ensemble du développement a été réalisé autour d’une carte Xilinx à base d’un circuit programmable FPGA Xilinx Virtex-5en mettant en œuvre le processeur hardcore PowerPC du circuit programmable dans l’environnement logiciel Linux pour l’embarqué. Le décodeur H.264/AVC ainsi développé comporte différents accélérateurs matériels pour la transformation inverse ainsi que le filtre anti-blocs. Nous avons pu tester les performances au regard du respect des contraintes temporelles en intégrant une extension temps réel à la plateforme de validation suivant différentes conditions de stress du système. L’extension temps réel Xenomai fournit ainsi une réponse adéquate aux problématiques de charge du système et de maîtrise des contraintes temporelles inhérentes à tout système de traitement vidéo tout en autorisant aussi l’utilisation d’applications classiques mises en œuvre dans l’environnement standard Linux embarqué
The main contribution of this thesis concerns the development and the design of an embedded system for multimedia based on the codesign approach (HW/SW). Towards this end, a library off lexible IP cores (Intellectual Property) for video applications was created. In this context, a hardware platform was used for evaluation of the codesign-based approach in order to study video processingalgorithms. Thus, we particularly focused on the study and the implementation of H.264/AVC decoder. For functional validation, the entire development was carried out around a FPGA Virtex-5 Xilinx board embedding a hardcore PowerPC processor running embedded Linux operating system. The H.264/AVC developed decoder consists of hardware accelerators for the inverse transformation and the deblocking filter. We evaluated the performances in terms of respect of temporal constraints by integrating a real-time extension to the validation platform under different stress conditions. The Xenomai real-time extension has proven its high performance level of compliance with hard real-time constraints. This extension offers a real solution for real-time behavior without limiting the use of conventional applications implemented traditionally in a time sharing environment

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Bergeron, Cyril. "Optimisation conjointe source/canal d'une transmission vidéo H. 264/AVC sur lien sans fil". Paris, ENST, 2007. https://pastel.hal.science/pastel-00004234.

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Dans le domaine des transmissions de données multimédia, de remarquables progrès ont été fait au cours des vingt dernières années permettant d'optimiser chaque module d'une chaîne de communication moderne. Mais en dépit de ces excellents résultats, une approche cloisonnée ou "séparée" a montré ses limites dans le cas des communications sans fil. Notre approche, qui suit celle du codage source/canal conjoint, a pour objectif de développer des stratégies où le codage de source et le codage canal sont déterminés conjointement tout en prenant en compte les paramètres du réseau et d'éventuelles contraintes utilisateurs. Cette approche offre la possibilité de faire converser le monde de l'application (codage source, chiffrement) et le monde des transmissions (codage canal) afin qu'ils optimisent conjointement l'usage du lien de communications sans fil de bout en bout. Trois axes de recherche sont traités dans ce mémoire de thèse qui permettent d'optimiser l'allocation des ressources de l'utilisateur et du réseau appliquée tout en assurant une compatibilité avec la norme de codage vidéo H. 264. Tout d'abord, nous proposons d'utiliser la redondance résiduelle présente dans un flux binaire en sortie du codeur source afin d'améliorer les performances du décodage. Ensuite, nous introduisons une méthode proposant des propriétés de scalabilité temporelle compatible du standard H. 264. Enfin, nous présentons une méthode d'optimisation conjointe de la répartition de débit entre le codeur de source et le codeur de canal au moyen d'un contrôleur applicatif estimant la distorsion globale introduite par ces différents codeurs grâce au calcul de la sensibilité des flux binaires considérés.

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Deknudt, Christophe. "Mise en oeuvre d'architectures de transcodage vidéo H. 264/AVC et SVC : application à la transmission optimisée de la vidéo haute définition". Valenciennes, 2011. http://www.theses.fr/2011VALE0012.

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Les travaux présentés dans ce manuscrit de thèse se sont déroulés majoritairement dans le cadre du projet TOSCANE dont l’objectif était d’optimiser les transmissions de flux vidéo haute définition (HD). Pour cela, deux types d’architectures de transcodage à complexité réduite des flux H. 264/AVC sont proposés afin d’adapter le débit vidéo à la bande passante du canal de transmission. La première architecture s’applique aux flux H. 264/AVC et réalise une sélection fréquentielle des coefficients résiduels. Après comparaison en termes de réduction de débit et de qualité vidéo entre cette solution et celle par requantification, nous avons constaté que notre architecture donnait majoritairement de meilleurs résultats. Puis, cette solution est intégrée dans un scénario de transmission vidéo HD par courant porteur en ligne. Ce type de canal est soumis à des changements d’états fréquents nécessitant une nouvelle estimation du canal et allocation des bits et des puissances afin de garantir un débit quasiment sans erreur. Au prix d’une légère baisse de PSNR, les flux sont dynamiquement transcodés afin d’adapter leur débit à celui du canal et rendre la transmission possible. La seconde architecture s’applique aux flux H. 264 SVC utilisant une échelonnabilité spatiale. Elle consiste à sélectionner par position fréquentielle les coefficients résiduels de la couche d’amélioration la plus haute afin d’obtenir des débits intermédiaires tout en restant dans la définition spatiale la plus élevée. Cette solution est mise en œuvre dans le cas d’une transmission ADSL, permettant d’augmenter la zone d’éligibilité des services vidéo HD et fournissant aux abonnés une qualité progressivement réduite
The works presented in this thesis are mainly part of the French ANR TOSCANE project which aims to optimize high definition video transmission. We propose two types of low complexity transrating architectures for H. 264/AVC streams to adapt video bitrate to channel bandwidth. The first transrating architecture is based on frequency selectivity of residual coefficients from H. 264/AVC streams. A comparison between this solution and the well known requantization processing in terms of bitrate reduction and video quality shows that our solution often gives better results. Then, our solution is included in a high definition video transmission scheme using power line communications. This type of channel can exhibit sudden changes states; as a consequence transmission needs a new channel estimation, bit and power allocation to guarantee quasi error free transmission. By means of a slight video distortion, transrating architecture is used to dynamically adapt video bitrate to channel one. The second transrating architecture is applied to H. 264 SVC streams using spatial scalability. It consists in selectively removing residual coefficients of upper enhancement layer to obtain intermediate bitrates with upper spatial definition. This transrating solution is used in an ADSL transmission, allowing the extension of the area of eligibility for high definition video services while providing a progressive reduced video quality to subscribers

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Corrêa, Guilherme Ribeiro. "Estudo e desenvolvimento de heurísticas e arquiteturas de hardware para decisão rápida do modo de codificação de bloco para o padrão H.264/AVC". reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2010. http://hdl.handle.net/10183/27654.

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O processo de compressão de vídeo é essencial para aplicações que utilizam vídeos digitais. O alto volume de informações contidas em um vídeo digital requer que um processo de compressão seja aplicado antes de este ser armazenado ou transmitido. O padrão H.264/AVC, estado-da-arte em termos de compressão de vídeo, introduziu um conjunto de ferramentas inéditas em relação a outros padrões, as quais possibilitam um ganho significativo em eficiência de compressão, diminuindo a taxa de bits sem perda na qualidade da imagem. Contudo, o preço deste ganho reside em um significativo aumento na complexidade de codificação. No padrão H.264/AVC, a codificação pode acontecer de acordo com um dos treze modos de codificação intra-quadro ou de acordo com um dos oito tamanhos de bloco disponíveis para a predição inter-quadros. A escolha de melhor modo utilizada pelo software de referência do padrão (JM 17.1) é baseada em uma busca exaustiva pelo melhor modo, realizando a codificação repetidamente para todos os modos até que o menor custo em termos de taxa de bits e distorção seja encontrado. Esta decisão aumenta drasticamente o fluxo de codificação, muitas vezes impossibilitando a codificação de vídeos digitais em tempo real. Neste contexto, a presente dissertação apresenta o estudo e o desenvolvimento de um conjunto de heurísticas que possibilitam a avaliação do melhor modo de codificação de bloco em um processo mais rápido que o usado pelo software de referência. Ao invés da realização do fluxo completo de codificação para todos os modos seguida por uma avaliação do melhor caso, propõe-se um conjunto de análises prévias que convergem para a decisão de apenas um modo de codificação. A redução atingida no número de repetições do processo de codificação foi de quarenta e sete vezes, ao custo de um aumento relativamente pequeno na taxa de bits. Quando comparada com outros trabalhos, a decisão rápida atingiu resultados expressivamente mais satisfatórios em termos de complexidade computacional, sem perda de qualidade ou aumento de taxa de bits significativo. Foram desenvolvidas arquiteturas de hardware que implementam as heurísticas propostas. A arquitetura de decisão intra-quadro atingiu uma frequência máxima de 105 MHz, enquanto que a arquitetura de decisão inter-quadros apresentou uma frequência de 118 MHz para dispositivos FPGA Virtex 5 da Xilinx, sendo ambas capazes de processar vídeos de alta definição em tempo real.
The video compression process is essential in digital video applications, due to the extremely high data volume present in a digital video to be stored or transmitted through a physical link. H.264/AVC, the state-of-art video coding standard, introduces a set of novel features which lead to a significant gain in terms of compression efficiency, decreasing the bit-rate without image quality losses. However, the price of this gain resides at a high complexity increase. In H.264/AVC, the encoding process can occur according to one of the thirteen intra-frame coding modes or according to one of the eight available inter-frames block sizes. In the reference software (JM 17.1), the choice of the best mode is performed through exhaustive executions of the whole encoding process. The mode which presents the lowest cost in terms of required bit-rate and image distortion is then chosen. This decision process increases significantly the encoding process, sometimes even forbidding its use in real time video coding applications. Considering this context, this thesis presents a study and the development of a set of heuristics which allow the evaluation of the best coding mode in a process which is faster than the one used by the reference software. Instead of performing the whole encoding flow for all the possible modes followed by an evaluation of the best case, this work proposes a set of pre-analysis which converge to the selection of one encoding mode. The reduction achieved in the number of repetitions of the encoding process is of forty seven times, at the cost of a relatively small bit-rate increase. When compared to other works, the fast mode decision results are expressively more satisfactory in terms of computational complexity, with no image quality loss or significant bit-rate increase. The hardware architectures which implement the proposed heuristics were also developed in this work. The architecture for intra-frame decision achieved a maximum frequency of 105 MHz, while the architecture for inter-frames decision presented a maximum frequency of 118 MHz for Virtex 5 FPGAs from Xilinx. They are both capable of processing high definition videos in real time.

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Abdullah, Jan Mirza, e Mahmododfateh Ahsan. "Multi-View Video Transmission over the Internet". Thesis, Linköping University, Department of Electrical Engineering, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-57903.

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3D television using multiple views rendering is receiving increasing interest. In this technology a number of video sequences are transmitted simultaneously and provides a larger view of the scene or stereoscopic viewing experience. With two views stereoscopic rendition is possible. Nowadays 3D displays are available that are capable of displaying several views simultaneously and the user is able to see different views by moving his head.

The thesis work aims at implementing a demonstration system with a number of simultaneous views. The system will include two cameras, computers at both the transmitting and receiving end and a multi-view display. Besides setting up the hardware, the main task is to implement software so that the transmission can be done over an IP-network.

This thesis report includes an overview and experiences of similar published systems, the implementation of real time video, its compression, encoding, and transmission over the internet with the help of socket programming and finally the multi-view display in 3D format. This report also describes the design considerations more precisely regarding the video coding and network protocols.

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Silva, André Marcelo Coelho da. "TÉCNICAS PARA O AUMENTO DE DESEMPENHO DE ARQUITETURAS DEDICADAS DAS TRANSFORMADAS DIRETAS E DE ESTIMAÇÃO DE MOVIMENTO DO PADRÃO H.264/AVC DE CODIFICAÇÃO DE VÍDEO PELOTAS 2009". Universidade Catolica de Pelotas, 2009. http://tede.ucpel.edu.br:8080/jspui/handle/tede/101.

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The increasing use of digital video on the Internet, devices and also in mobile digital TV has lead to an increasing interest for research in this area, from both industry and academia. This work follows this trend by proposing the investigation of the main aspects of digital video, video compression and also of the H.264/AVC video compression for the implementation of performance efficient dedicated architectures for some modules of the H.264/AVC encoder. In particular, this work presents some architectural alternatives for the increase of performance of two modules of the H.264/AVC, which are: T Module (composed by the Forward Hadamard and Discrete Cosine Transforms) and Motion Estimation (ME). For the implementation of these modules the use of techniques to the increase of performance has been considered, such as the use of efficient adders and pipeline. This efficient adders presents high use of hardware features. Thus, the implemented architectures in this work presented these characteristics too. The main aspect presented by the implemented modules is a large number of arithmetic operations of addition and subtraction for their processing. Thus, the motivation of this work is the increase of performance of these modules, from the use of efficient adder/subtractor circuits that are present in literature. In particular, 4:2, 8:2 and 16:2 adder compressors that perform the simultaneous addition of 4, 8 and 16 operands, respectively, with no penalties in area and the critical path are used. The architectures were described in VHDL and targeted to ASIC technology. The validation of the circuits and the obtained results were performed by using Leonardo Spectrum tool from Mentor Graphics. Comparisons against the solutions of the literature were done and the main results show that the architectures proposed in this work are more efficient. Significant gains in performance are achievable using our solutions for both Forward Transforms and Motion Estimation architectures
A crescente utilização de vídeos digitais na Internet, em dispositivos móveis e também na TV digital faz com que haja um interesse crescente em pesquisas nesta área, tanto na indústria quanto no meio acadêmico. Este trabalho segue esta tendência e tem como proposta estudar aspectos de vídeo digital, compressão de vídeo e também do padrão H.264/AVC de compressão de vídeo para a implementação de arquiteturas dedicadas eficientes em desempenho, isto é, com elevada frequência de operação, dos módulos do codificador do padrão H.264/AVC. Em particular, este trabalho apresenta algumas alternativas arquiteturais para aumento de desempenho de dois módulos do padrão H.264/AVC, que são: Módulo T (composto pelas Transformadas Diretas Transformadas Hadamard e Transformada Discreta do Coseno) e Estimação de Movimento (ME). A implementação destes módulos foi realizada utilizando técnicas para o aumento de desempenho, tais como o uso de somadores eficientes e pipeline. Uma característica dos somadores eficientes utilizados neste trabalho é o uso elevado de recursos de hardware. Assim, as arquiteturas implementadas neste trabalho também apresentaram esta característica. Os módulos implementados apresentam como principal característica um elevado número de operações aritméticas de soma e subtração para o seu processamento. Desta forma, a motivação deste trabalho consiste em aumentar o desempenho destes módulos, a partir da utilização de circuitos somadores/subtratores eficientes presentes na literatura. Em particular, são utilizados circuitos somadores compressores 4:2, 8:2 e 16:2, pois estes realizam a soma simultânea de 4, 8 e 16 operandos, respectivamente, sem penalidades em área e no caminho crítico. As arquiteturas foram descritas em VHDL e direcionadas para tecnologia ASIC, a validação e resultados foram obtidos através da ferramenta Leonardo Spectrum da Mentor Graphics. Para os estudos de caso utilizados neste trabalho (Transformadas Diretas e Estimação de Movimento), foram feitas comparações com soluções apresentadas na literatura e os resultados mostram que as arquiteturas implementadas neste trabalho obtiveram significativos ganhos em desempenho, quando comparadas com soluções apresentadas na literatura

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Bacquet, Anne-Sophie. "Transmission optimisée de flux vidéo haute définition H. 264/AVC et SVC sur ADSL2 : adaptation conjointe des paramètres de codage source et de transmission". Valenciennes, 2010. http://ged.univ-valenciennes.fr/nuxeo/site/esupversions/eae7153a-baf5-4519-95e2-77387529496c.

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L’éligibilité d’un client ADSL à un service vidéo dépend principalement de la longueur de sa ligne. Au delà d’une certaine distance, la transmission d’une vidéo au débit requis avec un niveau de qualité de service donné est impossible. Dans ces travaux nous avons proposé différentes solutions pour étendre la zone d’éligibilité aux services vidéo, et plus particulièrement les services haute définition. Elles s’appuient sur des techniques de réduction du débit du flux vidéo H. 264, dont les paramètres sont optimisés en termes de qualité reçue, conjointement avec les paramètres de transmission ADSL2. La première solution concerne un flux vidéo Haute Définition non scalable dont le débit est réduit grâce au transcodeur proposé. Le flux vidéo adapté est ensuite uniformément protégé et transmis sur ADSL2 selon les paramètres calculés lors de l’optimisation. Avec cette solution, l’éligibilité à été étendue de 1,2 Km en moyenne sur les lignes testées, avec une qualité visuelle résultante tout à fait acceptable. Les deux autres solutions concernent un flux vidéo scalable compressé avec l’extension scalable de H. 264/AVC. La première est basée sur une approche de réduction de débit hybride (scalabilité puis transcodage). Cette solution a permis d’améliorer la qualité des vidéos reçues avec des valeurs de PSNR jusqu’à 3dB supérieures. Ces premiers résultats avec SVC, nous ont conduits à évaluer les performances de ce codeur scalable pour des résolutions spatiales variables (CIF à Full-HD). Il est apparu que les performances de ce codec sont plus faibles pour les vidéos de résolutions inférieures. La dernière solution proposée pour l’extension d’éligibilité avec un flux vidéo scalable a donc été réalisée pour des vidéos de résolution CIF. Il s’agit d’une approche bi-résolution, où le flux vidéo scalable est scindé en deux parties d’importances variables, inégalement protégées. Cette proposition a permis d’améliorer les performances obtenues en comparaison avec une approche de protection égale jusqu'à 0. 5 dB
The eligibility of any ADSL subscriber to video services strongly depends on the length of his line. Beyond a given distance, video transmission is no more possible at the desired bit rate with a targeted quality of service level. In this work, we propose different solutions to extend the area of eligibility for high-definition video services. These solutions rely on bit rate adaptation techniques of the H. 264 compressed video streams, whose parameters are jointly optimized together with the ADSL2 transmission parameters in terms of received quality. In a first solution, we consider that the input high definition compressed video streams are non scalable: in this case, bit rate reduction is performed by means of appropriate transrating. The adapted video stream is then equally protected and transmitted according to optimal ADSL2 parameters. Thanks to this solution, eligibility was extended by 1. 2 km on average over the tested lines, with resultant satisfying visual quality. Two other solutions are then proposed when the input video stream is compressed thanks to the scalable extension of H. 264 named SVC. First, we propose a hybrid solution for bit rate adaptation, which relies on scalability then transrating. This solution improves the quality of received videos up to +3 dB in terms of PSNR values. Preliminary results obtained with the scalable extension of H. 264/AVC lead us to evaluate SVC performances for varying spatial resolutions (CIF to Full-HD). We show that the performances of this codec are reduced for lower resolutions videos. The last proposed solution for ADSL eligibility extension is finally presented for CIF resolution videos. It consists in a multi-resolution approach, where the scalable video stream is divided into two separated parts of variable relevance, which are therefore unequally protected. This proposal improves the performances up to 0. 5 dB obtained in comparison with an equal protection approach

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Vidal, Eloïse. "Étude et implémentation d'une architecture temps réel pour l'optimisation de la compression H.264/AVC de vidéos SD/HD". Thesis, Valenciennes, 2014. http://www.theses.fr/2014VALE0011/document.

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La vidéo sur IP a connu un essor rapide ces dernières années allant de la diffusion télévisuelle en haute qualité via des réseaux dédiés à la diffusion sur internet de contenus vidéo grand public. L’optimisation de l’encodage vidéo H.264/AVC permet aux différents acteurs du marché de se différencier en proposant des solutions pour réduire le débit nécessaire à la représentation d’un flux vidéo ainsi que pour améliorer la qualité perçue par les utilisateurs. C’est dans ce contexte de vidéo professionnelle en haute qualité que s’inscrivent ces travaux de thèse CIFRE réalisés au sein de l’entreprise Digigram, proposant des encodeurs vidéo temps réel pour des diffusions professionnelles en direct. Nous proposons deux solutions de prétraitement pour répondre aux problématiques du secteur de la distribution vidéo. Les deux solutions considèrent les caractéristiques du système visuel humain en exploitant un modèle de JND (Just Noticeable Distortion) définissant des seuils de perception en fonction d’une analyse du contenu des séquences vidéo à encoder. La première solution utilise un préfiltre adaptatif indépendant de l’encodeur, contrôlé par un modèle JND afin d'éliminer le contenu perceptuellement non pertinent et ainsi réduire le débit sans altérer la qualité ressentie. Une analyse approfondie de plusieurs filtres de la littérature, dont le filtre AWA (Adaptive Weighted Averaging) et le filtre bilatéral, nous a également amené à définir deux nouveaux filtres à support étendu qui permettent d’exploiter au mieux les corrélations dans les images haute définition. A l’aide de tests subjectifs, nous montrons que les préfiltres perceptuels proposés permettent en moyenne de diminuer le débit en sortie du codeur d'environ 20% pour une qualité constante en encodage VBR (débit variable) Intra et Inter-image. Finalement, une deuxième solution s’attache à améliorer la qualité perçue dans un contexte d’encodage CBR (débit constant) en intégrant un modèle JND dans l’une des implémentations de la norme H.264/AVC la plus reconnue, le codec x264. Une quantification adaptative perceptuelle est ainsi proposée permettant d’améliorer les performances du codec x264 en améliorant le codage de l’information de contour à moyen et bas débits en encodage intra et inter-image
The use of digital video over IP has increased exponentially over the last years, due to the development of high-speed networks dedicated to high quality TV transmission as well as the wide development of the nonprofessional video webcast. Optimization of the H.264/AVC encoding process allows manufacturers to offer differentiating encoding solutions, by reducing the bandwidth necessary for transmitting a video sequence at a given quality level, or improving the quality perceived by final users at a fixed bit rate. This thesis was carried out at the company Digigram in a context of professional high quality video. We propose two solutions of preprocessing which consider the characteristics of the human visual system by exploiting a JND profile (Just Noticeable Distortion). A JND model defines perceptual thresholds, below which a distortion cannot be seen, according to the video content. The first solution proposes an adaptive pre-filter independent to the encoder, controlled by a JND profile to reduce the perceptually non-relevant content and so reduce the bitrate while maintaining the perceived quality. By analyzing the state-of-the-art literature, the AWA (Adaptive Weighted Averaging) and Bilateral filters have been selected. Then we define two new filters using a large convolution mask, which enable to better exploit correlations in high-definition video contents. Through subjective tests, we show that the proposed perceptual prefilters give an average bitrate reduction of 20% for the same visual quality in VBR (Variable Bitrate) H.264/AVC Intra and Inter encoding. Finally, the second solution enables to improve the perceived quality in CBR (Constant Bitrate) encoding, by integrating the JND profile into the x264 codec, one of the best implementation of the H.264/AVC standard. Thus, we propose a perceptual adaptive quantization which enhances the x264 performance by improving edge information coding in low and middle bitrate applications

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Alaoui, Fdili Othmane. "Optimisation multicritères de la qualité de service dans les réseaux de capteurs multimédia sans fil". Thesis, Valenciennes, 2015. http://www.theses.fr/2015VALE0016/document.

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Les progrès réalisés en systèmes micro-électro-mécaniques couplés avec leur convergence vers les systèmes de communication sans fil, ont permis l'émergence des réseaux de capteurs sans fil (RCSF). Les contraintes de ces réseaux font que tous les efforts soient fournis pour proposer des solutions économes en énergie. Avec les récents développements des technologies CMOS, des capteurs d'images à faible coût ont été développés. En conséquence, un nouveau dérivé des RCSF, qui sont les Réseaux de Capteurs Vidéo Sans Fil (RCVSF), a été proposé. La particularité des données vidéo ainsi que les contraintes inhérentes aux nœuds ont introduit de nouveaux défis. Dans cette thèse, nous proposons deux solutions basées sur l'approche inter-couches pour la livraison de la vidéo sur les RCVSF. La première solution propose un nouveau schéma de compression vidéo adaptatif, efficace en énergie et basé sur la norme de compression vidéo H.264/AVC. Le flux vidéo est ensuite géré par une version améliorée du protocole MMSPEED que nous proposons et notons EQBSA-MMSPEED. Les résultats des simulations montrent que la durée de vie du réseau est étendue de 33%, tout en améliorant la qualité du flux vidéo reçu de 12%. Dans la deuxième solution, nous enrichissons le schéma de compression de modèles mathématiques pour prévoir la consommation d'énergie et la distorsion de l'image lors des phases d'encodage et de transmission. Le flux vidéo est géré par un nouveau protocole de routage efficace en énergie et à fiabilité améliorée noté ERMM. Comparée à une approche basique, cette solution réalise une extension de la durée de vie du réseau de 15%, tout en améliorant la qualité du flux vidéo reçu de 35%
Thanks to the valuable advances in Micro Electro-Mechanical Systems coupled with their convergence to wireless communication systems, the Wireless Sensor Networks (WSN). In the WSN context, all the efforts are made in order to propose energy-efficient solutions. With the recent developments in CMOS technology, low-cost imaging sensors have been developed. As a result, a new derivative of the WSN, which is the Wireless Video Sensor Network (WVSN), has been proposed. The particularities of the video data as well as the inherent constraints of the nodes have introduced new challenges. In this thesis, we propose two cross-layer based solutions for video delivery over the WVSN. The first solution proposes a new energy efficient and adaptive video compression scheme dedicated to the WVSNs, based on the H.264/AVC video compression standard. The video stream is then handled by an enhanced version of MMSPEED protocol, that we propose and note EQBSA-MMSPEED. Performance evaluation shows that the lifetime of the network is extended by 33%, while improving the video quality of the received stream by 12%. In the second solution, we enrich our compression scheme with mathematical models to predict the energy consumption and the video distortion during the encoding and the transmission phases. The video stream is then handled by a novel energy efficient and improved reliability routing protocol, that we note ERMM. Compared to a basic approach, this solution is extending the network lifetime by 15%, while improving the quality of the received video stream by 35%

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Messaoudi, Kamel. "Traitement des signaux et images en temps réel : "implantation de H.264 sur MPSoC"". Phd thesis, Université de Bourgogne, 2012. http://tel.archives-ouvertes.fr/tel-00905872.

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Cette thèse est élaborée en cotutelle entre l'université Badji Mokhtar (Laboratoire LERICA) et l'université de bourgogne (Laboratoire LE2I, UMR CNRS 5158). Elle constitue une contribution à l'étude et l'implantation de l'encodeur H.264/AVC. Durent l'évolution des normes de compression vidéo, une réalité sure est vérifiée de plus en plus : avoir une bonne performance du processus de compression nécessite l'élaboration d'équipements beaucoup plus performants en termes de puissance de calcul, de flexibilité et de portabilité et ceci afin de répondre aux exigences des différents traitements et satisfaire au critère " Temps Réel ". Pour assurer un temps réel pour ce genre d'applications, une solution reste possible est l'utilisation des systèmes sur puce (SoC) ou bien des systèmes multiprocesseurs sur puce (MPSoC) implantés sur des plateformes reconfigurables à base de circuit FPGA. L'objective de cette thèse consiste à l'étude et l'implantation des algorithmes de traitement des signaux et images et en particulier la norme H.264/AVC, et cela dans le but d'assurer un temps réel pour le cycle codage-décodage. Nous utilisons deux plateformes FPGA de Xilinx (ML501 et XUPV5). Dans la littérature, il existe déjà plusieurs implémentations du décodeur. Pour l'encodeur, malgré les efforts énormes réalisés, il reste toujours du travail pour l'optimisation des algorithmes et l'extraction des parallélismes possibles surtout avec une variété de profils et de niveaux de la norme H.264/AVC.Dans un premier temps de cette thèse, nous proposons une implantation matérielle d'un contrôleur mémoire spécialement pour l'encodeur H.264/AVC. Ce contrôleur est réalisé en ajoutant, au contrôleur mémoire DDR2 des deux plateformes de Xilinx, une couche intelligente capable de calculer les adresses et récupérer les données nécessaires pour les différents modules de traitement de l'encodeur. Ensuite, nous proposons des implantations matérielles (niveau RTL) des modules de traitement de l'encodeur H.264. Sur ces implantations, nous allons exploiter les deux principes de parallélisme et de pipelining autorisé par l'encodeur en vue de la grande dépendance inter-blocs. Nous avons ainsi proposé plusieurs améliorations et nouvelles techniques dans les modules de la chaine Intra et le filtre anti-blocs. A la fin de cette thèse, nous utilisons les modules réalisés en matériels pour la l'implantation Matérielle/logicielle de l'encodeur H.264/AVC. Des résultats de synthèse et de simulation, en utilisant les deux plateformes de Xilinx, sont montrés et comparés avec les autres implémentations existantes

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Leny, Marc. "Analyse et enrichissement de flux compressés : application à la vidéo surveillance". Thesis, Evry, Institut national des télécommunications, 2010. http://www.theses.fr/2010TELE0031/document.

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Le développement de réseaux de vidéosurveillance, civils ou militaires, pose des défis scientifiques et technologiques en termes d’analyse et de reconnaissance des contenus des flux compressés. Dans ce contexte, les contributions de cette thèse portent sur : - une méthode de segmentation automatique des objets mobiles (piétons, véhicules, animaux …) dans le domaine compressé, - la prise en compte des différents standards de compression les plus couramment utilisés en surveillance (MPEG-2, MPEG-4 Part 2 et MPEG-4 Part 10 / H.264 AVC), - une chaîne de traitement multi-flux optimisée depuis la segmentation des objets jusqu’à leur suivi et description. Le démonstrateur réalisé a permis d’évaluer les performances des approches méthodologiques développées dans le cadre d’un outil d’aide à l’investigation, identifiant les véhicules répondant à un signalement dans des bases de données de plusieurs dizaines d’heures. En outre, appliqué à des corpus représentatifs des différentes situations de vidéosurveillance (stations de métro, carrefours, surveillance de zones en milieu rural ou de frontières ...), le système a permis d’obtenir les résultats suivants : - analyse de 14 flux MPEG-2, 8 flux MPEG-4 Part 2 ou 3 flux AVC en temps réel sur un coeur à 2.66 GHZ (vidéo 720x576, 25 images par seconde), - taux de détection des véhicules de 100% sur la durée des séquences de surveillance de trafic, avec un taux de détection image par image proche des 95%, - segmentation de chaque objet sur 80 à 150% de sa surface (sous ou sur-segmentation liée au domaine compressé). Ces recherches ont fait l’objet du dépôt de 9 brevets liés à des nouveaux services et applications rendus opérationnels grâce aux approches mises en oeuvre. Citons entre autres des outils pour la protection inégale aux erreurs, la cryptographie visuelle, la vérification d’intégrité par tatouage ou l’enfouissement par stéganographie
The increasing deployment of civil and military videosurveillance networks brings both scientific and technological challenges regarding analysis and content recognition over compressed streams. In this context, the contributions of this thesis focus on: - an autonomous method to segment in the compressed domain mobile objects (pedestrians, vehicles, animals …), - the coverage of the various compression standards commonly used in surveillance (MPEG-2, MPEG-4 Part 2, MPEG-4 Part 10 / H.264 AVC), - an optimised multi-stream processing chain from the objects segmentation up to their tracking and description. The developed demonstrator made it possible to bench the performances of the methodological approaches chosen for a tool dedicated to help investigations. It identifies vehicles from a witness description in databases of tens of hours of video. Moreover, while dealing with corpus covering the different kind of content expected from surveillance (subway stations, crossroads, areas in countryside or border surveillance …), the system provided the following results: - simultaneous real time analysis of up to 14 MPEG-2 streams, 8 MPEG-4 Part 2 streams or 3 AVC streams on a single core (2.66 GHz; 720x576 video, 25 fps), - 100% vehicles detected over the length of traffic surveillance footages, with a image per image detection near 95%, - a segmentation spreading over 80 to 150% of the object area (under or over-segmentation linked with the compressed domain). These researches led to 9 patents linked with new services and applications that were made possible thanks to the suggested approaches. Among these lie tools for Unequal Error Protection, Visual Cryptography, Watermarking or Steganography

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Li, Xiongwen. "Enhancements & optimizations to H.264/AVC video coding". Thesis, Loughborough University, 2007. https://dspace.lboro.ac.uk/2134/35990.

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The H.264/AVC video coding standard offers enhanced performance compared to previous coding standards in terms of both rate-distortion (R-D) performance and functionality. In particular, its superior rate-distortion performance has resulted in a significant interest in its practical application in many different domains ranging from multimedia to security and surveillance. As a result in the recent past many successful research attempts have been made in further improving its efficiency and extending its application domains. This thesis provides two novel contributions: an object-based extension that is capable of extending H.264/AVC's effective use in video surveillance applications and a multi-objective optimization framework that can be used to enhance H.264/AVC's use in any general application area.

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Laroche, Guillaume. "Modules de codage par compétition et suppression de l'information de compétition pour le codage de séquences vidéo". Phd thesis, Télécom ParisTech, 2009. http://pastel.archives-ouvertes.fr/pastel-00005379.

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Cette thèse est dédiée à l'amélioration de la compression de séquences vidéo. Le but est de concevoir des méthodes suffisamment efficaces et réalistes pour être proposées aux organismes de normalisation de standard vidéo. Les approches choisies sont l'ajout de nouveaux modules de codage par compétition et la suppression de l'information de compétition. Un module de codage par compétition de prédicteurs de vecteurs mouvement, intégré dans le KTA, exploite, au sens du critère débit-distorsion, les redondances spatiales et temporelles des champs de vecteurs. De plus, une sélection automatique d'ensembles de prédicteurs orientée contenu est aussi proposée. Enfin, un nouveau mode de codage Intra basé sur un partitionnement 1D du macrobloc, réduisant la distance spatiale entre le signal de référence et la partition courante, est ajouté aux modes Intra bloc. Le standard de compression H.264/AVC, offre un nombre de compétitions plus élevé que celui de ses prédécesseurs. Pour réduire le débit lié à cette information de compétition, une partie de l'intelligence du codeur a été transférée au décodeur. Les indices des prédicteurs de vecteurs mouvement implicites, sont ainsi éliminés. Des prédicteurs Intra sont aussi supprimés en tenant compte du processus de quantification et du signal de référence. Enfin, en considérant que l'information de mouvement est une information de compétition, une estimation de mouvement au décodeur est mise en place. L'ensemble des méthodes développées offre des réductions de débit significatives par rapport à la référence. La combinaison d'une partie de ces méthodes obtient un gain moyen de 20% par rapport au standard pour un ensemble de séquences HD.

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Thiesse, Jean-Marc. "Codage vidéo ﬂexible par association d'un décodeur intelligent et d'un encodeur basé optimisation débit-distorsion". Phd thesis, Université de Nice Sophia-Antipolis, 2012. http://tel.archives-ouvertes.fr/tel-00719058.

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Cette thèse est dédiée à l'amélioration des performances de compression vidéo. Deux types d'approches, conventionnelle et en rupture, sont explorées aﬁn de proposer des méthodes eﬃcaces de codage Intra et Inter pour les futurs standards de compression. Deux outils sont étudiés pour la première approche. Tout d'abord, des indices de signalisations sont habilement traités par une technique issue du tatouage permettant de les masquer dans les résiduels de luminance et de chrominance de façon optimale selon le compromis débit-distorsion. La forte redondance dans le mouvement est ensuite exploitée pour améliorer le codage des vecteurs de mouvement. Après observation des précédents vecteurs utilisés, un ﬁn pronostic permet de déterminer les vecteurs résiduels à privilégier lors d'une troisième étape de modiﬁcation de la distribution des résiduels. 90% des vecteurs codés sont ainsi pronostiqués, ce qui permet une nette réduction de leur coût. L'approche en rupture vient de la constatation que H.264/AVC et son successeur HEVC sont basés sur un schéma prédictif multipliant les choix de codage, les améliorations passent alors par un meilleur codage de la texture à l'aide d'une compétition accrue. De tels schémas étant bornés par la signalisation engendrée, il est alors nécessaire de transférer des décisions au niveau du décodeur. Une approche basée sur la détermination conjointe au codeur et au décodeur de paramètres de codage à l'aide de partitions causales et ainsi proposée et appliquée aux modes de prédiction Intra et à la théorie émergente de l'échantillonnage compressé. Des performances encourageantes sont reportées et conﬁrment l'intérêt d'une telle solution innovante.

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30

Solak, Serdar. "Computational complexity management of H.264/AVC video coding standard". Thesis, McGill University, 2010. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=95058.

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Abstract (sommario):

The new H.264/AVC video coding standard achieves significantly improved compression efficiency compared to previous standards by adopting highly advanced and flexible encoding techniques at the expense of increased complexity. However, the high computational complexity of H.264/AVC is a big concern primarily for low-power devices with limited processing capabilities. This thesis presents new techniques to reduce and/or control the computational complexity of an H.264/AVC encoder. A new prediction method is developed to estimate the Lagrangian rate-distortion cost of a macroblock. The prediction method is used in the design of two complexity reduction algorithms for H.264/AVC. The first algorithm uses the predicted rate-distortion costs to identify the SKIP coded macroblocks prior to any INTRA or INTER mode trial. Simulation results show that the algorithm achieves significant complexity savings with negligible loss in rate-distortion performance. Similarly, the second algorithm seeks to further reduce the encoder complexity by using the predicted costs to identify not only SKIP coded but also the INTRA and INTER coded macroblocks at earlier stages. Results indicate greater reductions in the encoder complexity at the expense of slightly larger loss in rate-distortion performance. A complexity scalable encoding framework is proposed for controlling the encoder complexity at a macroblock level using a single parameter. The framework uses a special macroblock grouping technique called the ``wave-front macroblock scheduling''. The computational resources are allocated to the macroblocks within a wave-front. The resource allocation is further developed by adopting the Lagrangian rate-distortion cost prediction into the framework. Results demonstrate significant improvements in the rate-distortion performance of the encoder operating at limited complexity. Finally, the complexity reduction algorithms are installed into the complexity scalable encoding framework. Simul
La norme de codage vidéo H.264/AVC permet une efficacité de compression grandement supérieure à celle des normes précédentes grâce à des techniques de codage avancées d'une grande flexibilité. Ceci dit, le prix de cette performance améliorée est l'augmentation de la complexité du calcul requise, ce qui est un obstacle majeur pour les appareils dont la puissance et la capacité de calcul sont limitées. Ce mémoire présente de nouvelles techniques pour réduire et contrôler la complexité du calcul requise par un codeur H.264/AVC. Une nouvelle méthode de prédiction est développée pour estimer le coût débit-distorsion Lagrangien d'un macrobloc. Cette méthode est utilisée avec deux nouveaux algorithmes de réduction de la complexité pour un codeur H.264/AVC. Le premier algorithme utilise les coûts prédits du taux de distorsion pour identifier les macroblocs codés de type SKIP avant les essais des modes INTRA ou INTER. Des simulations démontrent que cet algorithme entraîne une réduction significative de la complexité du calcul avec une diminution négligeable de la performance débit-distorsion. Le deuxième algorithme utilise la méthode de prédiction des coûts débit-distorsion pour réduire la complexité du codeur en identifiant les macroblocs codés de type INTRA et INTER plus tôt lors du processus de codage. Les résultats indiquent que des réductions encore plus grandes de la complexité peuvent être obtenues au prix d'une dégradation accrue de la performance débit-distorsion. Un dispositif de contrôle évolutif est proposé pour contrôler la complexité au niveau du macrobloc à l'aide d'un unique paramètre. Le dispositif utilise une technique de regroupement gérant l'allocation des ressources de calcul aux macroblocs et intègre la méthode de prédiction du coût débit-distorsion Lagrangien. Les résultats démontrent une amélioration significative de la performance du taux de distorsion tout en limitant la comp

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31

Song, Yang. "Adaptive Motion Estimation Architecture for H.264/AVC Video Codec". Diss., The University of Arizona, 2011. http://hdl.handle.net/10150/145460.

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This study contributes to the domain of application specific adaptive hardware architectures with a design approach on processing element array, interconnect structure and memory interface concurrently. As summarized below, our architectural design choices push the limits of on-chip data reuse and avoid redundant computations that are essential for the high throughput, small area, and low power demands of the consumer market.Motion estimation (ME) is a key component in the H.264/AVC standard. Full Search (FS) based ME achieves optimal peak signal-to-noise-ratio (PSNR), and is the most adopted algorithm for developing hardware motion estimators. In this study, we first design a variable block size motion estimation (VBSME) engine based on hybrid grained processing elements (PEs) and a 2D programmable interconnect structure, which is adaptive to all block size configurations of H.264. PEs operate in bit-serial manner using MSB-first arithmetic for early termination to reduce the amount of computations, and the 2D architecture enables on-chip data reuse between neighboring PEs in a bit-by-bit pipelined fashion. Our design reduces the gate count by 7x compared to its ASIC counterpart, operates at a comparable frequency while sustaining 30 and 60 frames per second (fps); and outperforms bit parallel and bit serial architectures in terms of throughput and performance per gate.Numerous fast search algorithms (diamond, hexagon, three-step, etc.) have been developed to reduce the computation burden and the excessive amount of memory transactions required by FS, with a compromise in compression quality. We improve our VBSME engine and introduce the first adaptive ME architecture that provides the end user with the flexibility of choosing between the high quality video service during power-rich state (FS mode), and extended video service (fast search mode). We resolve the irregular indexing scheme challenge of three-step search (3SS) by introducing an on-chip buffer structure with a memory interface, which is adaptive to data access patterns of the FS and 3SS methods. The architecture sustains the real time CIF format (352x288) video encoding at 30fps with an operational frequency as low as 17.6MHz, and consumes 1.98mW based on the 45nm technology, outperforming all other FS and 3SS architectures.

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32

Yang, Mingyuan. "Mode decision for the H.264/AVC video coding standard". Thesis, Loughborough University, 2006. https://dspace.lboro.ac.uk/2134/35013.

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H.264/AVC video coding standard gives us a very promising future for the field of video broadcasting and communication because of its high coding efficiency compared with other older video coding standards. However, high coding efficiency also carries high computational complexity. Fast motion estimation and fast mode decision are two very useful techniques which can significantly reduce computational complexity. This thesis focuses on the field of fast mode decision. The goal of this thesis is that for very similar RD performance compared with H.264/AVC video coding standard, we aim to find new fast mode decision techniques which can afford significant time savings.

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33

Skeans, Jonathan P. "Rate Distortion Optimization for Interprediction in H.264/AVC Video Coding". University of Dayton / OhioLINK, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1375270759.

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34

Lubobya, Smart Charles. "Fast implementation of integer transforms in H.264/AVC video encoders". Master's thesis, University of Cape Town, 2011. http://hdl.handle.net/11427/11752.

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The Integer Discrete Cosine Transform (IDCT) and Hadamard transforms are adopted in the H.264/AVC standard encoder for the compression of residual video signals. Other video standards such as the H.261, H.262 and H.263 use Discrete Cosine Transform (DCT).

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35

Di, Laura Christian, Diego Pajuelo e Guillermo Kemper. "A Novel Steganography Technique for SDTV-H.264/AVC Encoded Video". Hindawi Publishing Corporation, 2016. http://hdl.handle.net/10757/609497.

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Today, eavesdropping is becoming a common issue in the rapidly growing digital network and has foreseen the need for secret communication channels embedded in digital media. In this paper, a novel steganography technique designed for Standard Definition Digital Television (SDTV) H.264/AVC encoded video sequences is presented. The algorithm introduced here makes use of the compression properties of the Context Adaptive Variable Length Coding (CAVLC) entropy encoder to achieve a low complexity and real-time inserting method. The chosen scheme hides the private message directly in the H.264/AVC bit stream by modifying the AC frequency quantized residual luminance coefficients of intrapredicted I-frames. In order to avoid error propagation in adjacent blocks, an interlaced embedding strategy is applied. Likewise, the steganography technique proposed allows self-detection of the hidden message at the target destination. The code source was implemented by mixing MATLAB 2010 b and Java development environments. Finally, experimental results have been assessed through objective and subjective quality measures and reveal that less visible artifacts are produced with the technique proposed by reaching PSNR values above 40.0 dB and an embedding bit rate average per secret communication channel of 425 bits/sec. This exemplifies that steganography is affordable in digital television.

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36

Hany, Hanafy Mahmoud Said. "Low bitrate multi-view video coding based on H.264/AVC". Thesis, Staffordshire University, 2015. http://eprints.staffs.ac.uk/2206/.

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Multi-view Video Coding (MVC) is vital for low bitrate applications that have constraints in bandwidth, battery capacity and memory size. Symmetric and mixed spatial-resolution coding approaches are addressed in this thesis, where Prediction Architecture (PA) is investigated using block matching statistics. Impact of camera separation is studied for symmetric coding to define a criterion for the best usage of MVC. Visual enhancement is studied for mixed spatial-resolution coding to improve visual quality for the interpolated frames by utilising the information derived from disparity compensation. In the context of symmetric coding investigations, camera separation cannot be used as a sufficient criterion to select suitable coding solution for a given video. Prediction architectures are proposed, where MVC that uses these architectures have higher coding performance than the corresponding codec that deploys a set of other prediction architectures, where the coding gain is up to 2.3 dB. An Adaptive Reference Frame Ordering (ARFO) algorithm is proposed that saves up to 6.2% in bits compared to static reference frame ordering when coding sequence that contains hard scene changes. In the case of mixed spatial-resolution coding investigations, a new PA is proposed that is able to save bitrate by 13.1 Kbps compared to the corresponding codec that uses the extended architecture based on 3D-digital multimedia. The codec that uses hierarchical B-picture PA has higher coding efficiency than the corresponding codec that employs the proposed PA, where the bitrate saving is 24.9 Kbps. The ARFO algorithm has been integrated with the proposed PA where it saves bitrates by up to 35.4 Kbps compared to corresponding codec that uses other prediction architectures. Visual enhancement algorithm is proposed and integrated within the presented PA. It provides highest quality improvement for the interpolated frames where coding gain is up to 0.9 dB compared to the corresponding frames that are coded by other prediction architectures.

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37

Shahid, Muhammad Zafar Javed. "Protection of Scalable Video by Encryption and Watermarking". Thesis, Montpellier 2, 2010. http://www.theses.fr/2010MON20074.

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Le champ du traitement des images et des vidéos attire l'attention depuis les deux dernières décennies. Ce champ couvre maintenant un spectre énorme d'applications comme la TV 3D, la télé-surveillance, la vision par ordinateur, l'imagerie médicale, la compression, la transmission, etc. En ce début de vingt et unième siècle nous sommes témoins d'une révolution importante. Les largeurs de bande des réseaux, les capacités de mémoire et les capacités de calcul ont été fortement augmentés durant cette période. Un client peut avoir un débit de plus de 100~mbps tandis qu'un autre peut utiliser une ligne à 56~kbps. Simultanément, un client peut avoir un poste de travail puissant, tandis que d'autres peuvent avoir juste un téléphone mobile. Au milieu de ces extrêmes, il y a des milliers de clients avec des capacités et des besoins très variables. De plus, les préférences d'un client doivent s'adapter à sa capacité, par exemple un client handicapé par sa largeur de bande peut être plus intéressé par une visualisation en temps réel sans interruption que d'avoir une haute résolution. Pour y faire face, des architectures hiérarchiques de codeurs vidéo ont été introduites afin de comprimer une seule fois, et de décomprimer de différentes manières. Comme la DCT n'a pas la fonctionnalité de multi-résolution, une architecture vidéo hiérarchique est conçue pour faire face aux défis des largeurs de bande et des puissances de traitement hétérogènes. Avec l'inondation des contenus numériques, qui peuvent être facilement copiés et modifiés, le besoin de la protection des contenus vidéo a pris plus d'importance. La protection de vidéos peut être réalisée avec l'aide de trois technologies : le tatouage de méta-données et l'insertion de droits d'auteur, le cryptage pour limiter l'accès aux personnes autorisées et la prise des empreintes digitales active pour le traçage de traître. L'idée principale dans notre travail est de développer des technologies de protection transparentes à l'utilisateur. Cela doit aboutir ainsi à un codeur vidéo modifié qui sera capable de coder et d'avoir un flux de données protégé. Puisque le contenu multimédia hiérarchique a déjà commencé à voir le jour, algorithmes pour la protection indépendante de couches d 'amélioration sont également proposées
Field of image and video processing has got lot of attention during the last two decades. This field now covers a vast spectrum of applications like 3D TV, tele-surveillance, computer vision, medical imaging, compression, transmission and much more. Of particular interest is the revolution being witnessed by the first decade of twenty-first century. Network bandwidths, memory capacities and computing efficiencies have got revolutionized during this period. One client may have a 100~mbps connection whereas the other may be using a 56~kbps dial up modem. Simultaneously, one client may have a powerful workstation while others may have just a smart-phone. In between these extremes, there may be thousands of clients with varying capabilities and needs. Moreover, the preferences of a client may adapt to his capacity, e.g. a client handicapped by bandwidth may be more interested in real-time visualization without interruption than in high resolution. To cope with it, scalable architectures of video codecs have been introduced to 'compress once, decompress many ways' paradigm. Since DCT lacks the multi-resolution functionality, a scalable video architecture is designed to cope with challenges of heterogeneous nature of bandwidth and processing power. With the inundation of digital content, which can be easily copied and modified, the need for protection of video content has got attention. Video protection can be materialized with help of three technologies: watermarking for meta data and copyright insertion, encryption to restrict access to authorized persons, and active fingerprinting for traitor tracing. The main idea in our work is to make the protection technology transparent to the user. This would thus result in a modified video codec which will be capable of encoding and playing a protected bitstream. Since scalable multimedia content has already started coming to the market, algorithms for independent protection of enhancement layers are also proposed

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38

Meng, Bojun. "Efficient intra prediction algorithm in H.264 /". View Abstract or Full-Text, 2003. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202003%20MENG.

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Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2003.
Includes bibliographical references (leaves 66-68). Also available in electronic version. Access restricted to campus users.

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39

Wong, Hoi Ming. "Motion estimation and compensation for H.264 video coding /". View abstract or full-text, 2006. http://library.ust.hk/cgi/db/thesis.pl?ECED%202006%20WONG.

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40

Comstedt, Erik. "Effect of additional compression features on h.264 surveillance video". Thesis, Mittuniversitetet, Avdelningen för informationssystem och -teknologi, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:miun:diva-30901.

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In video surveillance business, a recurring topic of discussion is quality versus data usage. A higher quality allows for more details to be captured at the cost of a higher bit rate, and for cameras monitoring events 24 hours a day, limiting data usage can quickly become a factor to consider. The purpose of this thesis has been to apply additional compression features to a h.264 video steam, and evaluate their effects on the videos overall quality. Using a surveillance camera, recordings of video streams were obtained. These recordings had constant GOP and frame rates. By breaking down one of these videos to an image sequence, it was possible to encode the image sequence into video streams with variable GOP/FPS using the software Ffmpeg. Additionally a user test was performed on these video streams, following the DSCQS standard from the ITU-R recom- mendation. The participants had to subjectively determine the quality of video streams. The results from the these tests showed that the participants did not no- tice any considerable difference in quality between the normal videos and the videos with variable GOP/FPS. Based of these results, the thesis has shown that that additional compression features can be applied to h.264 surveillance streams, without having a substantial effect on the video streams overall quality.

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41

Wu, Yannan. "Artifact reduction for AVS and H.264 coded videos /". View abstract or full-text, 2009. http://library.ust.hk/cgi/db/thesis.pl?ECED%202009%20WUY.

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42

Lam, Sui Yuk. "Complexity optimization in H.264 and scalable extension /". View abstract or full-text, 2008. http://library.ust.hk/cgi/db/thesis.pl?ECED%202008%20LAM.

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43

Mazataud, Camille. "Error concealment for H.264 video transmission". Thesis, Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/34715.

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Video coding standards such as H.264 AVC (Advanced Video Coding) rely on predictive coding to achieve high compression efficiency. Predictive coding consists of predicting each frame using preceding frames. However, predictive coding incurs a cost when transmitting over unreliable networks: frames are no longer independent and the loss of data in one frame may affect future frames. In this thesis, we study the effectiveness of Flexible Macroblock Ordering (FMO) in mitigating the effect of errors on the decoded video and propose solutions to improve the error concealment on H.264 decoders. After introducing the subject matter, we present the H.264 profiles and briefly determine their intended applications. Then we describe FMO and justify its usefulness for transmission over lossy networks. More precisely, we study the cost in terms of overheads and the improvements it offers in visual quality for damaged video frames. The unavailability of FMO in most H.264 profiles leads us to design a lossless FMO removal scheme, which allows the playback of FMO-encoded video on non FMO-compliant decoders. Then, we describe the process of removing the FMO structure but also underline some limitations that prevent the application of the scheme. Finally, we assess the induced overheads and propose a model to predict these overheads when FMO Type 1 is employed. Eventually, we develop a new error concealment method to enhance video quality without relying on channel feedback. This method is shown to be superior to existing methods, including those from the JM reference software and can be applied to compensate for the limitations of the scheme proposed FMO-removal scheme. After introducing our new method, we evaluate its performance and compare it to some classical algorithms.

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44

Zheng, Hao. "Analysis of H.264-based Vclan implementation /". free to MU campus, to others for purchase, 2004. http://wwwlib.umi.com/cr/mo/fullcit?p1422980.

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45

Yang, Kai-Ti, e 楊凱迪. "H.264/AVC Standard Digital Video Compression System Design". Thesis, 2004. http://ndltd.ncl.edu.tw/handle/12759760245111374188.

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碩士
中華大學
機械與航太工程研究所
92
The purpose of this research is by using the next generation compression technology - H.264/AVC standard in stead of MPEG-2 standard, and the high performance TMS320C6416 Evaluation Module to develop high resolution digital TV video display engine, which is programmable and integrating DSP/BIOS real-time multi-thread operation system. By the results of experiments and comparing H.264/AVC with MPEG-4, the Signal-to-noise Ratio(SNR) and the compression performance are increased by 3~5db and 2~3 times. The display speed is 22~23 frames per second with QP28 Foreman sequence of H.264/AVC Baseline Profile.

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46

陳致生. "An Efficient Intra-frame Encoding Process For Video Compression Standard H.264/AVC". Thesis, 2005. http://ndltd.ncl.edu.tw/handle/22585561452830888464.

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碩士
國立交通大學
資訊科學系所
93
Two international organizations named ISO/IEC and ITU-T had developed the H.264/AVC video coding standard that is the newest one by now. Although H.264/AVC can achieve higher coding efficiency than the previous standards, its encoding time complexity is unbearable. In this thesis, we will present an efficient algorithm for the intra mode decision which has nine prediction modes for a 4x4 block coding, and four prediction modes for a 16x16 block coding. A Fast Intra-mode Filtering Method (FIFM) is provided to quickly find out the candidate modes, and the spatial coherence is utilized to achieve some earlier termination. Experimental results show that the proposed algorithm can reduce the time complexity about 28.288% with 0.056dB loss of PSNR and 0.939% increment of bit-rate comparing with the RDO full search scheme. This result also shows that the proposed method is superior to the algorithm proposed by Pan et. al. under the same encoding conditions.

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47

Wu, Che-Wei, e 吳哲維. "Degradation Algorithm of Compressive Sensing for Integer DCT Transform with Application to H.264/AVC Video Compression". Thesis, 2013. http://ndltd.ncl.edu.tw/handle/59743086231294955541.

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碩士
淡江大學
電機工程學系碩士班
101
In the conventional image/video compression approach, we need to first capture the image/video signals from for example camera, and take more sampled data via sampling processes. For transmission those sampled data through various communication networks, high efficient compression algorithm is required for compressing data [2-8]. This processes of sampling analog signal and then compressing them for reducing the quantity of sampled data is a kind of wasting. Compressive sensing (CS) is an emerging approach for the acquisition of signals having a sparse or compressible representation in some basis. It has been developed from questions raised about the efficiency of the conventional signal processing pipeline for compression, coding and recovery of natural signals, including audio, still images and video. With the basic principle developed in CS, we might enable dramatically reduced measurement time, reduced sampling rates significantly, or reduced use of Analog-to-Digital converter resources. Many natural signals have concise representations when expressed in the proper basis. Recently, for data acquisition and signal recovery based on the premise that a signal having a sparse representation in the proper basis, the technique of degradation algorithm of CS [11] was presented for image compression. It showed that the complexity as well as signal reconstruction quality could be improved significantly. Via computer simulation, we verify that the performance is improved, in terms of the PSNR and the efficiency of the system.

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48

Zeng, Sheng-Mao, e 曾聖貿. "Efficient Chroma Subsampling Strategy for Compressing Digital Time Delay Integration Mosaic Video Sequences in H.264/AVC". Thesis, 2011. http://ndltd.ncl.edu.tw/handle/gjau4z.

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碩士
國立臺灣科技大學
資訊工程系
99
Digital time delay and integration (DTDI) mosaic video sequences captured by high speed DTDI line-scan cameras are commonly used in industrial print inspection and high speed capture applications. To reduce the memory requirement for saving these video sequences, it is necessary to compress them. In this paper, we present an efficient chroma subsampling strategy for compressing DTDI mosaic video sequences in H.264/AVC. Based on the color domain transform between the RGB domain and the YUV domain, a position selection strategy is proposed to determine the two subsampling chroma components, U and V, according to the DTDI mosaic structure. The quality of reconstructed DTDI video sequences is better than those reconstructed by conventional methods. By experimenting on some popular test DTDI mosaic video sequences, the results turned out to be superior than conventional ones that adopt H.264/AVC as compression standard.

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49

Verma, Rohit. "Local Binary Pattern Approach for Fast Block Based Motion Estimation". Thesis, 2013. http://hdl.handle.net/10012/7998.

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With the rapid growth of video services on smartphones such as video conferencing, video telephone and WebTV, implementation of video compression on mobile terminal becomes extremely important. However, the low computation capability of mobile devices becomes a bottleneck which calls for low complexity techniques for video coding. This work presents two set of algorithms for reducing the complexity of motion estimation. Binary motion estimation techniques using one-bit and two-bit transforms reduce the computational complexity of matching error criterion, however sometimes generate inaccurate motion vectors. The first set includes two neighborhood matching based algorithms which attempt to reduce computations to only a fraction of other methods. Simulation results demonstrate that full search local binary pattern (FS-LBP) algorithm reconstruct visually more accurate frames compared to full search algorithm (FSA). Its reduced complexity LBP (RC-LBP) version decreases computations significantly to only a fraction of the other methods while maintaining acceptable performance. The second set introduces edge detection approach for partial distortion elimination based on binary patterns. Spiral partial distortion elimination (SpiralPDE) has been proposed in literature which matches the pixel-to-pixel distortion in a predefined manner. Since, the contribution of all the pixels to the distortion function is different, therefore, it is important to analyze and extract these cardinal pixels. The proposed algorithms are called lossless fast full search partial distortion elimination ME based on local binary patterns (PLBP) and lossy edge-detection pixel decimation technique based on local binary patterns (ELBP). PLBP reduces the matching complexity by matching more contributable pixels early by identifying the most diverse pixels in a local neighborhood. ELBP captures the most representative pixels in a block in order of contribution to the distortion function by evaluating whether the individual pixels belong to the edge or background. Experimental results demonstrate substantial reduction in computational complexity of ELBP with only a marginal loss in prediction quality.

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50

Che-Chun, Su. "H.264/AVC-Based Multiple Description Video Coding". 2006. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-2507200616405400.

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