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Tesi sul tema "Parallel computers Evaluation"

Autore: Grafiati

Pubblicato: 4 giugno 2021

Ultima modifica: 11 febbraio 2022

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1

Grove, Duncan A. "Performance modelling of message-passing parallel programs." Title page, contents and abstract only, 2003. http://web4.library.adelaide.edu.au/theses/09PH/09phg8832.pdf.

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This dissertation describes a new performance modelling system, called the Performance Evaluating Virtual Parallel Machine (PEVPM). It uses a novel bottom-up approach, where submodels of individual computation and communication events are dynamically constructed from data-dependencies, current contention levels and the performance distributions of low-level operations, which define performance variability in the face of contention.

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2

Ligon, Walter Batchelor III. "An empirical evaluation of architectural reconfigurability." Diss., Georgia Institute of Technology, 1992. http://hdl.handle.net/1853/8204.

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3

Maache, Ahmed. "A prototype parallel multi-FPGA accelerator for SPICE CMOS model evaluation." Thesis, University of Southampton, 2011. https://eprints.soton.ac.uk/173435/.

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Due to ever increasing complexity of circuits, EDA tools and algorithms are demanding more computational power. This made transistor-level simulation a growing bottleneck in the circuit development process. This thesis serves as a proof of concept to evaluate and quantify the cost of using multi-FPGA systems in SPICE-like simulations in terms of acceleration, throughput, area, and power. To this end, a multi-FPGA architecture is designed to exploit the inherent parallelism in the device model evaluation phase within the SPICE simulator. A code transformation flow which converts the high-level

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4

Dhandapani, Mangayarkarasi. "Performance evaluation of high performance parallel I/O." Master's thesis, Mississippi State : Mississippi State University, 2003. http://sun.library.msstate.edu/ETD-db/theses/available/etd-07072003-155031/unrestricted/mythesis.pdf.

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5

Larriba, Pey Josep Lluís. "Design and evaluation of tridiagonal solvers for vector and parallel computers." Doctoral thesis, Universitat Politècnica de Catalunya, 1995. http://hdl.handle.net/10803/6012.

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6

Jiang, Jie Cheng. "Performance monitoring in transputer-based multicomputer networks." Thesis, University of British Columbia, 1990. http://hdl.handle.net/2429/28968.

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Parallel architectures, like the transputer-based multicomputer network, offer potentially enormous computational power at modest cost. However, writing programs on a multicomputer to exploit parallelism is very difficult due to the lack of tools to help users understand the run-time behavior of the parallel system and detect performance bottlenecks in their programs. This thesis examines the performance characteristics of parallel programs in a multicomputer network, and describes the design and implementation of a real-time performance monitoring tool on transputers. We started with a sim

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7

Afsahi, Ahmad. "Design and evaluation of communication latency hiding/reduction techniques for message-passing environments." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2000. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape4/PQDD_0019/NQ48225.pdf.

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8

Li, Xiaogang. "Efficient and parallel evaluation of XQuery." Columbus, Ohio : Ohio State University, 2006. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1139939037.

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9

Fu, Jingsong. "ParPlum : a system for evaluating parallel program optimization methods." PDXScholar, 1991. https://pdxscholar.library.pdx.edu/open_access_etds/4177.

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The diversity of application programs and parallel architectures makes the mapping problem complicated and hard to evaluate. The quality of mapping is machine and application dependent and varies due to inaccurate values of application and architecture characteristics. A system for developing, applying and evaluating mappings must have four characteristics: (1) Simplicity: A mapping procedure can be evaluated by separately evaluating its submapping, so the complicated problem can be simplified. (2) Generality: A wide range of application programs and architectures can be easily represented and

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10

Tang, Dezheng. "Mapping Programs to Parallel Architectures in the Real World." PDXScholar, 1992. https://pdxscholar.library.pdx.edu/open_access_etds/4534.

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Mapping an application program to a parallel architecture can be described as a multidimensional optimization problem. To simplify the problem, we divide the overall mapping process into three sequential substeps: partitioning, allocating, and scheduling, with each step using a few details of the program and architecture description. Due to the difficulty in accurately describing the program and architecture and the fact that each substep uses incomplete information, inaccuracy is pervasive in the real-world mapping process. We hypothesize that the inaccuracy and the use of suboptimal, heurist

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11

Surma, David Ray 1963. "Design and performance evaluation of parallel architectures for image segmentation processing." Thesis, The University of Arizona, 1989. http://hdl.handle.net/10150/277042.

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The design of parallel architectures to perform image segmentation processing is given. In addition, the various designs are evaluated as to their performance, and a discussion of an optimal design is given. In this thesis, a set of eight segmentation algorithms has been provided as a starting point. Four of these algorithms will be evaluated and partitioned using two techniques. From this study of partitioning and considering the data flow through the total system, architectures utilizing parallel techniques will be derived. Timing analysis using pen and paper techniques will be given on the

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12

Sankaran, Rajesh Madukkarumukumana. "Performance Evaluation of Specialized Hardware for Fast Global Operations on Distributed Memory Multicomputers." PDXScholar, 1995. https://pdxscholar.library.pdx.edu/open_access_etds/4919.

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Workstation cluster multicomputers are increasingly being applied for solving scientific problems that require massive computing power. Parallel Virtual Machine (PVM) is a popular message-passing model used to program these clusters. One of the major performance limiting factors for cluster multicomputers is their inefficiency in performing parallel program operations involving collective communications. These operations include synchronization, global reduction, broadcast/multicast operations and orderly access to shared global variables. Hall has demonstrated that a .secondary network with w

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13

Hansen, Christian Leland. "Towards Comparative Profiling of Parallel Applications with PPerfDB." PDXScholar, 2001. https://pdxscholar.library.pdx.edu/open_access_etds/2666.

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Due to the complex nature of parallel programming, it is difficult to diagnose and solve performance related problems. Knowledge of program behavior is obtained experimentally, with repeated runs of a slightly modified version of the application or the same code in different environments. In these circumstances, comparative performance analysis can provide meaningful insights into the subtle effects of system and code changes on parallel program behavior by highlighting the difference in performance results across executions. I have designed and implemented modules which extend the PPerfDB per

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14

Mohror, Kathryn Marie. "Scalable event tracking on high-end parallel systems." PDXScholar, 2010. https://pdxscholar.library.pdx.edu/open_access_etds/2811.

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Accurate performance analysis of high end systems requires event-based traces to correctly identify the root cause of a number of the complex performance problems that arise on these highly parallel systems. These high-end architectures contain tens to hundreds of thousands of processors, pushing application scalability challenges to new heights. Unfortunately, the collection of event-based data presents scalability challenges itself: the large volume of collected data increases tool overhead, and results in data files that are difficult to store and analyze. Our solution to these problems is

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15

Parker, Brandon S. "CLUE: A Cluster Evaluation Tool." Thesis, University of North Texas, 2006. https://digital.library.unt.edu/ark:/67531/metadc5444/.

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Modern high performance computing is dependent on parallel processing systems. Most current benchmarks reveal only the high level computational throughput metrics, which may be sufficient for single processor systems, but can lead to a misrepresentation of true system capability for parallel systems. A new benchmark is therefore proposed. CLUE (Cluster Evaluator) uses a cellular automata algorithm to evaluate the scalability of parallel processing machines. The benchmark also uses algorithmic variations to evaluate individual system components' impact on the overall serial fraction and efficie

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16

Suh, Taeweon. "Integration and Evaluation of Cache Coherence Protocols for Multiprocessor SoCs." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/14065.

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System-on-a-chip (SoC) designs is characterized by heavy reuse of IP blocks to satisfy specific computing needs for target applications, reduce overall design cost, and expedite time-to-market. To meet their performance goal and cost constraint, SoC designers integrate multiple, sometimes heterogeneous, processor IPs to perform particular functions. This design approach is called Multiprocessor SoC (MPSoC). In this thesis, I investigated generic methodologies for enabling efficient communication among heterogeneous processors and quantified the efficiency of coherence traffic. Hardware techniq

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17

Squillante, Mark S. "Issues in shared-memory multiprocessor scheduling : a performance evaluation /." Thesis, Connect to this title online; UW restricted, 1990. http://hdl.handle.net/1773/6858.

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18

Leung, K. H. W., and 梁海宏. "Implementation and performance evaluation of doubly-linked list protocols on a cluster of workstations." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 1999. http://hub.hku.hk/bib/B31223060.

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19

Balasubramaniam, Mahadevan. "Performance analysis and evaluation of dynamic loop scheduling techniques in a competitive runtime environment for distributed memory architectures." Master's thesis, Mississippi State : Mississippi State University, 2003. http://library.msstate.edu/etd/show.asp?etd=etd-04022003-154254.

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20

Codrescu, Lucian. "An evaluation of the Pica architecture for an object recognition application." Thesis, Georgia Institute of Technology, 1998. http://hdl.handle.net/1853/15483.

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21

Subbiah, Arun. "Design and evaluation of a distributed diagnosis algorithm for arbitrary network topologies in dynamic fault environments." Thesis, Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/13273.

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22

Grossman, J. P. 1973. "Design and evaluation of the Hamal parallel computer." Thesis, Massachusetts Institute of Technology, 2003. http://hdl.handle.net/1721.1/16909.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, February 2003.<br>"December 2002."<br>Includes bibliographical references (p. 145-152).<br>This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.<br>Parallel shared-memory machines with hundreds or thousands of processor-memory nodes have been built; in the future we will see machines with millions or even billions of nodes. Associated with such large systems is a new set of design challenges. M

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23

Sivasubramaniam, Anand. "A framework for evaluating architectural issues of parallel systems." Diss., Georgia Institute of Technology, 1995. http://hdl.handle.net/1853/9194.

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24

Pennycook, Simon J. "Evaluating the performance of legacy applications on emerging parallel architectures." Thesis, University of Warwick, 2012. http://wrap.warwick.ac.uk/57050/.

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The gap between a supercomputer's theoretical maximum ("peak") floating-point performance and that actually achieved by applications has grown wider over time. Today, a typical scientific application achieves only 5-20% of any given machine's peak processing capability, and this gap leaves room for significant improvements in execution times. This problem is most pronounced for modern "accelerator" architectures - collections of hundreds of simple, low-clocked cores capable of executing the same instruction on dozens of pieces of data simultaneously. This is a significant change from the low n

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25

Pout, Mike. "Performance evaluation of an associative processor array for computer vision tasks." Thesis, University of Bristol, 1992. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.358020.

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26

Söderquist, Fredrik. "Evaluation of Methodology for Parallel Scheduling." Thesis, Linköping University, Department of Electrical Engineering, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2867.

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<p>In the rapidly progressing evolution of technology, more and more emphasize is put on developing proper tools for the task of designing new and revolutionary systems. These tools are required in order to allow for a designer to fully utilize the power of new architectures and techniques. This thesis examines the current state of available scheduling tools for embedded systems, by evaluating and analyzing a number of di erent tools. An attempt is made to provide an overview of how the tools are constructed, and what types of methodology have been used.</p>

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27

Hernzndes-Gonzalez, Emilio. "A methodology for the design of parallel benchmarks." Thesis, University of Southampton, 1996. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.242181.

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28

O'Gorman, Russell John. "Design and application of the RPA II." Thesis, University of Southampton, 1989. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.330153.

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29

Hall, James E. "Performance evaluations of a parallel and expandable database computer -- the Multi-Backend Database computer." Thesis, Monterey, California. Naval Postgraduate School, 1989. http://hdl.handle.net/10945/27202.

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30

Papaefstathiou, Efstathios. "A framework for characterising parallel systems for performance evaluation." Thesis, University of Warwick, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.307345.

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31

Komathukattil, Deepa V. "Evaluating Speedup in Parallel Compilers." UNF Digital Commons, 2012. http://digitalcommons.unf.edu/etd/417.

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Parallel programming is prevalent in every field mainly to speed up computation. Advancements in multiprocessor technology fuel this trend toward parallel programming. However, modern compilers are still largely single threaded and do not take advantage of the machine resources available to them. There has been a lot of work done on compilers that add parallel constructs to the programs they are compiling, enabling programs to exploit parallelism at run time. Auto parallelization of loops by a compiler is one such example. Researchers have done very little work towards parallelizing the compil

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32

Teran, Maria. "An analysis for evaluating the cost/profit effectiveness of parallel systems." Master's thesis, Mississippi State : Mississippi State University, 2002. http://library.msstate.edu/etd/show.asp?etd=etd-10282002-201316.

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33

Lingtorp, Alexander, and Simon Mossmyr. "Performance comparison of parallel turbulent noise evaluation with different gradient selection methods." Thesis, KTH, Skolan för datavetenskap och kommunikation (CSC), 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-208410.

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Noise is of vital interest in many parts of computer sciene, especially in the computer graphics eld where noise is used to create nature-like e ects. Perlin’s 1985 algorithm to generate noise remains the most pop- ular in spite of many alternatives having been presented over the years. In this report we have examined the execution time impact of two new gradient table data structures and a new hash method for this algo- rithm, suggested by Perlin in 2002 and Olano in 2005 respectively. Our implementation simulated turbulence and ran in parallel on a modern GPU using the OpenCL framework. We a

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34

Engström, Gustav, and Marcus Falgert. "Implementation and Evaluation of Concurrency on Parallella." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-177385.

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The question asked is what optimizations can be done when working with the Parallella board from Adapteva and how they di er from other concurrent solutions. Parallella is a small super computer with a unique 16 core co-processor that we were to utilize. We have been working to parallelizing image manipulation software, and then analyzing the results of some performed tests. The goal is to conclude how to properly utilize the Epiphany accelerator, and also see how it performs in comparison to other CPUs. This project is a part of the PaPP project, which will utilize Parallella, and the work ca

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35

Markomanolis, Georgios. "Performance Evaluation and Prediction of Parallel Applications." Phd thesis, Ecole normale supérieure de lyon - ENS LYON, 2014. http://tel.archives-ouvertes.fr/tel-00951125.

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Analyzing and understanding the performance behavior of parallel applicationson various compute infrastructures is a long-standing concern in the HighPerformance Computing community. When the targeted execution environments arenot available, simulation is a reasonable approach to obtain objectiveperformance indicators and explore various ''what-if?'' scenarios. In thiswork we present a framework for the off-line simulation of MPIapplications. The main originality of our work with regard to the literature is to rely on\tit execution traces. This allows for an extreme scalability as heterogeneou

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36

Rudd, Kevin Edward. "Parallel three-dimensional acoustic and elastic wave simulation methods with applications in nondestructive evaluation." W&M ScholarWorks, 2007. https://scholarworks.wm.edu/etd/1539623332.

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In this dissertation, we present two parallelized 3D simulation techniques for three-dimensional acoustic and elastic wave propagation based on the finite integration technique. We demonstrate their usefulness in solving real-world problems with examples in the three very different areas of nondestructive evaluation, medical imaging, and security screening. More precisely, these include concealed weapons detection, periodontal ultrasography, and guided wave inspection of complex piping systems. We have employed these simulation methods to study complex wave phenomena and to develop and test a

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37

Rahman, Kamela Choudhury. "Complete Design Methodology of a Massively Parallel and Pipelined Memristive Stateful IMPLY Logic Based Reconfigurable Architecture." PDXScholar, 2016. http://pdxscholar.library.pdx.edu/open_access_etds/2956.

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Continued dimensional scaling of CMOS processes is approaching fundamental limits and therefore, alternate new devices and microarchitectures are explored to address the growing need of area scaling and performance gain. New nanotechnologies, such as memristors, emerge. Memristors can be used to perform stateful logic with nanowire crossbars, which allows for implementation of very large binary networks that can be easily reconfigured. This research involves the design of a memristor-based massively parallel datapath for various applications, specifically SIMD (Single Instruction Multiple Data

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38

Zhou, Jun. "Parallel Go on CUDA with Monte Carlo Tree Search." University of Cincinnati / OhioLINK, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1367942396.

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39

Li, Shen Carmen C. Duren Russell Walker. "Evaluating Impulse C and multiple parallelism partitions for a low-cost reconfigurable computing system." Waco, Tex. : Baylor University, 2008. http://hdl.handle.net/2104/5280.

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40

Karlbom, David. "A Performance Evaluation of MPI Shared Memory Programming." Thesis, KTH, Skolan för datavetenskap och kommunikation (CSC), 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-188676.

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The thesis investigates the Message Passing Interface (MPI) support for shared memory programming on modern hardware architecture with multiple Non-Uniform Memory Access (NUMA) domains. We investigate its performance in two case studies: the matrix-matrix multiplication and Conway’s game of life. We compare MPI shared memory performance in terms of execution time and memory consumption with the performance of implementations using OpenMP and MPI point-to-point communication, also called "MPI two-sided". We perform strong scaling tests in both test cases. We observe that MPI two-sided implement

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41

SARAIVA, SILVA IVAN. "Evaluation des performances au niveau systeme d'une architecture simd appliquee a la comparaison de sequences genetiques." Paris 6, 1995. http://www.theses.fr/1995PA066461.

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Comparaison de sequences genetiques est actuellement une activite courante en biologie moleculaire. Les comparaisons dites exactes sont, le plus souvent, executees avec des algorithmes de programmation dynamique tels que les algorithmes de needleman et wunsch ou de smith et waterman. Ces algorithmes presentant cependant une complexite theorique de l'ordre de o(m. N), ou m et n sont les tailles des sequences comparees. Cette complexite, alliee au grand volume des bases de donnees genetiques, rend impossible la realisation de comparaisons exhaustives sur des machines sequentielles classiques. Ce

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42

La, Fratta Patrick Anthony. "Evaluating the Design and Performance of a Single-Chip Parallel Computer Using System-Level Models and Methodology." Thesis, Virginia Tech, 2005. http://hdl.handle.net/10919/32424.

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As single-chip systems are predicted to soon contain over a billion transistors, design methodologies are evolving dramatically to account for the fast evolution of technologies and product properties. Novel methodologies feature the exploration of design alternatives early in development, the support for IPs, and early error detection â all with a decreasing time-to-market. In order to accommodate these product complexities and development needs, the modeling levels at which designers are working have quickly changed, as development at higher levels of abstraction allows for faster simula

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43

Savas, Suleyman. "Implementation and Evaluation of MPEG-4 Simple Profile Decoder on a Massively Parallel Processor Array." Thesis, Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-14549.

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The high demand of the video decoding has pushed the developers to implement the decoders on parallel architectures. This thesis provides the deliberations about the implementation of an MPEG-4 decoder on a massively parallel processor array (MPPA), Ambric 2045, by converting the CAL actor language implementation of the decoder. This decoder is the Xilinx model of the MPEG-4 Simple Profile decoder and consists of four main blocks; parser, acdc, idct2d and motion. The parser block is developed in another thesis work [20] and the rest of the decoder, which consists of the other three blocks, is

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44

Elliott, Grant (Grant Andrew). "Design and evaluation of a quasi-passive robotic knee brace : on the effects of parallel elasticity on human running." Thesis, Massachusetts Institute of Technology, 2012. http://hdl.handle.net/1721.1/71474.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.<br>Cataloged from PDF version of thesis.<br>Includes bibliographical references (p. 103-106).<br>While the effects of series compliance on running biomechanics are documented, the effects of parallel compliance are known only for the simpler case of hopping. As many practical exoskeleton and orthosis designs act in parallel with the leg, it is desirable to understand the effects of such an intervention. Spring-like forces offer a natural choice of perturbation, as they are both b

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45

Wang, Xiaoyang. "Evaluation of two word alignment systems." Thesis, Linköping University, Department of Computer and Information Science, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2215.

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<p>This project evaluates two different systems that generate wordalignments on English-Swedish data. The systems to be used are the Giza++ system, that may generate a variety of statistical translation models, and I*Trix system developed at IDA/NLPLab that generates word pairs with frequencies. </p><p>The file formats of these two systems, the way of running them and the differences of the two systems are addressed in this paper. Evaluation in this project considers a variety of parameters such as corpus size, characteristics of the corpus, the effect of linguistic knowledge, etc. At the end

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46

Gannholm, Lovisa. "A Comparative Evaluation Between Two Design Solutions for an Information Dashboard." Thesis, Linköpings universitet, Institutionen för datavetenskap, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-102134.

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This study is a software usability design case about information presentation in a software dashboard. The dashboard is supposed to present system information about an enterprise resource planning system. The study aims to evaluate if the intended users of the dashboard prefer a list-based or an object-based presentation of the information and why. It also investigates if the possibility to get familiar with the prototype affects the evaluation’s result. The study was performed using parallel prototypes and evaluation with users. The use of parallel prototypes is a rather unexplored area. L

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47

J'lali, Yousra. "DirectX 12: Performance Comparison Between Single- and Multithreaded Rendering when Culling Multiple Lights." Thesis, Blekinge Tekniska Högskola, Fakulteten för datavetenskaper, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-20201.

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Background. As newer computers are constructed, more advanced and powerful hardware come along with them. This leads to the enhancement of various program attributes and features by corporations to get ahold of the hardware, hence, improving performance. A relatively new API which serves to facilitate such logic, is Microsoft DirectX 12. There are numerous opinions about this specific API, and to get a slightly better understanding of its capabilities with hardware utilization, this research puts it under some tests. Objectives. This article’s aim is to steadily perform tests and comparisons i

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48

Hazra, Tushar K., Richard A. Stephenson, and Gregory M. Troendly. "EVOLUTION OF THE COST EFFECTIVE, HIGH PERFORMANCE GROUND SYSTEMS: A QUANTITATIVE APPROACH." International Foundation for Telemetering, 1994. http://hdl.handle.net/10150/608555.

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International Telemetering Conference Proceedings / October 17-20, 1994 / Town & Country Hotel and Conference Center, San Diego, California<br>During the recent years of small satellite space access missions, the trend has been towards designing low-cost ground control centers to maintain the space/ground cost ratio. The use of personal computers (PC) in combination with high speed transputer modules as embedded parallel processors, provides a relatively affordable, highly versatile, and reliable desktop workstation upon which satellite telemetry systems can be built to meet the ever-grow

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49

Nguyen, Ken D. "Multiple Biolgical Sequence Alignment: Scoring Functions, Algorithms, and Evaluations." Digital Archive @ GSU, 2011. http://digitalarchive.gsu.edu/cs_diss/62.

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Aligning multiple biological sequences such as protein sequences or DNA/RNA sequences is a fundamental task in bioinformatics and sequence analysis. These alignments may contain invaluable information that scientists need to predict the sequences' structures, determine the evolutionary relationships between them, or discover drug-like compounds that can bind to the sequences. Unfortunately, multiple sequence alignment (MSA) is NP-Complete. In addition, the lack of a reliable scoring method makes it very hard to align the sequences reliably and to evaluate the alignment outcomes. In this disser

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Jacquiot, Olivier. "Evaluation d'architectures parallèles à mémoire virtuelle partagée distribuée : étude et réalisation d'un émulateur." Phd thesis, Grenoble INPG, 1996. http://tel.archives-ouvertes.fr/tel-00004995.

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Abstract (sommario):

Le but principal de cette thèse est d'étudier et de réaliser un émulateur performant de machines parallèles dotées d'une mémoire virtuelle partagée distribuée. Cet émulateur doit permettre d'évaluer la charge induite par des machines de ce type sur le réseau d'interconnexion, afin d'en choisir la meilleure topologie. Pour cela, ce travail est divisé en deux parties. La première est constituée d'une étude de l'éventail des techniques pouvant être utilisées lors de la construction d'une hiérarchie de mémoires ou lors du maintien de la cohérence des données contenues dans cette hiérarchie. La sec

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