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Letteratura scientifica selezionata sul tema "SERIAL ASYNCHRONOUS"

Autore: Grafiati

Pubblicato: 26 ottobre 2023

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Articoli di riviste sul tema "SERIAL ASYNCHRONOUS"

Dobkin, Rostislav, Michael Moyal, Avinoam Kolodny e Ran Ginosar. "Asynchronous Current Mode Serial Communication". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 18, n. 7 (luglio 2010): 1107–17. http://dx.doi.org/10.1109/tvlsi.2009.2020859.

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P, Srikanth, e Latha Kodam. "Design of Serial-Serial Multiplier based on the Asynchronous Counter Accumulation". International Journal of Computer Applications Technology and Research 3, n. 4 (1 aprile 2014): 263–66. http://dx.doi.org/10.7753/ijcatr0304.1013.

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Tošić, M. B., M. K. Stojčev, D. M. Maksimović e G. Lj Djordjević. "The asynchronous counterflow pipeline bit-serial multiplier". Journal of Systems Architecture 44, n. 12 (settembre 1998): 985–1004. http://dx.doi.org/10.1016/s1383-7621(97)00046-5.

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Hariyanto, D., A. C. Nugraha, A. Asmara e H. Liu. "An Asynchronous Serial Communication Learning Media: Usability Evaluation". Journal of Physics: Conference Series 1413 (novembre 2019): 012018. http://dx.doi.org/10.1088/1742-6596/1413/1/012018.

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Pambudi, Bimo Langgeng Rilo, e Wahyu Sapto Aji. "Serial Communication Module with Visual Basic and Arduino for Practical Use". Buletin Ilmiah Sarjana Teknik Elektro 3, n. 2 (30 settembre 2021): 130–36. http://dx.doi.org/10.12928/biste.v3i2.1494.

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Interface techniques on computers and instruments cannot be separated from the software contained in computers to communicate. Communication that is commonly used is serial and parallel data. The method used in this development uses the Asynchronous serial data communication method which occurs if the clock on each communication device is not synchronized in reading data and displaying data. serial communication using Visual Basic Software as a medium to read and display serial data from Arduino. The level of accuracy when reading data and displaying data error rate/error 0% with 8 times of testing Data reading and displaying data. Teknik interface pada komputer dan instrumen tidak dapat dipisahkan dariÂ perangkat lunak yang terdapat pada komputer untuk berkomunikasi. Komunikasi yang umum digunakan adalah data serial dan paralel. Metode yang digunakan pada pengembangan ini menggunakan metode Komunikasi data serial Asynchronous yang terjadi jika clock yang terdapat pada masing-masing perangkat komunikasi tidak tersinkronisasi pada pembacaan data dan menampilkan data. komunikasi serial menggunakan Software Visual Basic sebagai media untuk membaca dan menampilkan data serial dari Arduino. Tingkat akurasi pada saat Pembacaan data dan menampilkan data tingkat kesalahan/error 0% dengan 8 kali pengujian Pembacaan data dan menampilkan data.

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Zeki, Semir. "A massively asynchronous, parallel brain". Philosophical Transactions of the Royal Society B: Biological Sciences 370, n. 1668 (19 maggio 2015): 20140174. http://dx.doi.org/10.1098/rstb.2014.0174.

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Whether the visual brain uses a parallel or a serial, hierarchical, strategy to process visual signals, the end result appears to be that different attributes of the visual scene are perceived asynchronously—with colour leading form (orientation) by 40 ms and direction of motion by about 80 ms. Whatever the neural root of this asynchrony, it creates a problem that has not been properly addressed, namely how visual attributes that are perceived asynchronously over brief time windows after stimulus onset are bound together in the longer term to give us a unified experience of the visual world, in which all attributes are apparently seen in perfect registration. In this review, I suggest that there is no central neural clock in the (visual) brain that synchronizes the activity of different processing systems. More likely, activity in each of the parallel processing-perceptual systems of the visual brain is reset independently, making of the brain a massively asynchronous organ, just like the new generation of more efficient computers promise to be. Given the asynchronous operations of the brain, it is likely that the results of activities in the different processing-perceptual systems are not bound by physiological interactions between cells in the specialized visual areas, but post-perceptually, outside the visual brain.

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Zhan, Hua Lin, e Xiao Chun Lai. "Multiple Serial Communication Design Based on ADSP-BF561". Advanced Materials Research 846-847 (novembre 2013): 667–70. http://dx.doi.org/10.4028/www.scientific.net/amr.846-847.667.

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This paper introduces asynchronous serial design and communication implementation by TI Co.,Ltd TL16C554 based on dual core processorADSP-BF561 and uClinux. This paper has accomplished multiple serial accessing using share interrupt scheme which has already been used in a wireless sense network.

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Kim, Hyoung Won, Hyo Dal Park e Taek Lyul Song. "Multisensor Bias Estimation with Serial Fusion for Asynchronous Sensors". Journal of the Korea Institute of Military Science and Technology 15, n. 5 (5 ottobre 2012): 676–86. http://dx.doi.org/10.9766/kimst.2012.15.5.676.

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KumarMeena, Manoj, e Neelam Rup Prakash. "ARM7TDMI based Low Cost Portable Serial Asynchronous Protocol Analyzer". International Journal of Computer Applications 40, n. 7 (29 febbraio 2012): 27–32. http://dx.doi.org/10.5120/4977-7234.

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Gopal, P. Bala, e K. Hari Kishore. "An FPGA Implementation of On Chip UART Testing with BIST Techniques". International Journal of Reconfigurable and Embedded Systems (IJRES) 5, n. 3 (1 novembre 2016): 176. http://dx.doi.org/10.11591/ijres.v5.i3.pp176-182.

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A Universal Asynchronous Receiver Transmitter (UART) is usually implemented for asynchronous serial communication, mostly used for short distance communications. It allows full duplex serial communication link and is used in data communication and control system. Nowadays there is a requirement for on chip testing to overcome the product failures. This paper targets the introduction of Built-in self test (BIST) for UART to overcome the above two constraints of testability and data integrity. The 8-bit UART with BIST module is coded in Verilog HDL and synthesized and simulated using Xilinx XST and implemented on SPARTAN 3E FPGA. Results indicate that this model eliminates the need for expensive testers and thereby it can reduce the development time and cost.

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Più fonti

Tesi sul tema "SERIAL ASYNCHRONOUS"

Schachter, Paul J. "TABS - an Asynchronous Block Serial Protocol for Multipoint Applications". International Foundation for Telemetering, 1986. http://hdl.handle.net/10150/615281.

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International Telemetering Conference Proceedings / October 13-16, 1986 / Riviera Hotel, Las Vegas, Nevada
Since the early 1960’s, AT&T has established a trend toward centralized and remote operations of the transmission network. Thorough and continuous monitoring of global network properties can only be achieved through centralization. As a result, a secondary network has evolved in support of these monitoring functions. The “telemetry network” comprises a system of distributed processors dedicated to analyses of the transmission network, together with all necessary communication links. Monitoring access to the transmission network is provided at special interface points. Often the interface hardware is integrated into the transmission network element itself. AT&T uses a special protocol, TABS, the Telemetry Asynchronous Block Serial protocol, at the interface between the telemetry network and the transmission network.[1] TABS was designed by AT&T Bell Laboratories to optimize the performance and economics of this interface. In this paper, we describe the structure of that protocol, its performance properties and current implementations.

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Ardestani, Arash Khani. "Asynchronous cellular automata - special networks local slowdown produces global speedup". [Tampa, Fla] : University of South Florida, 2009. http://purl.fcla.edu/usf/dc/et/SFE0002814.

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VARACCA, ALESSANDRO. "Problematiche commerciali ed organizzative nelle filiere di mais e soia: il ruolo dei prodotti GM e non-GM". Doctoral thesis, Università Cattolica del Sacro Cuore, 2016. http://hdl.handle.net/10280/10806.

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Da oltre vent’anni l’Unione Europea (UE) è protagonista di un acceso dibattito circa l’orami vasta adozione di OGM in agricoltura. Laddove la maggior parte dei paesi Nord e Sud americani ha già largamente introdotto tali colture, l’UE è invece in forte ritardo, complice una legislazione basata sul Principio di Precauzione. Queste discrepanze nei i processi legislativi hanno portato a galla alcune problematiche di carattere commerciale: primo, la riduzione delle disponibilità di materia prima non-OGM costituisce un problema per la stabilità delle filiere ad essa dedicate; secondo, il commercio di prodotti convenzionali è compromesso dalla possibilità di riscontrare varietà OGM non approvate in UE all’interno delle partite provenienti da paesi terzi. In ultimo, data l’ampia diffusione di OGM nelle Americhe, è lecito porsi il quesito di come tale tendenza abbia influito sui prezzi delle materie prime agricole. In questa tesi si cercherà di analizzare queste tematiche. Per prima cosa, ci occupiamo di capire come la filiera della soia non-OGM italiana sia organizzata e gestita in modo da minimizzare i rischi di presenza avventizia. La conclusione è che le forme di governance ibride garantiscono la migliore forma di gestione. Successivamente ci domandiamo se le diversità legislative in materia di OGM abbiamo un impatto sull’import Europeo di mais e soia. Utilizzando l’analisi della domanda, riscontriamo che i paesi esportatori competono o sul prezzo o in base alla disponibilità stagionale di prodotto. In ultimo, utilizzando serie storiche, analizziamo il ruolo del tasso di adozione di soia OGM sui prezzi reali; ciò che osserviamo indica che questo ha un effetto deflattivo di breve periodo, ma di scarso peso.
The debate on the increasing adoption of GMOs in agriculture has been in vogue for the last twenty years. Whereas most North and South American countries have largely adopted GMOs, the European Union (EU) has not. Since the EU legislation is based on the Precautionary Principle, the introduction of new GM varieties has been slow. These discrepancies put forward some fundamental issues: first, the decreasing availability of non-GM raw materials poses the sustainability of these supply chains at risk; second, the trade of conventional products is undermined by the possible occurrence of unauthorized GMOs in overseas. Last, the wide adoption of GM crops in North and Latin America poses the question of what effect the spreading of biotechnology in agriculture has exerted on market prices. In this thesis, we try to answer these three research questions. First of all, we investigate how the Italian supply chain for non-GM soybean meal is framed and managed in order to reduce the risk of adventitious presence. We find that hybrid organizations represent the best governance form. Next, we assess the role of legislative diversities (regarding GMOs) on EU import decisions through import demand analysis. We conclude that competition among exporters is solely based on price and seasonality. Last, we disentangle the role of GMOs adoption on the variability of US soybean prices. Results indicate that a higher rate of adoption reduces real soybean market prices, yet the effect is short lived and not much relevant.

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YUAN, SHI-YI, e 袁世一. "A bit-serial asynchronous RSA coding/decoding circuit". Thesis, 1993. http://ndltd.ncl.edu.tw/handle/42772675318552264977.

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SINGH, VIJENDRA KUMAR. "DESIGNING OF EMBEDDED SOLUTION FOR SERIAL ASYNCHRONOUS TO ANALOG RESOLVER FORMAT CONVERSION". Thesis, 2021. http://dspace.dtu.ac.in:8080/jspui/handle/repository/18966.

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A marine vessel platform is fitted with sensors and equipments of diverse origin which are required to work in tandem in order to enhance its operation capability. However, due to incompatibilities in respect of data formats and protocols that are used, these equipments/ sensors cannot be interfaced directly. Presently, some systems are digital type, and some are analog type. Therefore, this project focuses on the design and development of embedded solution for Serial Asynchronous (Digital) to Analog Resolver format conversion for transmission of Roll and Pitch Angle and it also provides interfacing of digital and analog Resolver systems. An embedded board was designed using Cadence OrCAD proprietary software and it was developed using microcontroller 8051, Digital to Resolver converter modules, Low power operational amplifiers and some other required components. This electronic interfacing embedded board converts the Digital input contains Roll and Pitch angle into Analog Resolver types of output. It was tested using simulated Roll and Pitch angle created with the help of COM Port Toolkit application software and the output of this embedded interfacing solution was measured on Angle Position Indicator (API) and on an oscilloscope.

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Jacquier, Vanessa. "Metastability for serial and parallel dynamics". Doctoral thesis, 2022. http://hdl.handle.net/2158/1274534.

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Metastability is an ubiquitous phenomenon in nature. It appears in a plethora of diverse fields including physics, chemistry, biology, computer science, climatology and economics. Metastability is best described as a dynamical phenomenon that occurs when a system is close to a first order phase transition. After changing some thermodynamic parameters, the system remains for a considerable (random) time in the old phase, the metastable state, before suddenly making a transition to the new phase, the stable state. In other words, on a short time scale, the system behaves as if it was in equilibrium, while, on a long time scale, it moves between different regions of the state space. At low temperature, this motion is preceded by the appearance of a critical mesoscopic configuration of the system via a spontaneous fluctuation or some external perturbation. Thus, when the system is initiated in the metastable phase, it starts its long transition towards the stable phase. In particular, it must overcome an energy barrier to reach the stable state starting from the metastable state. Formally, an Hamiltonian or energy function and the associated dynamics characterized the detailed evolution of the system. Moreover, it is possible to define an equilibrium measure based on the Hamiltonian, for example the Gibbs measure. If the dynamics satisfies the detailed balance condition, then it is reversible with respect to this equilibrium measure. There are three interesting questions that are typically investigated in metastability. The first is the study of the transition time from the set of metastable states to the set of the stable states, i.e., the time necessary to arrive at the equilibrium phase. The second issue is the identification of the so-called critical configurations that the system creates in order to reach equilibrium. The third question concerns the study of the typical paths that the system follows with high probability during the transition from the metastable state to the stable state. The thesis is organized in five chapters. In the first two chapters, we present the different approaches and results on asynchronous (serial) and synchronous (parallel) dynamics, in Chapters 2 and 3 respectively. In particular, at the end of the third chapter, we present one of the novelties of this work: an estimate of the mixing time and of the spectral gap, and the computation of the prefactor for the mean transition time also in the case of a series of degenerate metastable states. Next, we study three models evolving under different dynamics. In Chapter 4, we examine the Ising model on the hexagonal lattice with a serial non-conservative dynamics, Glauber dynamics. In particular, we prove some model-dependent results that together with the results of Chapter 2 yield the desired metastability theorems. Indeed, we identify the metastable states proving the recurrence property and computing the maximal stability level. In addition to this, we give a geometrical description of the critical configurations and we show how these are related to polyiamonds. The characterization of the shape of the critical configurations allows us to estimate the mean transition time via potential-theoretic approach. In Chapter 5.1, we describe a particular Probabilistic Cellular Automata model to represent the metastable behavior of a system subject to parallel dynamics. In particular, using our model-independent results at the end of Chapter 3, we show the behavior of the mixing time and the spectral gap, and we find a rigorous estimate of the expected hitting time. In addition, we identify the metastable states proving recurrence property and classifying the configurations according their stability level. Finally, in Chapter 6, we study the Blume-Capel model evolving under a serial conservative dynamics, the Kawasaki dynamics. These results are still quite heuristic since this is an ongoing project. We present an heuristic study of the phase-diagram and we explain the behavior of the system showing which should be the stable and the metastable states. We suggest an idea based on the crucial role of the boundary to estimate the stability level, to prove the recurrence property and to show the asymptotic behavior of transition time.

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Libri sul tema "SERIAL ASYNCHRONOUS"

1945-, Spaniol Otto, Danthine A e Effelsberg Wolfgang, a cura di. Architecture and protocols for high-speed networks. Boston: Kluwer Academic, 1994.

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Danthine, André, Wolfgang Effelsberg e Otto Spaniol. Architecture and Protocols for High-Speed Networks. Springer, 2013.

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Effelsberg, Wolfgang, Andre Danthine e Otto Spaniol. Architecture and Protocols for High-Speed Networks. Springer, 2010.

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Capitoli di libri sul tema "SERIAL ASYNCHRONOUS"

Meroth, Ansgar, e Petre Sora. "Asynchronous Serial Interfaces". In Sensor networks in theory and practice, 183–204. Wiesbaden: Springer Fachmedien Wiesbaden, 2023. http://dx.doi.org/10.1007/978-3-658-39576-6_7.

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Dawoud, Dawoud Shenouda, e Peter Dawoud. "Universal Asynchronous Receiver/Transmitter (UART)". In Serial Communication Protocols and Standards, 47–92. New York: River Publishers, 2022. http://dx.doi.org/10.1201/9781003339496-2.

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Oguri, Kiyoshi, Yuichiro Shibata e Akira Nagoya. "Asynchronous Bit-Serial Datapath for Object-Oriented Reconfigurable Architecture PCA". In Advances in Computer Systems Architecture, 54–68. Berlin, Heidelberg: Springer Berlin Heidelberg, 2003. http://dx.doi.org/10.1007/978-3-540-39864-6_6.

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Zhang, Weigong, Yongqin Hu, Rui Ding e Bo Yang. "Research on High-Speed Asynchronous Serial Transmission Based on 8b10b". In Communications in Computer and Information Science, 586–92. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-23220-6_74.

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Bridgett, Rob. "Diversity of Work (Parallel, Serial/Synchronous, Semi-Synchronous, and Asynchronous)". In Working with Sound, 26–28. London: Focal Press, 2023. http://dx.doi.org/10.4324/9781003354352-8.

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Jesshope, Chris, e Ivailo Nedelchev. "Asynchronous packet routers". In DIMACS Series in Discrete Mathematics and Theoretical Computer Science, 211–27. Providence, Rhode Island: American Mathematical Society, 1995. http://dx.doi.org/10.1090/dimacs/021/15.

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Nanya, Takashi. "Challenges to Dependable Asynchronous Processor Design". In The Kluwer International Series in Engineering and Computer Science, 191–213. Boston, MA: Springer US, 1993. http://dx.doi.org/10.1007/978-1-4615-3154-8_9.

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Neto, Abel, Pedro Cardoso e Miguel Carvalhais. "Asynchronous Interactions Between Players and Game World". In Springer Series in Design and Innovation, 148–56. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-61671-7_14.

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Gorrieri, Roberto. "Adding Asynchronous Parallel Composition: CFM and BPP". In Monographs in Theoretical Computer Science. An EATCS Series, 95–119. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-55559-1_5.

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Berthet, C., e E. Cerny. "Verification of Asynchronous Circuits: Behaviors, Constraints and Specifications". In The Kluwer International Series in Engineering and Computer Science, 385–404. Boston, MA: Springer US, 1988. http://dx.doi.org/10.1007/978-1-4613-2007-4_13.

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Atti di convegni sul tema "SERIAL ASYNCHRONOUS"

Lines, Andrew. "Asynchronous Serial Infrastructure Using FPIO". In 2021 27th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). IEEE, 2021. http://dx.doi.org/10.1109/async48570.2021.00017.

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Ji, Wang, Liu Zhaoqing e Zhang Yigang. "Design of 4-Channel Asynchronous Serial Communications Interface". In 2007 8th International Conference on Electronic Measurement and Instruments. IEEE, 2007. http://dx.doi.org/10.1109/icemi.2007.4351287.

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Hongying, Guo, e Ren Guo-Feng. "The Design of Asynchronous Serial Interface Detection Apparatus". In 2012 International Conference on Computing, Measurement, Control and Sensor Network (CMCS). IEEE, 2012. http://dx.doi.org/10.1109/cmcsn.2012.39.

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Andrysiewicz, Wojciech, Dariusz Koscielnik e Marek Miskowicz. "I2C hardware master serial interface for asynchronous ADCs". In 2015 IEEE International Symposium on Systems Engineering (ISSE). IEEE, 2015. http://dx.doi.org/10.1109/syseng.2015.7302736.

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Kumar Singh, Viiendra, e Yashna Sharma. "Designing of Serial Asynchronous to Analog Resolver Format Converter". In 2021 6th International Conference on Communication and Electronics Systems (ICCES). IEEE, 2021. http://dx.doi.org/10.1109/icces51350.2021.9489231.

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Sauer, Jon, Vincent Heuring, Harry Jordan e Jonathan Pratt. "Bit serial optical computer project". In OSA Annual Meeting. Washington, D.C.: Optica Publishing Group, 1988. http://dx.doi.org/10.1364/oam.1988.mt3.

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We have begun one of three proof-of-principle system projects to be demonstrated recently. The design philosophy is to build, with a minimal and reliable subset of the optoelectronic components currently available, a functional stored-program digital computer system. A migration path to gigahertz speeds, with the inclusion of as yet undeveloped all-optical devices, is a central design goal. A result of this effort should be a more complete understanding of the architectural and practical design issues involved in building digital optical processors. These include construction without the benefit of optical asynchronous memory or optical cascadable logic.

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Fok, Sam, e Kwabena Boahen. "A Serial H-Tree Router for Two-Dimensional Arrays". In 2018 24th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). IEEE, 2018. http://dx.doi.org/10.1109/async.2018.00026.

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Dobkin, Rostislav Reuven, Yevgeny Perelman, Tuvia Liran, Ran Ginosar e Avinoam Kolodny. "High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link". In 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07). IEEE, 2007. http://dx.doi.org/10.1109/async.2007.20.

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Lin, Shang-Hsien, Kuang-Hao Lin, Ssu-Shun Huang e Shou-Cheng Peng. "Design and Implementation of Asynchronous Serial Digital Data Transmission Decoder". In 2020 IEEE 9th Global Conference on Consumer Electronics (GCCE). IEEE, 2020. http://dx.doi.org/10.1109/gcce50665.2020.9291807.

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Ros, Paolo Motto, Marco Crepaldi, Chiara Bartolozzi e Danilo Demarchi. "Asynchronous DC-free serial protocol for event-based AER systems". In 2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS). IEEE, 2015. http://dx.doi.org/10.1109/icecs.2015.7440295.

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Rapporti di organizzazioni sul tema "SERIAL ASYNCHRONOUS"

Quail, Stephanie, e Sarah Coysh. Inside Out: A Curriculum for Making Grant Outputs into OER. York University Libraries, ottobre 2020. http://dx.doi.org/10.25071/10315/38016.

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Catalyzed by the passing of the York University Open Access Policy last year, a recognition has been growing at York University, like most other institutions, about the value of Open Educational Resources (OER) and more broadly, open education. This heightened awareness led to the formation of a campus-wide Open Education Working Group in January 2020. The group advocated that faculty members who receive internal funding for teaching innovation projects through York’s Academic Innovation Fund (AIF) should include a Creative Commons license on their grant outputs to facilitate the re-use, and potentially re-mixing, of the content by educators inside and outside of York University. A copy and/or link to their grant output would also be deposited into York’s institutional repository, YorkSpace. To support the 71 funded projects in achieving these lofty goals, an open education and open licensing curriculum was developed by two of the librarian members of the Open Education Working Group. This session describes how the librarians created the training program and participants will leave the session better understanding: How to develop learning modules for adult learners and apply these best practices when teaching faculty online (synchronously & asynchronously); How to access York’s open education training program and learn how they can remix the content for their own institution’s training purposes; The common types of questions and misconceptions that arise when teaching an open education and Creative Commons licensing program for faculty. Originally the program was conceived as an in-person workshop series; however, with the COVID-19 campus closure, it was redesigned into a four module synchronous and asynchronous educational program delivered via Moodle, H5P and Zoom. Modeled after the SUNY OER Community Course and materials from Abbey Elder’s OER Starter Kit, the program gave grant recipients a grounding in open educational resources, searching open course material repositories, copyright/Creative Commons licensing, and content deposit in York’s institutional repository, including OER metadata creation and accessibility considerations. The librarians modeled best practices in the use and creation of Creative Commons licensed resources throughout the program. Qualitative feedback was gathered at the end of each module in both the synchronous and asynchronous offerings of the program and will be shared with participants. The presenters will also discuss lessons learned, next steps, and some of the challenges they encountered. https://youtu.be/n6dT8UNLtJo

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