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Статті в журналах з теми "Mémoire non volatile, NVM":
1
Shao, Zili, and Yuan-Hao Chang. "Non-Volatile memory (NVM) technologies." Journal of Systems Architecture 71 (November 2016): 1. http://dx.doi.org/10.1016/j.sysarc.2016.11.007.
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Chu, Zhaole, Yongping Luo, and Peiquan Jin. "An Efficient Sorting Algorithm for Non-Volatile Memory." International Journal of Software Engineering and Knowledge Engineering 31, no. 11n12 (December 2021): 1603–21. http://dx.doi.org/10.1142/s0218194021400143.
Анотація:
Non-volatile memory (NVM) has emerged as an alternative of the next-generation memory due to its non-volatility, byte addressability, high storage-density, and low-energy consumption. However, NVM also has some limitations, e.g. asymmetric read and write latency. Therefore, at present, it is not realistic to completely replace DRAM with NVM in computer systems. A more feasible scheme is to adopt the hybrid memory architecture composed of NVM and DRAM. Following the assumption of hybrid memory architecture, in this paper, we propose an NVM-friendly sorting algorithm called NVMSorting. Particularly, we introduce a new concept called Natural Run to improve the existing MONTRES algorithm. Further, we apply the proposed NVMSorting to database join algorithms to improve the performance of the existing sort-merge join. To verify the performance of our proposal, we implement six existing sorting algorithms as baselines, including the MONTRES algorithm, and conduct comparative experiments on real Intel Optane DC persistent memory. The results show that NVMSorting outperforms other sorting algorithms in terms of execution time and NVM writes. In addition, the results of the join experiment show that the NVMSorting algorithm achieves the highest performance among all schemes. Especially, in the partially ordered data, the execution time of NVMSorting is 2.9%, 2.7%, and 4.2% less than MONTRES, external sort, and quick sort, respectively. Also, the amount of NVM writes of the NVMSorting is 26.1%, 43.6%, 96.2% less than MONTRES, external sort, and quick sort, respectively.
3
Kawata, Hirotaka, Gaku Nakagawa, and Shuichi Oikawa. "Using DRAM as Cache for Non-Volatile Main Memory Swapping." International Journal of Software Innovation 4, no. 1 (January 2016): 61–71. http://dx.doi.org/10.4018/ijsi.2016010105.
Анотація:
The performance of mobile devices such as smartphones and tablets has been rapidly improving in recent years. However, these improvements have been seriously affecting power consumption. One of the greatest challenges is to achieve efficient power management for battery-equipped mobile devices. To solve this problem, the authors focus on the emerging non-volatile memory (NVM), which has been receiving increasing attention in recent years. Since its performance is comparable with that of DRAM, it is possible to replace the main memory with NVM, thereby reducing power consumption. However, the price and capacity of NVM are problematic. Therefore, the authors provide a large memory space without performance degradation by combining NVM with other memory devices. In this study, they propose a design for non-volatile main memory systems that use DRAM as a swap space. This enables both high performance and energy efficient memory management through dynamic power management in NVM and DRAM.
4
Li, Xiaochang, and Zhengjun Zhai. "UHNVM: A Universal Heterogeneous Cache Design with Non-Volatile Memory." Electronics 10, no. 15 (July 22, 2021): 1760. http://dx.doi.org/10.3390/electronics10151760.
Анотація:
During the recent decades, non-volatile memory (NVM) has been anticipated to scale up the main memory size, improve the performance of applications, and reduce the speed gap between main memory and storage devices, while supporting persistent storage to cope with power outages. However, to fit NVM, all existing DRAM-based applications have to be rewritten by developers. Therefore, the developer must have a good understanding of targeted application codes, so as to manually distinguish and store data fit for NVM. In order to intelligently facilitate NVM deployment for existing legacy applications, we propose a universal heterogeneous cache hierarchy which is able to automatically select and store the appropriate data of applications for non-volatile memory (UHNVM), without compulsory code understanding. In this article, a program context (PC) technique is proposed in the user space to help UHNVM to classify data. Comparing to the conventional hot or cold files categories, the PC technique can categorize application data in a fine-grained manner, enabling us to store them either in NVM or SSDs efficiently for better performance. Our experimental results using a real Optane dual-inline-memory-module (DIMM) card show that our new heterogeneous architecture reduces elapsed times by about 11% compared to the conventional kernel memory configuration without NVM.
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He, Qinlu, Huiguo Dong, Genqing Bian, Fan Zhang, Weiqi Zhang, Kexin Liu, and Zhen Li. "The Research of Spark Memory Optimization Based on Non-Volatile Memory." Journal of Nanoelectronics and Optoelectronics 17, no. 1 (January 1, 2022): 30–39. http://dx.doi.org/10.1166/jno.2022.3166.
Анотація:
With the advent of the significant data era, more and more data information needs to be processed, bringing tremendous challenges to storage and computing. The spark amount of data is getting larger and larger, and the I/O bottleneck of computing and scheduling from the disk has increasingly become an essential factor restricting performance. The spark came into being and proposed in-memory computing, which significantly improved the computing speed. In addition, the high rate of the memory is easy to lose without power, and the small but expensive feature is also an urgent need to improve. The emergence of new non-volatile memory (NVM) not only brings the characteristics of non-volatile, large capacity, low latency but also brings new opportunities and challenges to the storage system. Therefore, based on the emergence of NVM and the problems to be improved in Spark memory, this paper proposes an NVM-based Spark memory optimization method. Add NVM to the Spark memory system, build a hybrid storage structure of NVM and memory, and make the partition management for NVM storage. What’s more, add some new persistence levels and optimize RDDs and other vital data. In the end, make the related optimization for cache and recovery.
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Haywood Dadzie, Thomas, Jiwon Lee, Jihye Kim, and Hyunok Oh. "NVM-Shelf: Secure Hybrid Encryption with Less Flip for Non-Volatile Memory." Electronics 9, no. 8 (August 13, 2020): 1304. http://dx.doi.org/10.3390/electronics9081304.
Анотація:
The Non-Volatile Memory (NVM), such as PRAM or STT-MRAM, is often adopted as the main memory in portable embedded systems. The non-volatility triggers a security issue against physical attacks, which is a vulnerability caused by memory extraction and snapshots. However, simply encrypting the NVM degrades the performance of the memory (high energy consumption, short lifetime), since typical encryption causes an avalanche effect while most NVMs suffer from the memory-write operation. In this paper, we propose NVM-shelf: Secure Hybrid Encryption with Less Flip (shelf) for Non-Volatile Memory (NVM), which is hybrid encryption to reduce the flip penalty. The main idea is that a stream cipher, such as block cipher CTR mode, is flip-tolerant when the keystream is reused. By modifying the CTR mode in AES block cipher, we let the keystream updated in a short period and reuse the keystream to achieve flip reduction while maintaining security against physical attacks. Since the CTR mode requires additional storage for the nonce, we classify write-intensive cache blocks and apply our CTR mode to the write-intensive blocks and apply the ECB mode for the rest of the blocks. To extend the cache-based NVM-shelf implementation toward SPM-based systems, we also propose an efficient compiler for SA-SPM: Security-Aware Scratch Pad Memory, which ensures the security of main memories in SPM-based embedded systems. Our compiler is the first approach to support full encryption of memory regions (i.e., stack, heap, code, and static variables) in an SPM-based system. By integrating the NVM-shelf framework to the SA-SPM compiler, we obtain the NVM-shelf implementation for both cache-based and SPM-based systems. The cache-based experiment shows that the NVM-shelf achieves encryption flip penalty less than 3%, and the SPM-based experiment shows that the NVM-shelf reduces the flip penalty by 31.8% compared to the whole encryption.
7
Jung, Myoungsoo, Ellis H. Wilson, Wonil Choi, John Shalf, Hasan Metin Aktulga, Chao Yang, Erik Saule, Umit V. Catalyurek, and Mahmut Kandemir. "Exploring the Future of Out-of-Core Computing with Compute-Local Non-Volatile Memory." Scientific Programming 22, no. 2 (2014): 125–39. http://dx.doi.org/10.1155/2014/303810.
Анотація:
Drawing parallels to the rise of general purpose graphical processing units (GPGPUs) as accelerators for specific high-performance computing (HPC) workloads, there is a rise in the use of non-volatile memory (NVM) as accelerators for I/O-intensive scientific applications. However, existing works have explored use of NVM within dedicated I/O nodes, which are distant from the compute nodes that actually need such acceleration. As NVM bandwidth begins to out-pace point-to-point network capacity, we argue for the need to break from the archetype of completely separated storage. Therefore, in this work we investigate co-location of NVM and compute by varying I/O interfaces, file systems, types of NVM, and both current and future SSD architectures, uncovering numerous bottlenecks implicit in these various levels in the I/O stack. We present novel hardware and software solutions, including the new Unified File System (UFS), to enable fuller utilization of the new compute-local NVM storage. Our experimental evaluation, which employs a real-world Out-of-Core (OoC) HPC application, demonstrates throughput increases in excess of an order of magnitude over current approaches.
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Bittman, Daniel, Peter Alvaro, Pankaj Mehra, Darrell D. E. Long, and Ethan L. Miller. "Twizzler: A Data-centric OS for Non-volatile Memory." ACM Transactions on Storage 17, no. 2 (June 7, 2021): 1–31. http://dx.doi.org/10.1145/3454129.
Анотація:
Byte-addressable, non-volatile memory (NVM) presents an opportunity to rethink the entire system stack. We present Twizzler, an operating system redesign for this near-future. Twizzler removes the kernel from the I/O path, provides programs with memory-style access to persistent data using small (64 bit), object-relative cross-object pointers, and enables simple and efficient long-term sharing of data both between applications and between runs of an application. Twizzler provides a clean-slate programming model for persistent data, realizing the vision of Unix in a world of persistent RAM. We show that Twizzler is simpler, more extensible, and more secure than existing I/O models and implementations by building software for Twizzler and evaluating it on NVM DIMMs. Most persistent pointer operations in Twizzler impose less than 0.5 ns added latency. Twizzler operations are up to faster than Unix , and SQLite queries are up to faster than on PMDK. YCSB workloads ran 1.1– faster on Twizzler than on native and NVM-optimized SQLite backends.
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Bez, Roberto, Emilio Camerlenghi, and Agostino Pirovano. "Materials and Processes for Non-Volatile Memories." Materials Science Forum 608 (December 2008): 111–32. http://dx.doi.org/10.4028/www.scientific.net/msf.608.111.
Анотація:
The development of the semiconductor industry through the CMOS technology has been possible thanks to the unique properties of the silicon and silicon dioxide material. Nevertheless the continuous scaling of the device dimension and the increase of the integration level, i.e. the capability to follow for more than 20 years the so-called Moore’s law, has been enabled not only by the Si-SiO2 system, but also by the use of other materials. The introduction of new materials every generation has allowed the integration of sub-micron and now of nanometer scale devices: different types of dielectrics, like Si3N4 or doped-SiO2, to form spacer, barrier and separation layers; conductive films, like WSi2, TiSi2, CoSi2 and NiSi2, to build low resistive gates; metals, like W, Ti, TiN, to have low resistive contacts, or like Al or Cu, to have low resistive interconnects. Although the technology development has been mainly driven by the CMOS transistor downscaling, other devices and most of all Non-Volatile Memories (NVM) have been able to evolve due to the large exploitation of these materials. NVM today represent a large portion of the overall semiconductor market and one of the most important technologies for the mobile application segment. In particular the main technology line in the NVM field is represented by the Flash Memory. Flash memory cell is based on the concept of a MOS transistor with a Floating-Gate (FG). The writing/reading operations of the cell are possible thanks again to the unique properties of the SiO2 system, being a quasi-ideal dielectric at low electric field, enabling the Flash memory to store electrons for several years, and becoming a fair conductor at higher electric field by tunnel effect, thus allowing reaching fast programming speeds. Flash have now reached the integration of many billions of bits in one monolithic component with cell dimension of 0.008um2 at 45nm technology node, always based on the FG concept. Nevertheless Flash have technological and physical constraint that will make more difficult their further scaling, even if the scaling limits are still under debate. In this contest there is the industrial interest for alternative technologies that exploit new materials and concepts to go beyond the Flash technology, to allow better scaling, and to enlarge the memory performance. Hence other technologies, alternative to floating gate devices, have been proposed and are under investigation. These new proposals exploit different physical mechanisms and different materials to store the information: magnetism and magnetoresistive materials (e.g. Co, Ni, Fe, Mn) in magnetic memories or MRAM; ferroelectricity and perovskite materials (e.g. PbTixZr1-xO3 or SrBi2Ta2O9 or BaxSr1-xTiO3) in ferroelectric memories or FeRAM; phase change and chalcogenide materials (e.g. Ge2Sb2Te5 or AsInSbTe) in phase-change memory or PCM. Among these alternative NVM, PCM are one of the most promising candidates to become a mainstream NVM, having the potentiality to improve the performance compared to Flash - random access time, read throughput, direct write, bit granularity, endurance - as well as to be scalable beyond Flash technology.
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Wang, Ming Qian, Jie Tao Diao, Nan Li, Xi Wang, and Kai Bu. "A Study on Reconfiguring On-Chip Cache with Non-Volatile Memory." Applied Mechanics and Materials 644-650 (September 2014): 3421–25. http://dx.doi.org/10.4028/www.scientific.net/amm.644-650.3421.
Анотація:
NVM has become a promising technology to partly replace SRAM as on-chip cache and reduce the gap between the core and cache. To take all advantages of NVM and SRAM, we propose a Hybrid Cache, constructing on-chip cache hierarchies with different technologies. As shown in article, hybrid cache performance and power consumption of Hybrid Cache have a large advantage over caches base on single technologies. In addition, we have shown some other methods that can optimize the performance of hybrid cache.
Дисертації з теми "Mémoire non volatile, NVM":
1
Jovanovic, Natalija. "Bascules et registres non-volatiles à base de ReRAM en technologies CMOS avancées." Thesis, Paris, ENST, 2016. http://www.theses.fr/2016ENST0023.
Анотація:
Les mémoires et l'éléments séquentiels non-volatiles peuvent améliorer l'efficacité énergétique des appareils à piles en éliminant la consommation statique tout en maintenant l'état du système.Parmi les nouvelles technologies NVM intégrées, ReRAMs se distinguent par un temps de programmation rapide, une structure simple, compatible avec la technologie CMOS et très bien scalable. Les flip-flops non-volatiles (NVFF) basées sur ReRAM ont été implémentées dans des nœuds CMOS de 90nm ou plus et souffrent de problèmes de fiabilité dans les nœuds plus petits, en raison de hautes tensions de programmation et de formation. Cette thèse fait l'analyse de la conception robuste et fiable non volatile dans le nœud CMOS 28nm et ci-dessous. Elle présente deux nouvelles solutions de conception pour la programmation de dispositifs ReRAM. Les circuits de programmation sont appliqués en architecture NVFF qui utilise deux dispositifs ReRAM (2R). Une architecture alternative (1R) est également proposée afin d'obtenir une densité plus élevée et une consommation plus faible. Les solutions NVFF sont optimisées pour les conditions de programmation ReRAM qui améliorent l'endurance et minimisent la puissance necessaire pour la programmation. L'analyse statistique de la structure du FF et de son optimisation a été réalisée, afin d'évaluer les meilleures architectures de fonctionnement de restauration. Les NVFF sont implémentés en FDSOI CMOS 28nm et comparés à un FF d'une bibliothèque standard. Enfin, pour minimiser la surcharge de la zone NVFF sans affecter la robustesse des opérations non volatiles, un Fichier de registres non-volatils multi-ports (NVRF) basé sur la solution 1R NVFF est proposéNon-volatile memories and flip-flops can improve the energy efficiency in battery-operated devices by eliminating the sleep-mode consumption, while maintaining the system state. Among emerging embedded NVM technologies, ReRAMs differentiate itself with a fast programming time, a simple CMOS-compatible structure and a good scalability. Previously proposed ReRAM-based non-volatile flip-flops (NVFF) have been implemented in 90nm or older CMOS nodes and suffer from CMOS reliability issues in scaled nodes due to high programming and forming voltages. This thesis makes the analysis of robust and reliable non-volatile design in 28nm CMOS node and below. It presents two novel thin-gate oxide CMOS design solutions for the programming of ReRAM devices. The programming circuits are applied in dual-voltage NVFF architecture which employs two ReRAM devices (2R). Alternative 1R NVFF architecture is also proposed in order to achieve higher density and lower consumption. With regard to the existing ReRAM technologies, given NVFF solutions are optimized for ReRAM programming conditions which improve endurance and minimize programming power. Statistical analysis of the FF core and its optimization was performed, to evaluate the best restore operation architectures which meet digital CMOS circuit design yield requirements. The NVFFs are implemented in 28nm CMOS FDSOI and benchmarked against a master slave flip-flop from a standard library and a data-retention flip-flop. Finally, to minimize the NVFF area overhead without impacting the robustness of \nv{} operations, multi-port non-volatile register file (NVRF) based on the 1R NVFF solution is proposed
2
Innocenti, Jordan. "Conception et procédés de fabrication avancés pour l’électronique ultra-basse consommation en technologie CMOS 80 nm avec mémoire non volatile embarquée." Thesis, Nice, 2015. http://www.theses.fr/2015NICE4142/document.
Анотація:
L’accroissement du champ d’application et de la performance des microcontrôleurs s’accompagne d’une augmentation de la puissance consommée limitant l’autonomie des systèmes nomades (smartphones, tablettes, ordinateurs portables, implants biomédicaux, …). L’étude menée dans le cadre de la thèse, consiste à réduire la consommation dynamique des circuits fabriqués en technologie CMOS 80 nm avec mémoire non-volatile embarquée (e-NVM) ; à travers l’amélioration des performances des transistors MOS. Pour augmenter la mobilité des porteurs de charge, des techniques de fabrication utilisées dans les nœuds les plus avancés (40 nm, 32 nm) sont d’abord étudiées en fonction de différents critères (intégration, coût, gain en courant/performance). Celles sélectionnées sont ensuite optimisées et adaptées pour être embarquées sur une plate-forme e-NVM 80 nm. L’étape suivante est d’étudier comment transformer le gain en courant, en gain sur la consommation dynamique, sans dégrader la consommation statique. Les approches utilisées ont été de réduire la tension d’alimentation et la largeur des transistors. Un gain en consommation dynamique supérieur à 20 % est démontré sur des oscillateurs en anneau et sur un circuit numérique conçu avec près de 20 000 cellules logiques. La méthodologie appliquée sur le circuit a permis de réduire automatiquement la taille des transistors (évitant ainsi une étape de conception supplémentaire). Enfin, une dernière étude consiste à optimiser la consommation, les performances et la surface des cellules logiques à travers des améliorations de conception et une solution permettant de réduire l’impact de la contrainte induite par l’oxyde STIThe increase of the scope of application and the performance of microcontrollers is accompanied by an increase in power consumption reducing the life-time of mobile systems (smartphones, tablets, laptops, biomedical implants, …). Here, the work consists of reducing the dynamic consumption of circuits manufactured in embedded non-volatile memories (e-NVM) CMOS 80 nm technology by improving the performance of MOS transistors. In order to increase the carriers’ mobility, manufacturing techniques used in the most advanced technological nodes (40 nm, 32 nm) are firstly studied according to different criteria (process integration, cost, current/performance gain). Then, selected techniques are optimized and adapted to be used on an e-NVM technological platform. The next step is to study how to transform the current gain into dynamic power gain without impacting the static consumption. To do so, the supply voltage and the transistor widths are reduced. Up to 20 % in dynamic current gain is demonstrated using ring oscillators and a digital circuit designed with 20,000 standard cells. The methodology applied on the circuit allows automatic reduction to all transistor widths without additional design modifications. Finally, a last study is performed in order to optimize the consumption, the performance and the area of digital standard cells through design improvements and by reducing the mechanical stress of STI oxide
3
Barlas, Marios Dimitrios. "Development and characterization of innovative nonvolatile OxRAM memory cells compatible with advanced nodes." Thesis, Aix-Marseille, 2019. http://www.theses.fr/2019AIXM0229.
Анотація:
La mémoire résistive à la base des oxydes de transition métallique (ReRAM) est une classe de technologies de mémoire non volatile dans lesquelles la commutation entre états de mémoire est rendue possible par la décomposition réversible de l’oxyde au moyen de la création et de la dissolution d’un chemin de percolation (filament). Les principaux avantages de cette technologie résident dans l’évolutivité de la cellule de mémoire, principalement en raison de la dimension inférieure à 10 nm du filament, de sa faible consommation d’énergie (<300 pJ / commutateur) et de la compatibilité des matériaux avec la technologie CMOS avancée. Néanmoins, deux obstacles majeurs ont jusqu'à présent empêché la mise en œuvre de ReRAM dans les réseaux de grande taille: premièrement, la nécessité d'une tension de claquage initiale supérieure à la tension de fonctionnement et, deuxièmement, les composantes de variabilité intrinsèque et extrinsique résultant de l'interaction des matériaux à son environnement ainsi qu’à la nature stochastique fondamentale de la conduction percolative. Ce travail est axé sur la technologie ReRAM à base de HfO2. D'abord, des alliages d'HfO2 sont étudiés. Dans la seconde partie, l’alliage HfSiOx proposé est intégré dans le BEOL d’un procédé de 130 nm et l’impact de l’intégration de la zone de commutation dans la formation, la commutation, l’évolution du taux d’erreur et la conservation des données est étudié. Dans la dernière partie, une intégration basée sur HfO2 dans le MOL ancien d’un processus CMOS FDSOI 300 mm avancé est étudiée, qui étudie les performances et les limitations standard de HfO2 ReRAMTransition Metal Oxide ReRAM is a class of non-volatile memory technologies where the switching between memory states is enabled by the reversible breakdown of the oxide by means of the creation and dissolution of a percolation path (filament). The main advantages of the technology lie in the scalability of the memory cell –mainly owed to the sub 10nm dimension of the filament, its low power consumption (< 300 pJ/ switch) and material compatibility to advanced CMOS. Nevertheless, there are two major roadblocks that have prevented so far the implementation of ReRAM in large arrays: first, the requirement for an initial breakdown happening voltages significantly higher than the operating voltage range and second, the intrinsic and extrinsic variability components arising from material interaction to its environment as well as the fundamental stochastic nature of percolative conduction. This work, is focused on HfO2 based ReRAM technology. In the first part, we investigate different dopants to engineer the conductive properties of HfO2 by combining a first-principles approach and in-depth material characterization techniques. In the second part, the proposed HfSiOx alloy is integrated in the BEOL of a 130nm process and the impact of the integration of the switching zone in forming, switching, error rate evolution and data retention is investigated. In the last part, a HfO2 based integration in the early MOL of an advanced FDSOI 300mm CMOS process is demonstrated investigating standard HfO2 ReRAM performances and limitations
4
Chatzistergiou, Andreas. "Library support for historical and persistent data structures in non-volatile memories." Thesis, University of Edinburgh, 2016. http://hdl.handle.net/1842/25797.
Анотація:
In the context of emerging non-volatile memory (NVM) where data structures can persist in-memory and are accessed through CPU loads and stores, we study how to efficiently manage data evolution. This is an extensively applied problem in both the scientific and business domains and is rapidly becoming an important component for a wider range of applications. We argue that the best way to achieve a smoother transition to the new programming model is to design a solution that is non-intrusive and generic i.e. not bound to a specific data model. We propose a novel library-level approach where the user can manage historical data directly from programming language code. This is achieved with a combination of two software layers: REWIND and VARIANT. At the bottom, lies REWIND (REcovery Write-Ahead System for In- Memory Non-Volatile Data Structures) which handles the low level specifics of NVM by dealing with write-ordering problems that arise in such context and allows recoverability of arbitrary data structures. Then, VARIANT (Versioning ARbItrary dAta structures in Non-volatile memory for Time-travel) focuses on versioning and time travel (moving between versions). We adopt a logging approach and we tightly integrate both systems for best performance by utilizing a common physical log of memory operations. With REWIND, we propose a novel recoverable log structure that permits atomic and durable appends and removals of log records. This is the keystone for building recoverable systems on top of NVM. Because latencies in recent NVM technologies such as Phase-change memory (PCM) are asymmetric, we propose novel techniques for reducing the write pressure of the recoverable log as well as mitigating the effect of synchronization control primitives such as memory fences (enhanced for NVM), i.e. barriers that enforce ordering and persistence to preceding instructions. We also propose different implementations for trading logging performance for rollback performance when this is appropriate. Finally, we revisit state-of-the-art recovery algorithms for the new context given the different latencies and synchronization control. Our results clearly indicate that current approaches for recoverability are ill-fitted for persisting data structures in the new context and it is possible to achieve low-overhead logging with customized mechanisms. Next, we focus on data evolution. We expose a simple API that allows versioning and time travel with minimal intrusiveness. We propose mechanisms for efficient and transparent cloning of Versionable data structures. This allows high concurrency since past images are returned as copies of the original data structure which remains intact. Then, we propose novel indexing techniques that significantly improve time travel performance as well as cloning with lazy schemes. We achieve a low overhead architecture by employing a mix of volatile and non-volatile data structures as well as hybrid structures that reside in both volatile and non-volatile memories. We perform an extensive evaluation of the proposed techniques and conclude that, in our context, by carefully mitigating the drawbacks of physical logging it is possible to create efficient systems for managing data evolution that are both data structure agnostic and non-intrusive.
5
Guilmain, Marc. "Fabrication de mémoire monoélectronique non volatile par une approche de nanogrille flottante." Thèse, Université de Sherbrooke, 2013. http://hdl.handle.net/11143/6127.
Анотація:
Les transistors monoélectroniques (SET) sont des dispositifs de tailles nanométriques qui permettent la commande d'un électron à la fois et donc, qui consomment peu d'énergie. Une des applications complémentaires des SET qui attire l'attention est son utilisation dans des circuits de mémoire. Une mémoire monoélectronique (SEM) non volatile a le potentiel d'opérer à des fréquences de l'ordre des gigahertz ce qui lui permettrait de remplacer en même temps les mémoires mortes de type FLASH et les mémoires vives de type DRAM. Une puce SEM permettrait donc ultimement la réunification des deux grands types de mémoire au sein des ordinateurs. Cette thèse porte sur la fabrication de mémoires monoélectroniques non volatiles. Le procédé de fabrication proposé repose sur le procédé nanodamascène développé par C. Dubuc et al. à l'Université de Sherbrooke. L'un des avantages de ce procédé est sa compatibilité avec le back-end-of-line (BEOL) des circuits CMOS. Ce procédé a le potentiel de fabriquer plusieurs couches de circuits mémoirestrès denses au-dessus de tranches CMOS. Ce document présente, entre autres, la réalisation d'un simulateur de mémoires monoélectroniques ainsi que les résultats de simulations de différentes structures. L'optimisation du procédé de fabrication de dispositifs monoélectroniques et la réalisation de différentes architectures de SEM simples sont traitées. Les optimisations ont été faites à plusieurs niveaux : l'électrolithographie, la gravure de l'oxyde, le soulèvement du titane, la métallisation et la planarisation CMP. La caractérisation électrique a permis d'étudier en profondeur les dispositifs formés de jonction de Ti/TiO2 et elle a démontré que ces matériaux ne sont pas appropriés. Par contre, un SET formé de jonction de TiN/Al2 O3 a été fabriqué et caractérisé avec succès à basse température. Cette démonstration démontre le potentiel du procédé de fabrication et de la déposition de couche atomique (ALD) pour la fabrication de mémoires monoélectroniques.[symboles non conformes]
6
Bossu, Germain. "Architectures innovantes de mémoire non-volatile embarquée sur film mince de silicium." Aix-Marseille 1, 2009. http://www.theses.fr/2009AIX11044.
Анотація:
Les plateformes CMOS s’orientent vers l’utilisation de film mince de silicium pour faire face aux effets parasites qui limitent la miniaturisation du transistor sur substrat massif. Cette configuration technologique ouvre la porte à de nouvelles architectures de dispositifs mémoire non-volatile. L’étude réalisée au cours de cette thèse porte sur l’adaptation des technologies film mince pour obtenir des mémoires non-volatile embarquées denses fonctionnant à la tension nominale du circuit pour une co-intégration aisée sur les plateformes technologiques CMOS Bulk et film mince. La construction de la cellule SQeRAM, tout d’abord proposée, repose sur la séquence de procédés de fabrication de la technologie Silicon-On-Nothing (SON) additionnées au core process CMOS bulk. Le point mémoire obtenu présente un stockage de charge sur l¿interface opposée au canal de conduction. Cette mémoire est quasi-non-volatile, du fait de l’empilement ONO (Oxyde Nitrure Oxyde) mince requis pour un fonctionnement à seulement 3 V d’alimentation. Un modèle semi-analytique de transistor film mince à double grille indépendante (IDG) est explicité. En associant ce modèle IDG à celui d’un transistor Bulk, les phénomènes physiques en jeu dans la SQeRAM sont détaillés. Cette modélisation permet aussi l’optimisation technologique en vue des applications double-bit. Les limites à la miniaturisation de la SQeRAM, en particulier la maîtrise de la technologie, m’ont conduit à envisager un point mémoire non-volatile construit sur le seul transistor IDG. Le concept, la réalisation et les spécificités de cette architecture sont présentés. L’étude modèle associée permet une discussion sur les mécanismes physiques en jeu et analyse les principales caractéristiques électriques du dispositif suivant la densité de charge piégée. Enfin ce manuscrit de thèse préfigure une nouvelle forme de mémoire universelle hybride combinant le stockage non-volatile et l’utilisation du substrat flottant pour les applications 1T-DRAM sur des structures sur film mince de siliciumCMOS platforms are heading silicon thin film to face parasitic effects blocking bulk transistor scaling. This technological option is opening the way of new non-volatile memory device architectures. This PhD study deals with thin film technology tuning to turn into dense embedded non-volatile memory working with standard circuit power supply for an easy co-integration on bulk and thin film CMOS platforms. The first proposed SQeRAM cell is based on Silicon-On-Nothing technology process flow added to bulk CMOS core process. The resulting memory point presents charges stored at the opposite interface of inversion layer. This memory device is quasi-non-volatile due to a thin ONO stack allowing 3V only power supply. A semi-analytical model is developed to describe Independent Double Gate transistor considering electrons, holes and doping level. By the association of this approach with a charge-sheet Bulk transistor model, SQeRAM physical phenomena are detailed. In addition technological optimization is discussed to allow double-bit applications. SQeRAM scaling limitations, particularly technological process control, leads me to imagine another new non-volatile memory point built on a pure thin film IDG transistor. Concept, realization and specificities are described. The associated model developed drives physical mechanisms analysis of the main electrical characteristics versus trapped charge density. At last my PhD thesis brings up the guidelines of a new hybrid memory based on silicon thin film device combining non-volatile storage and floating body properties of the 1T-DRAM
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Nail, Cécile. "Etude de mémoire non-volatile hybride CBRAM OXRAM pour faible consommation et forte fiabilité." Thesis, Université Grenoble Alpes (ComUE), 2018. http://www.theses.fr/2018GREAT010/document.
Анотація:
À mesure que les technologies de l'information (IT) continuent de croître, les dispositifs mémoires doivent évoluer pour répondre aux exigences du marché informatique. De nos jours, de nouvelles technologies émergent et entrent sur le marché. La mémoire Resistive Random Access Memory (RRAM) fait partie de ces dispositifs émergents et offre de grands avantages en termes de consommation d'énergie, de performances, de densité et la possibilité d'être intégrés en back-end. Cependant, pour être compétitif, certains problèmes doivent encore être surmontés en particulier en ce qui concerne la variabilité, la fiabilité et la stabilité thermique de la technologie. Leur place sur le marché des mémoires est encore indéfinie. En outre, comme le principe de fonctionnement des RRAM dépend des matériaux utilisés et doit être observé à la résolution nanométrique, la compréhension du mécanisme de commutation est encore difficile. Cette thèse propose une analyse du principe de fonctionnement microscopique des CBRAM à base d'oxyde basé sur des résultats de caractérisation électrique et de simulation atomistique. Une interdépendance entre les performances électriques des RRAM et certains paramètres matériaux est étudiée, indiquant de nouveaux paramètres à prendre en compte pour atteindre les spécifications d'une application donnéeAs Information Technologies (IT) are still growing, memory devices need to evolve to answer IT market demands. Nowadays, new technologies are emerging and are entering the market. Resistive Random Access Memory (RRAM) are part of these emerging devices and offer great advantages in terms of power consumption, performances, density and the possibility to be integrated in the back end of line. However, to be competitive, some roadblocks still have to be overcome especially regarding technology variability, reliability and thermal stability. Their place on memory market is then still undefined. Moreover, as RRAM working principle depends on stack materials and has to be observed at nanometer resolution, switching mechanism understanding is still challenging. This thesis proposes an analysis of oxide-based CBRAM microscopic working principle based on electrical characterization results and atomistic simulation. Then, an interdependence between RRAM electrical performances as well as material parameters is studied to point out new parameters that can be taken into account to target specific memory applications
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Puglia, Gianlucca Oliveira. "Exploring atomicity on memory mapped files based on non-volatile memory file systems." Pontif?cia Universidade Cat?lica do Rio Grande do Sul, 2017. http://tede2.pucrs.br/tede2/handle/tede/7768.
Анотація:
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As tecnologias de mem?rias n?o-vol?teis s?o uma grande promessa na ?rea de arquitetura de computadores e ? esperado que sejam poderosas ferramentas para solucionar os problemas referentes a manipula??o eficiente de dados dos dias de hoje. Estas tecnologias prov?m alta performance e acesso em granularidade de bytes com a distinta vantagem de serem persistentes. Por?m, afim de explorar estas tecnologias em todo seu potencial, os sistemas e arquiteturas de hoje precisam buscar meios de se adaptar a esta nova forma de acessar dados e de superar os desafios que v?m com ela.Trabalhos existentes na ?rea j? prop?em m?todos para adaptar as arquiteturas existentes para o uso de NVM bem como formas inovadoras de empregar estas mem?rias em futuras aplica??es. No entanto, o suporte dos sistemas operacionais a estas solu??es, ainda que existente, ainda ? muito limitado. Neste trabalho, n?s apresentamos duas varia??es da chamada de sistema msync, modeladas para explorar as caracter?sticas das tecnologias de NVM e garantir consist?ncia para os dados dos usu?rios. Ambas s?o solu??es simples que permitem aos usu?rios definirem checkpoints de seus arquivos usando a sintaxe comum de sistemas de arquivos. N?s implementamos e testamos estes m?todos sobre o sistema operacional Linux utilizando como base um sistema de arquivo nativamente voltado a NVM. Nossos resultados mostram que estes mecanismos s?o capazes de garantir a integridade dos arquivos mesmo na presen?a de falhas no sistema enquanto mant?m uma performance razo?vel.
Upcoming non-volatile memory technologies are a big promise in computer architecture and are expected to be powerful tools to address today?s issues regarding efficient data manipulation. They provide high performance and byte granularity while also having the distinct advantage of being persistent. However in order to explore these technologies to their full potential, existing systems and architecture must adapt to this new way of working with data and workaround the challenges that come with it. Existing work in the area already proposes methods to adapt existing architecture to NVM as well as innovative ways to employ these memories in future applications. However operating system support to such NVM-enabled solutions, although existent, still very limited. In this work, we present two variations of the existing mmap system call, designed to both explore NVM characteristics and provide user data consistency. Both are very simple solutions that allow users to control the persistence and define checkpoints to their files while using the common mapped file syntax. We have implemented and tested these methods over Linux using a NVM file system as our base. Our results show that these mechanisms can ensure file integrity in the presence of system failures while also providing a reasonable performance.
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Yao, Thierry. "Modélisation et conception d'une mémoire non-volatile dédiée aux applications bas coût télé-alimentées." Paris, ENST, 2002. http://www.theses.fr/2002ENST0018.
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Delizy, Tristan. "Gestion de la mémoire dynamique pour les systèmes embarqués avec mémoire hétérogène." Thesis, Lyon, 2019. http://www.theses.fr/2019LYSEI134.
Анотація:
La réduction de la consommation énergétique des systèmes embarqué est un enjeu majeur de la réalisation de l'Internet des Objets. Les mémoires émergentes NVRAMs présentent notamment le potentiel de consommer peu et d'être denses, mais les différentes technologies souffrent encore de désavantages spécifiques comme une latence d'écriture élevée ou une faible endurance. Pour contrebalancer ces désavantages, les concepteurs de systèmes embarqués tendent à juxtaposer différentes technologies sur une même puce. Cette thèse s'intéresse aux interactions entre l'allocation mémoire dynamique et l'hétérogénéité mémoire. Notre objectif est de fournir au programmeur d'applications embarquées un mécanisme logiciel transparent pour exploiter cette hétérogénéité mémoire. Nous proposons un simulateur au cycle près de plateformes embarquées intégrant des technologies mémoire variées qui montre que les stratégies de placement des objets alloués dynamiquement ont un impact important. Nous montrons également que des gains intéressants peuvent être dégagés même avec une faible proportion de la mémoire utilisant une technologie à faible latence mais uniquement en utilisant une stratégie intelligente pour le placement entre les différentes banques mémoires. Nous fournissons une stratégie efficace basée sur le profilage de l'application dans notre simulateurReducing energy consumption is a key challenge to the realisation of the Internet of Things. While emerging memory technologies may offer power reduction and high integration density, they come with major drawbacks such as high latency or limited endurance. As a result, system designers tend to juxtapose several memory technologies on the same chip. We aim to provide the embedded application programmer with a transparent software mechanism to leverage this memory heterogeneity. This work studies the interaction between dynamic memory allocation and memory heterogeneity. We provide cycle accurate simulation of embedded platforms with various memory technologies and we show that different dynamic allocation strategies have a major impact on performance. We demonstrates that interesting performance gains can be achieved even for a low fraction of memory using low latency technology, but only with a clever placement strategy between memory banks. We propose an efficient strategy based on application profiling in our simulator
Частини книг з теми "Mémoire non volatile, NVM":
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Dimitrakis, Panagiotis. "Introduction to NVM Devices." In Charge-Trapping Non-Volatile Memories, 1–36. Cham: Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-15290-5_1.
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Yu, Hao, and Yuhao Wang. "Fundamentals of NVM Physics and Computing." In Design Exploration of Emerging Nano-scale Non-volatile Memory, 29–44. New York, NY: Springer New York, 2014. http://dx.doi.org/10.1007/978-1-4939-0551-5_2.
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Yu, Hao, and Yuhao Wang. "Nonvolatile State Identification and NVM SPICE." In Design Exploration of Emerging Nano-scale Non-volatile Memory, 45–83. New York, NY: Springer New York, 2014. http://dx.doi.org/10.1007/978-1-4939-0551-5_3.
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Khyzha, Artem, and Ori Lahav. "Abstraction for Crash-Resilient Objects." In Programming Languages and Systems, 262–89. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-030-99336-8_10.
Анотація:
AbstractWe study abstraction for crash-resilient concurrent objects using non-volatile memory (NVM). We develop a library-correctness criterion that is sound for ensuring contextual refinement in this setting, thus allowing clients to reason about library behaviors in terms of their abstract specifications, and library developers to verify their implementations against the specifications abstracting away from particular client programs. As a semantic foundation we employ a recent NVM model, called Persistent Sequential Consistency, and extend its language and operational semantics with useful specification constructs. The proposed correctness criterion accounts for NVM-related interactions between client and library code due to explicit persist instructions, and for calling policies enforced by libraries. We illustrate our approach on two implementations and specifications of simple persistent objects with different prototypical durability guarantees. Our results provide the first approach to formal compositional reasoning under NVM.
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Butterfield, N. R., R. Mays, B. Khan, R. Gudlavalleti, and F. C. Jain. "Quantum Dot Gate (QDG) Quantum Dot Channel (QDC) Multistate Logic Non-Volatile Memory (NVM) with High-K Dielectric HfO2 Barriers." In Selected Topics in Electronics and Systems, 1–12. WORLD SCIENTIFIC, 2021. http://dx.doi.org/10.1142/9789811242823_0001.
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Wu, Xiaohan, Ruijing Ge, Deji Akinwande, and Jack C. Lee. "Memristors Based on 2D Monolayer Materials." In Memristor - An Emerging Device for Post-Moore’s Computing and Applications. IntechOpen, 2021. http://dx.doi.org/10.5772/intechopen.98331.
Анотація:
2D materials have been widely used in various applications due to their remarkable and distinct electronic, optical, mechanical and thermal properties. Memristive effect has been found in several 2D systems. This chapter focuses on the memristors based on 2D materials, e. g. monolayer transition metal dichalcogenides (TMDs) and hexagonal boron nitride (h-BN), as the active layer in vertical MIM (metal–insulator–metal) configuration. Resistive switching behavior under normal DC and pulse waveforms, and current-sweep and constant stress testing methods have been investigated. Unlike the filament model in conventional bulk oxide-based memristors, a new switching mechanism has been proposed with the assistance of metal ion diffusion, featuring conductive-point random access memory (CPRAM) characteristics. The use of 2D material devices in applications such as flexible non-volatile memory (NVM) and emerging zero-power radio frequency (RF) switch will be discussed.
Тези доповідей конференцій з теми "Mémoire non volatile, NVM":
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Brewer, J. E. "NVM in the far term." In 2005 Non-Volatile Memory Technology Symposium. IEEE, 2005. http://dx.doi.org/10.1109/nvmt.2005.1541374.
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Lindstrom, Jan, Dhananjoy Das, Torben Mathiasen, Dulcardo Arteaga, and Nisha Talagala. "NVM aware MariaDB database system." In 2015 IEEE Non-Volatile Memory System and Applications Symposium (NVMSA). IEEE, 2015. http://dx.doi.org/10.1109/nvmsa.2015.7304362.
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Bu, Jiankang, William Belcher, Courtney Parker, and Hank Prosack. "Unique Challenges and Solutions in CMOS Compatible NVM." In 2006 7th Annual Non-Volatile Memory Technology Symposium. IEEE, 2006. http://dx.doi.org/10.1109/nvmt.2006.378876.
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Li, Shuangchen, Ping Chi, Jishen Zhao, Kwang-Ting Cheng, and Yuan Xie. "Leveraging nonvolatility for architecture design with emerging NVM." In 2015 IEEE Non-Volatile Memory System and Applications Symposium (NVMSA). IEEE, 2015. http://dx.doi.org/10.1109/nvmsa.2015.7304356.
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Park, Sung-Kun, Nam-Yoon Kim, Kwang-il Choi, Jae-Gwan Kim, In-Wook Cho, Kyung-Dong Yoo, Eun-Mee Kwon, and Sang-Yong Kim. "Characteristics comparison of standard logic and HVCMOS processed SGLC embedded NVM." In 2014 14th Non-Volatile Memory Technology Symposium (NVMTS). IEEE, 2014. http://dx.doi.org/10.1109/nvmts.2014.7060858.
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Bayram, Ismail, and Yiran Chen. "NV-TCAM: Alternative interests and practices in NVM designs." In 2014 IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA). IEEE, 2014. http://dx.doi.org/10.1109/nvmsa.2014.6927206.
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Choi, Gunhee, Seungboo Kim, and Jongmoo Choi. "Quantitative Analysis of File System Performance on NVM." In 2018 IEEE 7th Non-Volatile Memory Systems and Applications Symposium (NVMSA). IEEE, 2018. http://dx.doi.org/10.1109/nvmsa.2018.00027.
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Duan, Hongwei, Liang Shi, Qingfeng Zhuge, Edwin Hsing-Mean Sha, Changlong Li, and Yujiong Liang. "An Empirical Study of NVM-based File System." In 2021 IEEE 10th Non-Volatile Memory Systems and Applications Symposium (NVMSA). IEEE, 2021. http://dx.doi.org/10.1109/nvmsa53655.2021.9628430.
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Ho, Yu Ting, Chun-Feng Wu, Ming-Chang Yang, Tseng-Yi Chen, and Yuan-Hao Chang. "Replanting Your Forest: NVM-friendly Bagging Strategy for Random Forest." In 2019 IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA). IEEE, 2019. http://dx.doi.org/10.1109/nvmsa.2019.8863525.
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Hakert, Christian, Kuan-Hsun Chen, Simon Kuenzer, Sharan Santhanam, Shuo-Han Chen, Yuan-Hao Chang, Felipe Huici, and Jian-Jia Chen. "Split'n Trace NVM: Leveraging Library OSes for Semantic Memory Tracing." In 2020 9th Non-Volatile Memory Systems and Applications Symposium (NVMSA). IEEE, 2020. http://dx.doi.org/10.1109/nvmsa51238.2020.9188136.