Thematische Bibliographien / A capacitance-to-voltage converter and a comparator

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  2. Dissertationen
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Auswahl der wissenschaftlichen Literatur zum Thema „A capacitance-to-voltage converter and a comparator“

Autor: Grafiati
Veröffentlicht am 9. September 2021
Zuletzt aktualisiert am 29. Juli 2025

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Zeitschriftenartikel zum Thema "A capacitance-to-voltage converter and a comparator"

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WAWRYN, KRZYSZTOF, ROBERT SUSZYNSKI, and BOGDAN STRZESZEWSKI. "A LOW POWER DIGITALLY ERROR CORRECTED 2.5 BIT PER STAGE PIPELINED A/D CONVERTER USING CURRENT-MODE SIGNALS." Journal of Circuits, Systems and Computers 20, no. 01 (2011): 29–43. http://dx.doi.org/10.1142/s0218126611007050.

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This paper, presents a novel low power current mode 9 bit pipelined a/d converter. The a/d converter structure is composed of three 2.5 bit stages and one 3 bit stage operating in current mode and a final comparator which converts the analog current signal into a digital voltage signal. All the building blocks of the converter were designed in CMOS AMS 0.35 μm technology, simulated, and then a prototype converter was manufactured and measured to verify the proposed concept. The performances of the converter are compared to performances of known voltage-mode switched-capacitance and current-mod
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Kulikov, V. A., V. N. Syakterev, and V. V. Syaktereva. "Application of Passive Time-to-Pulse Converter in Temperature Measurement Systems of Moving Objects." Intellekt. Sist. Proizv. 20, no. 4 (2022): 9–19. http://dx.doi.org/10.22213/2410-9304-2022-4-9-19.

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A variant of the implementation of a time-to-pulse converter as part of a human temperature measurement system is considered, in which a first-order circuit forming an information time interval is formed by a resistance temperature device and a capacitor. Initialization and registration of the time for the transient phenomena are carried out by MIS transistor and an integral comparator. Assessment of the differential sensibility of the converter depending on the time constant of the forming circuit for medium-speed keys is provided. The scheme of a multichannel converter is presented, with seq
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He, Xinyuan, Weifeng Qiao, Xinpeng Xing та Haigang Feng. "A Power-Efficient 16-bit 1-MS/s Successive Approximation Register Analog-to-Digital Converter with Digital Calibration in 0.18 μm Complementary Metal Oxide Semiconductor". Journal of Low Power Electronics and Applications 14, № 2 (2024): 32. http://dx.doi.org/10.3390/jlpea14020032.

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A power-efficient 16-bit 1-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) is presented in this paper. High-bit sampling makes the bridge capacitance in the digital-to-analog converter (DAC) a unit one, eliminating fractional capacitance mismatch. The high-precision comparator is composed of a four-stage preamplifier and a strong-arm latch, with auto-zeroing used to mitigate input offset further. Digital foreground calibration based on low-bit weight is implemented to correct DAC capacitance mismatch. The post-layout simulation results show that the core ADC achi
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M., Zahangir, Khan Sheroz, Adam I., Abdul Kadir K., N. Nordin A., and N. Ibrahim S. "A Proposed Resistance-to-Time Converter with Switching Impulse Calibrators for Application in Resistive Bridge Sensors." Indonesian Journal of Electrical Engineering and Computer Science 11, no. 1 (2018): 47–50. https://doi.org/10.11591/ijeecs.v11.i1.pp47-50.

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This paper presents a simple resistance-to-time converter. It consists of two voltage comparators, a ramp voltage generator, two logic gates and impulse voltage calibrators. A square-wave generator circuit is suggested in this paper. The design is simple and independent of the OPAMP offset issues. The resulting square-wave is rectified to get its DC equivalent and to a triangular output; the two outputs are applied to a comparator for generating a digital output with a duty cycle proportional to a change in resistance upon which is dependent the DC.
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Julie, Roslita Rusli, Shafie Suhaidi, Mohd Sidek Roslina, Abdul Majid Hasmayadi, Z. Wan Hassan W., and Mustafa M.A. "Optimized low voltage low power dynamic comparator robust to process, voltage and temperature variation." Indonesian Journal of Electrical Engineering and Computer Science (IJEECS) 17, no. 2 (2020): 783–92. https://doi.org/10.11591/ijeecs.v17.i2.pp783-792.

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Power consumption and speed are the main criteria in designing comparator for analog-to-digital converter (ADC). This paper presents an optimized low voltage low power dynamic comparator which is robust to process, voltage and temperature (PVT) variations with adequate speed. The comparator circuit was designed using 0.18µm CMOS technology with low voltage supply of 0.8V. The method used to verify the robustness of the comparator circuit across 45 PVT is presented. The circuit is simulated with 10% voltage supply variation, five process corners and temperature variation from 0°C to 1
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Liu, K., S. Fang, Y. Wang, and Z. Huang. "Development of a low-power SAR ADC for analog front-end readout circuit of hydrophones." Journal of Physics: Conference Series 2740, no. 1 (2024): 012044. http://dx.doi.org/10.1088/1742-6596/2740/1/012044.

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Abstract A low-power 16 bit 250KSa/s successive approximation analog-to-digital converter (SAR ADC) is designed. The capacitor array consists of a 2-segment sub-capacitor array and high sampling makes the coupling capacitance a unit capacitance, solving the problem of fractional capacitance mismatch. The power consumption is reduced by introducing a common-mode voltage during the switching process of the capacitor array. The circuit uses a 4-stage pre-amplifier and adds a dynamically latched comparator using output misalignment calibration to ensure high accuracy resolution. Simulated in DB Hi
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Priya, Nadendla Bindu, and Muralidharan Jayabhalan. "A 5 Bit 600MS/S Asynchronous Digital Slope ADC with Modified Strong Arm Comparator." International Journal of Engineering and Advanced Technology 9, no. 1s5 (2019): 41–43. http://dx.doi.org/10.35940/ijeat.a1012.1291s519.

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Strong arm comparator has some characteristics like it devours zero static power and yields rail to rail swing. It acquires a positive feedback allowed by two cross coupled pairs of comparators and results a low offset voltage in input differential stage. We modified a strong arm Comparator for high speed without relying on complex calibration Schemes. a 5-bit 600MS/s asynchronous digital slope analog to digital converter (ADS-ADC) with modified strong arm comparator designed in cadence virtuoso at 180nm CMOS technology. The design of SR-Latch using Pseudo NMOS NOR Gate optimizes the speed. Th
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Roslita Rusli, Julie, Suhaidi Shafie, Roslina Mohd Sidek, Hasmayadi Abdul Majid, W. Z. Wan Hassan, and M. A. Mustafa. "Optimized low voltage low power dynamic comparator robust to process, voltage and temperature variation." Indonesian Journal of Electrical Engineering and Computer Science 17, no. 2 (2020): 783. http://dx.doi.org/10.11591/ijeecs.v17.i2.pp783-792.

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Power consumption and speed are the main criteria in designing comparator for analog-to-digital converter (ADC). This paper presents an optimized low voltage low power dynamic comparator which is robust to process, voltage and temperature (PVT) variations with adequate speed. The comparator circuit was designed using 0.18µm CMOS technology with low voltage supply of 0.8V. The method used to verify the robustness of the comparator circuit across 45 PVT is presented. The circuit is simulated with 10% voltage supply variation, five process corners and temperature variation from 0°C to 100°C. The
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Gwóźdź, Michał. "Power Electronics Programmable Voltage Source with Reduced Ripple Component of Output Signal Based on Continuous-Time Sigma-Delta Modulator." Energies 14, no. 20 (2021): 6784. http://dx.doi.org/10.3390/en14206784.

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In this work, an idea of a wideband, precision, power electronics programmable voltage source (PVS) is presented. One of the basic elements of the converter, the control section, contains a continuous-time sigma-delta modulator (SDM) with a pair of interconnected complementary comparators, which represents a new approach. In this case, the SDM uses comparators with a dynamic hysteresis loop (DHC) that includes an AC circuit rather than an R-R network. Dynamic hysteresis is a very effective way of eliminating parasitic oscillation during the signal transition at the input of the comparator; it
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Faure, Nicolaas, and Saurabh Sinha. "High-speed Cherry Hooper flash analog-to-digital converter." Microelectronics International 34, no. 1 (2017): 22–29. http://dx.doi.org/10.1108/mi-08-2015-0075.

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Purpose The 60 GHz unlicensed band is being utilized for high-speed wireless networks with data rates in the gigabit range. To successfully make use of these high-speed signals in a digital system, a high-speed analog-to-digital converter (ADC) is necessary. This paper aims to present the use of a common collector (CC) input tree and Cherry Hooper (C-H) differential amplifier to enable analog-to-digital conversion at high frequencies. Design/methodology/approach The CC input tree is designed to separate the input Miller capacitance of each comparator stage. The CC stages are biased to obtain b
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Dissertationen zum Thema "A capacitance-to-voltage converter and a comparator"

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Nisar, Kashif. "DC to DC converter for smart dust." Thesis, Linköpings universitet, Institutionen för systemteknik, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-77247.

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This work describes the implementation of DC to DC converter for Smart Dust in 65 nm CMOS technology. The purpose of a DC to DC converter is to convert a battery voltage of 1 Vto a lower voltage of 0.5 V used by the processor. The topology used in this DC to DC converteris of Buck type which converts a higher voltage to lower voltage with the advantage of givinghigh efficiency about 75%. The system uses PWM (Pulse width modulation) technique. It usesnon-overlapping clock generation technique for reducing the power consumption. The systemprovides up to 5 mA load current and has power consumptio
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Wang, Mingzhen. "High-speed Low-voltage CMOS Flash Analog-to-Digital Converter for Wideband Communication System-on-a-Chip." Wright State University / OhioLINK, 2007. http://rave.ohiolink.edu/etdc/view?acc_num=wright1189815482.

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Zhang, Dai. "Design and Evaluation of an Ultra-Low Power Successive Approximation ADC." Thesis, Linköping University, Department of Electrical Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-18219.

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<p>Analog-to-digital converters (ADC) targeted for use in medical implant devices serve an important role as the interface between analog signal and digital processing system. Usually, low power consumption is required for a long battery lifetime. In such application which requires low power consumption and moderate speed and resolution, one of the most prevalently used ADC architectures is the successive approximation register (SAR) ADC.This thesis presents a design of an ultra-low power 9-bit SAR ADC in 0.13μm CMOS technology. Based on a literature review of SAR ADC design, the proposed SAR
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Miri, Lavasani Seyed Hossein. "Design and phase-noise modeling of temperature-compensated high frequency MEMS-CMOS reference oscillators." Diss., Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/41096.

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Frequency reference oscillator is a critical component of modern radio transceivers. Currently, most reference oscillators are based on low-frequency quartz crystals that are inherently bulky and incompatible with standard micro-fabrication processes. Moreover, their frequency limitation (<200MHz) requires large up-conversion ratio in multigigahertz frequency synthesizers, which in turn, degrades the phase-noise. Recent advances in MEMS technology have made realization of high-frequency on-chip low phase-noise MEMS oscillators possible. Although significant research has been directed toward r
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Kongpark, Patcharee. "Conditionnement de capteurs capacitifs dans des systèmes faible consommation." Thesis, Montpellier, 2016. http://www.theses.fr/2016MONTT251/document.

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De nos jours, les capteurs capacitifs sont largement utilisés dans la mesure de grandeurs physiques telles que le déplacement, l’humidité, la pression, etc. Cette large diffusion est principalement due au développement des technologies MEMS qui ont permis de réduire leur coût, leur taille et leur consommation. Pour mesurer ces variations de capacité, des interfaces de conditionnement électronique ont été développées afin d’obtenir un signal électrique exploitable tel qu’une tension, un courant, un temps, une fréquence ou directement une sortie numérique. C’est dans ce cadre que se positionne l
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Santos, Ângelo Emanuel Neves dos. "Design and simulation of a smart bottle with fill-level sensing based on oxide TFT technology." Master's thesis, 2016. http://hdl.handle.net/10362/19593.

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Packaging is an important element responsible for brand growth and one of the main rea-sons for producers to gain competitive advantages through technological innovation. In this re-gard, the aim of this work is to design a fully autonomous electronic system for a smart bottle packaging, being integrated in a European project named ROLL-OUT. The desired application for the smart bottle is to act as a fill-level sensor system in order to determine the liquid content level that exists inside an opaque bottle, so the consumer can exactly know the remaining quantity of the product inside. An in-h
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Buchteile zum Thema "A capacitance-to-voltage converter and a comparator"

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Mesbah, Fatima, Karim El Khadiri, Mohammed Ouazzani Jamil, et al. "Switching Power Supply Boost Converter Using 180 nm CMOS Technology." In Advances in Computational Intelligence and Robotics. IGI Global, 2024. http://dx.doi.org/10.4018/979-8-3693-3775-2.ch015.

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DC-DC (direct current) boost converters are used in a variety of applications, including battery packs for electric vehicles, power sources for white LEDs (light-emitting diode) and portable applications. This study offers a complete circuit design for a DC-DC boost converter using the cadence software for use in portable applications. The control circuits are composed of a bandgap, a voltage divider, a comparator, a ring oscillator, and a buffer. An inductor, Schottky diode, capacitor, and resistor serve as the load in the circuit's boost portion. This work discusses the design, simulation, a
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Kiran B., Raghu N., and Manjunatha K. N. "VLSI Implementation of a High-Speed Pipeline A/D Converter." In Role of 6G Wireless Networks in AI and Blockchain-Based Applications. IGI Global, 2023. http://dx.doi.org/10.4018/978-1-6684-5376-6.ch005.

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In very large-scale-integrated (VLSI) design, a challenge is to increase the speed without compromising the power consumption in an analog and mixed mode signal circuit. This research work is carried out to design a 12-bit pipeline A/D converter (ADC) of 400MS/s sampling rate to meet the high computing requirements. The design is focused to determine high speed and resolution in pipeline ADC to cater different applications. The main advantages of pipeline method are simple to implement, more flexible to improve the speed, and makes layout design simple. A proposed technique holds sample and ho
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Wu, Pan, Bingyang Liu, Xuefei Zhao, and Bo Gao. "Design and Simulation of the 16-bit SAR ADC." In Advances in Transdisciplinary Engineering. IOS Press, 2024. https://doi.org/10.3233/atde241315.

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The paper presents a high-precision successive approximation register (SAR) analog-to-digital converters (ADCs) for the bio-signal detection in internet of things (IoT) applications. A 16-bit SAR ADC with 2.5V input voltage range is designed using 180nm CMOS process. The 16-bit SAR ADC mainly includes bootstrap switches, a capacitor DAC (CDAC), a dynamic comparator, SAR logic with rotation averaging correction. The CDAC adopts a three-segment structure to realize the high resolution. The control timing sequence of the SAR ADC is VCM-based, further reducing the area of the capacitor array, and
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Su, Guojun, and Weilin Xu. "Single-Input Multi-Output High Conversion Ratio Hybrid Structure Buck-Boost DC-DC Converter for Energy Harvesting." In Frontiers in Artificial Intelligence and Applications. IOS Press, 2024. https://doi.org/10.3233/faia241335.

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This paper presents a hybrid buck-boost DC-DC converter structure to address the limitations of single-output and low conversion ratios (CR) in traditional energy harvesting systems. To reduce the CR of the inductive boost and enhance the total CR of the converter while improving efficiency, the proposed converter cascades a boost circuit with a reconfigurable switched capacitor (SC), and also includes a supercapacitor. The advantage of this architecture is the ability to use low-voltage low-threshold transistors with lower parasitic capacitance and on-resistance, which achieve high-voltage ou
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Zhang, Jinsheng, and Wei Chen. "Measurement and Modeling of Long Multi-Conductor Shielded Cable Based on Fast Vector Fitting Algorithm." In Advances in Transdisciplinary Engineering. IOS Press, 2022. http://dx.doi.org/10.3233/atde221040.

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The transmission lines need to be modeled accurately to predict the voltage reflections and EMI levels of the converter system. In this paper, a transmission line model based on fast vector fitting algorithm is proposed. At high frequencies, the parasitic capacitance of the cable conductor causes the cable impedance to resonate. Due to skin effect and proximity effect, the cable parameters change with frequency. The frequency equivalent model is used to characterize the effect of cable parameters varying with frequency. When cable is open-circuited and short-circuited, and the high-frequency i
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Konferenzberichte zum Thema "A capacitance-to-voltage converter and a comparator"

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Ruthwik, J., N. Sai Mahanth, B. Aravind Reddy, and J. Ajayan. "Optimization of Advanced Nanoscale Dynamic Voltage Comparators for the Development Future Analog to Digital Converters." In 2025 IEEE International Conference on Interdisciplinary Approaches in Technology and Management for Social Innovation (IATMSI). IEEE, 2025. https://doi.org/10.1109/iatmsi64286.2025.10985494.

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Hong, Bo-Xun, and Tsung-Heng Tsai. "A Hybrid Voltage-Time Dual-Slope Capacitance-to-Digital Converter With Noise Shaping for Extracellular Vesicle Sensing Systems." In 2024 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS). IEEE, 2024. https://doi.org/10.1109/apccas62602.2024.10808653.

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Woo, Jong-Kwan, Tae-Hoon Kim, Hyongmin Lee, Sunkwon Kim, Hyunjoong Lee, and Suhwan Kim. "A comparator-based cyclic analog-to-digital converter with boosted preset voltage." In 2011 International Symposium on Low Power Electronics and Design (ISLPED). IEEE, 2011. http://dx.doi.org/10.1109/islped.2011.5993636.

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Mohns, Enrico, Alexander Dubowik, and Martin Gotz. "An Accurate AC Current-to-Voltage Converter Based On a Fully Compensated Current Comparator." In 2020 Conference on Precision Electromagnetic Measurements (CPEM 2020). IEEE, 2020. http://dx.doi.org/10.1109/cpem49742.2020.9191843.

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Hwu, K. I., and Y. T. Yau. "Applying one-comparator counter-based PWM control strategy to DC-AC converter with voltage reference feedforward control considered." In 2011 IEEE Applied Power Electronics Conference and Exposition - APEC 2011. IEEE, 2011. http://dx.doi.org/10.1109/apec.2011.5744842.

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Arfah, Nurul, A. H. M. Zahirul Alam, and Sheroz Khan. "Capacitance-to-voltage converter for capacitance measuring system." In 2011 4th International Conference on Mechatronics (ICOM). IEEE, 2011. http://dx.doi.org/10.1109/icom.2011.5937147.

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Royo, G., C. Sánchez-Azqueta, C. Gimeno, C. Aldea, and S. Celma. "Programmable differential capacitance-to-voltage converter for MEMS accelerometers." In SPIE Microtechnologies, edited by Luis Fonseca, Mika Prunnila, and Erwin Peiner. SPIE, 2017. http://dx.doi.org/10.1117/12.2264784.

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Ferri, G., F. R. Parente, and V. Stornelli. "Current-mode differential capacitance to voltage converter for position sensing." In 2017 European Conference on Circuit Theory and Design (ECCTD). IEEE, 2017. http://dx.doi.org/10.1109/ecctd.2017.8093318.

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Zhu, Zilan, Wenchang Li, Wenxuan Yang, and Jian Liu. "A Programmable Capacitance-to-Voltage Converter for MEMS Capacitive Sensors." In 2019 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA). IEEE, 2019. http://dx.doi.org/10.1109/icta48799.2019.9012889.

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Mizushima, Kota, Satomi Ogawa, and Takahide Sato. "A High-Accuracy Capacitance-to-Voltage Converter for Capacitive Sensors." In 2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS). IEEE, 2020. http://dx.doi.org/10.1109/lascas45839.2020.9069051.

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