Thematische Bibliographien / Binary multiplier

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Auswahl der wissenschaftlichen Literatur zum Thema „Binary multiplier“

Autor: Grafiati

Veröffentlicht am 28. Juni 2021

Zuletzt aktualisiert am 21. Juni 2025

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Zeitschriftenartikel zum Thema "Binary multiplier"

Padmanabhan, Khamalesh Kumar, Umadevi Seerengasamy, and Abraham Sudharson Ponraj. "High-Speed Grouping and Decomposition Multiplier for Binary Multiplication." Electronics 11, no. 24 (2022): 4202. http://dx.doi.org/10.3390/electronics11244202.

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In the computation systems that are frequently utilized in Digital Signal Processing (DSP)- and Fast Fourier transform (FFT)-based applications, binary multipliers play a crucial role. Multipliers are one of the basic arithmetic components used, and they require more hardware resources and computational time. Due to this, numerous studies have been performed so as to decrease the computational time and hardware requirements. In this research study on reducing the necessary computational time, a high-speed binary multiplier known as the Grouping and Decomposition (GD) multiplieris proposed. The proposed multiplier aims to achieve competency in processing algorithms over existing multiplier architectures through a combination of the parallel grouping of partial products of the same size and the decomposition of each grouped partial-product bit, with the final summation performed using a 5:2 logic adder (5LA). The usage of parallel processing and decomposition logic reduces the number of computation steps and hence achieves a higher speed in multiplication. The front-end and physical design implementation of the proposed GD multiplier have been executed in the 180 nm technology library using the Cadence® Virtuoso and Cadence® Virtuoso Assura tools. From the front-end design of the 8 × 8 proposed GD multiplier, it was observed that the GD multiplier achieves a reduction of approximately 56% in computation time and a reduction of 53% in power–delay product when compared to existing multiplier architectures. A further reduction in the power–delay product is achieved by the physical design implementation of the proposed multiplier due to the internal routing of subsystems with the shortest-path algorithm. The proposed multiplier works better with higher-order multiplication and is suitable for high-end applications.

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Madenda, Sarifuddin, Suryadi Harmanto, and Astie Darmayantie. "New Concept of Universal Binary Multiplication and Its Implementation on FPGA." Journal of Southwest Jiaotong University 56, no. 3 (2021): 124–39. http://dx.doi.org/10.35741/issn.0258-2724.56.3.11.

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This paper proposes the new improvements of signed binary multiplication equation, signed multiplier, and universal multiplier. The proposed multipliers have low complexity algorithms and are easy to implement into software and hardware. Both signed, and universal multipliers are embedded into FPGA by optimizing the use of LUTs (6-LUT and 5-LUT), carry chain Carry4, and fast carry logics: MUXCYs and XORCYs.Each one is implemented as a serial-parallel multiplier and parallel multiplier. The signed multiplier executes four types of multiplication, i.e., between two operands that each one can be a signed positive (SPN) or signed negative numbers (SNN). The universal multiplier can handle all (nine) types of multiplication, where each operand can be as unsigned(USN), signed positive, and signed negative numbers. For 8x8 bits, signed serial-parallel and signed parallel multipliers occupy19 LUTs and 58 LUTs with a logic time delay of 0.769 ns and 3.600 ns. Besides, for 8x8 bits, serial-parallel and parallel universal multipliers inhabit 21 LUTs and 60 LUTs with a logic time delay of 0.831ns and 3.677 ns, successively.

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Mokhtar, Anis Shahida, Chew Sue Ping, Muhamad Faiz Md Din, Nazrul Fariq Makmor, and Muhammad Asyraf Che Mahadi. "Implementation of Booth Multiplier Algorithm using Radix-4 in FPGA." Jurnal Kejuruteraan si4, no. 1 (2021): 161–65. http://dx.doi.org/10.17576/jkukm-2021-si4(1)-20.

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This paper presentsthe performance of Radix-4 Modified Booth Algorithm. Booth algorithm is a multiplication algorithm that multiplies two signed binary numbers in two's complement notation. Multiplier is a fundamental component in general-purpose microprocessors and in digital signal processors. With advances in technology, researchers design multipliers which offer high speed, low power, and less area implementation. Booth multiplier algorithm is designed to reduce number of partial products as compared to conventional multiplier. The proposed design is simulated by using Verilog HDL in Quartus II and implemented in Cyclone II FPGA. The result shows that the average output delay is 20.78 ns. The whole design has been verified by gate level simulation.

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Etiemble, Daniel, and Ramzi A. Jaber. "Design of (3,2) and (4,2) CNTFET Ternary Counters for Multipliers." Asian Journal of Research in Computer Science 16, no. 3 (2023): 103–18. http://dx.doi.org/10.9734/ajrcos/2023/v16i3349.

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The reduction trees of combinational multipliers are widely applying counters. To be able to compare the ternary and the binary approaches, Nanotube Field-Effect Transistor (CNTFET) ternary (3,2) and ternary (4,2) counters have been designed. The ternary (4,2) counter is compared with the binary (7,3) counter as both compute approximately the same amount of information. The binary counter is more efficient. However, comparing counters is not enough: in the Wallace reduction tree of the ternary multiplier, there are two times more lines to reduce compared to the binary one, as a 1-trit multiplier generates both product and carry terms. Comparing the Wallace tree of an 8*8-trit multiplier and a 12*12-bit binary one also shows that the binary implementation is the most efficient.

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Alkurwy, Salah. "A novel approach of multiplier design based on BCD decoder." Indonesian Journal of Electrical Engineering and Computer Science 14, no. 1 (2019): 38–43. https://doi.org/10.11591/ijeecs.v14.i1.pp38-43.

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A novel approach of multiplier design is presented in this paper. The design idea is implemented based on binary coded decimal (BCD) decoder to seven segment display, by computing all the probability of multiplying 3×3 binary digits bits and grouping in table rows. The obtaining of the combinational logic functions is achieved by simplified the generated columns of [A5: A0], using a Karnaugh map. Then, the 3×3-bits multiplier circuit is used to implement the 6×6- and 12×12-bit multipliers. Comparing with a conventional multiplier, the proposed design outperformed in terms of the time delay by a 32% and 41.8% respectively. It is also reduced the combinational adaptive look-up-tables (ALUTs) by 24.6%, and 46% for both multipliers. Both overmentioned advantages make the proposed multipliers more attractive and suitable for high-speed digital systems.

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Sharma, Virat, and Manju K. Chattopadhyay. "Implementation of Novel 2x2 Vedic Multiplier using QCA Technology." Journal of Physics: Conference Series 2603, no. 1 (2023): 012045. http://dx.doi.org/10.1088/1742-6596/2603/1/012045.

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Abstract Advantages like working at high speed, scalability, and lower power consumption make QCA technology more feasible than modern CMOS technology. QCA Technology uses electrons’ Coulombic interaction and polarization to represent binary information 0 and 1. The present paper proposes a novel XOR Gate and a Half Adder design and uses them to implement a new 2x2 Vedic Multiplier on QCA technology. A 2x2 Vedic Multiplier multiplies two inputs, of two bits each, using Urdhva-Tiryakbhyam Vedic Sutra. The proposed circuit has a reduced cell count and Quantum cost compared Co-planar Vedic Multipliers to available in the literature. QCADesigner 2.0.3 is used for the simulation and verification of all three proposed circuits.

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Rajkumar, K. "Design and optimization of MSI-enabled multi-precision binary multiplier architecture." i-manager's Journal on Circuits and Systems 11, no. 2 (2023): 27. http://dx.doi.org/10.26634/jcir.11.2.20397.

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Arithmetic Logic Units (ALUs) are key elements within processors, executing a variety of operations including multiplication, division, addition, and subtraction. Among these, multiplication stands out as the most frequently utilized function within ALUs. This study presents an innovative MSI-interfaced multiplier architecture designed for integration into a multi-precision floating-point multiplier framework. This novel architecture offers configurations for 24-bit, 53-bit, 113-bit, and 237-bit binary operations, corresponding to single, double, quadruple, and octuple precision modes of floating-point computation. Notably, it enhances throughput by accommodating the multiplication of multiple batches of inputs with each operation initiation, surpassing existing binary multiplication systems. A unique Mantissa Similarity Investigation (MSI) implementation is developed and integrated into the binary multiplier architecture. Comparative analysis of the path delay in 24-bit mode against existing 24-bit multipliers demonstrates that the novel MSI-interfaced binary multiplier architecture, with and without MSI, exhibits reduced path delay compared to all existing systems, as anticipated.

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Al-Nounou, Abd Al-Rahman, Osama Al-Khaleel, Fadi Obeidat, and Mohammad Al-Khaleel. "FPGA Implementation of Fast Binary Multiplication Based on Customized Basic Cells." JUCS - Journal of Universal Computer Science 28, no. (10) (2022): 1030–57. https://doi.org/10.3897/jucs.86282.

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Multiplication is considered one of the most time-consuming and a key operation in wide variety of embedded applications. Speeding up this operation has a significant impact on the overall performance of these applications. A vast number of multiplication approaches are found in the literature where the goal is always to achieve a higher performance. One of these approaches relies on using smaller multiplier blocks which are built based on direct Boolean algebra equations to build large multipliers. In this work, we present a methodology for designing binary multipliers where different sizes customized partial products generation (CPPG) cells are designed and used as smaller building blocks. The sizes of the designed CPPG cells are 2×2, 3×3, 4×4, 5×5, and 6×6. We use these cells to build 8×8, 16×16, 32×32, 64×64, and 128×128 binary multipliers. All of the CPPG cells and the binary multipliers are described using the VHDL language, tested, and implemented using XILINX ISE 14.6 tools targeting different FPGA families. The implementation results show that the best performance is achieved when cell 3×3 is used and Virtex-7 FPGA is targeted. The binary multipliers that are designed using the proposed CPPG cells achieve better performance when compared with the binary multipliers presented in the literature. As an application that utilizes the proposed multiplier, a Multiply-Accumulate (MAC) unit is designed and implemented in Spartan-3E. The implementation results of the MAC unit demonstrate the effectiveness of the proposed multiplier.

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Kalimoldayev, M., S. Tynymbayev, M. Ibraimov, M. Magzom, Y. Kozhagulov, and T. Namazbayev. "PIPELINE MULTIPLIER OF POLYNOMIALS MODULO WITH ANALYSIS OF HIGH-ORDER BITS OF THE MULTIPLIER." BULLETIN 386, no. 4 (2020): 13–20. http://dx.doi.org/10.32014/2020.2518-1467.98.

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Among public-key cryptosystems, cryptosystems built on the basis of a polynomial system of residual classes are special. Because in these systems, arithmetic operations are performed at high speed. There are many algorithms for encrypting and decrypting data presented in the form of polynomials. The paper considers data encryption based on the multiplication of polynomials modulo irreducible polynomials. In such a multiplier, the binary image of a multiply polynomial can serve as a fragment of encrypted text. The binary image of the multiplier polynomial is the secret key and the binary representation of the irreducible polynomial is the module. Existing sequential polynomial multipliers and single-cycle matrix polynomial multipliers modulo do not provide the speed required by the encryption block. The paper considers the possibility of multiplying polynomials modulo on a Pipeline in which architectural techniques are laid in order to increase computing performance. In the conclusion of the work, the time gain of the multiplication modulo is shown by the example of the multiplication of five triples of polynomials. Verilog language was used to describe the scheme of the Pipeline multiplier. Used FPGA Artix-7 from Xilinx companies. The developed Pipeline multiplier can be used for cryptosystems based on a polynomial system of residual classes, which can be implemented in hardware or software.

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Al-Nounou, Abd Al-Rahman, Osama Al-Khaleel, Fadi Obeidat, and Mohammad Al-Khaleel. "FPGA Implementation of Fast Binary Multiplication Based on Customized Basic Cells." JUCS - Journal of Universal Computer Science 28, no. 10 (2022): 1030–57. http://dx.doi.org/10.3897/jucs.86282.

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Multiplication is considered one of the most time-consuming and a key operation in wide variety of embedded applications. Speeding up this operation has a significant impact on the overall performance of these applications. A vast number of multiplication approaches are found in the literature where the goal is always to achieve a higher performance. One of these approaches relies on using smaller multiplier blocks which are built based on direct Boolean algebra equations to build large multipliers. In this work, we present a methodology for designing binary multipliers where different sizes customized partial products generation (CPPG) cells are designed and used as smaller building blocks. The sizes of the designed CPPG cells are 2&times;2, 3&times;3, 4&times;4, 5&times;5, and 6&times;6. We use these cells to build 8&times;8, 16&times;16, 32&times;32, 64&times;64, and 128&times;128 binary multipliers. All of the CPPG cells and the binary multipliers are described using the VHDL language, tested, and implemented using XILINX ISE 14.6 tools targeting different FPGA families. The implementation results show that the best performance is achieved when cell 3&times;3 is used and Virtex-7 FPGA is targeted. The binary multipliers that are designed using the proposed CPPG cells achieve better performance when compared with the binary multipliers presented in the literature. As an application that utilizes the proposed multiplier, a Multiply-Accumulate (MAC) unit is designed and implemented in Spartan-3E. The implementation results of the MAC unit demonstrate the effectiveness of the proposed multiplier.

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Dissertationen zum Thema "Binary multiplier"

Hojný, Ondřej. "Evoluční návrh kombinačních obvodů." Master's thesis, Vysoké učení technické v Brně. Fakulta strojního inženýrství, 2021. http://www.nusl.cz/ntk/nusl-442801.

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This diploma thesis deals with the use of Cartesian Genetic Programming (CGP) for combinational circuits design. The work addresses the issue of optimizaion of selected logic circuts, arithmetic adders and multipliers, using Cartesian Genetic Programming. The implementation of the CPG is performed in the Python programming language with the aid of NumPy, Numba and Pandas libraries. The method was tested on selected examples and the results were discussed.

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Rogers, Derek. "Non-binary spread-spectrum multiple-access communications /." Title page, contents and abstract only, 1995. http://web4.library.adelaide.edu.au/theses/09PH/09phr725.pdf.

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Khalid, Abbas. "Coding for the multiple access binary channel." Thesis, Lancaster University, 2012. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.659445.

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Transmitting the maximum amount of information in minimum possible bandwidth is always desired . Multiple access (MA) communication is often used to achieve this objective. However, the mutual interference among the users handicaps the performance considerably. Addition of redundancy bits for reliable transmission demands more bandwidth. Power line communication (PLC) is considered an attractive candidate to overcome the scarcity of the bandwidth and the associated huge cost. PLC uses power lines as a communication medium which were originally designed for power distribution rather than data transmission and are more harsh compared to other communication media. Frequency-selective fading and inter-symbol-interference (ISI) due to multipaths degrade the bit error rate (BER) substantially. Furthermore, devices connected to the grid introduce impulsive noise on the network. Robust coding and modulation schemes are therefore required to increase the communication reliability. Multi-fold turbo coding is a technique used to improve the error performance of conventional turbo codes. Multi-fold turbo coding increases the randomness of a turbo code by dividing the long information sequence in small subsequences and making use of multiple pseudo random interleavers. Multiple interleavers spread the error burst over several symbols making the errors appear in random. Orthogonal frequency-division multiplex (OFDM) distributes the overall transmitted data in parallel on several orthogonal subcarriers and transforms a frequency-selective fading channel to a group of many flat-fading channels. OFDM possesses a unique property which disperses impulsive noise burst across its several sub-carriers; hence Abstract is able to cope better in an impulsive noise environment. This thesis presents multi-fold turbo coding scheme for MA channels. Specifically, a member of multi-fold family called two-fold has been adopted for the simplest MA channel, the two-user binary adder channel (2-BAC). Each user uses a distinct code to encode the information and the decoder employed uses iterative decoding to decode the received signal. Making use of distinct codes not only allows the correction of errors due to noise but also the correction of errors due to interference between users. Performance of multi-fold turbo codes has been evaluated under Gaussian and power-line conditions. Depedance of performance on number of iterations and blocklength is also presented. A simplified multipath model approach is introduced for complex power-line channels in which the power-line network is divided into number of small segments and each segment is considered as an independent sub-channel. Transfer function of each sub-channel is determined. The transfer function of the whole network is taken as a product of all component transfer functions. The approach has been applied to model two PLC networks that are used as reference channels for the work presented in the thesis. Multi-fold turbo codes can be modified to provide unequal error protection (UEP) levels to the information having different ranks of importance where the most significant information is protected more than the information with least importance. To demonstrate the practicality of the UEP mechanism for the 2-BAC, two test images are decomposed into luminance (£), saturation (8) and hue (if) components. The L component of each image is protected twice than the other two components. The performance of the modified multi-fold turbo codes is compared with the multi-fold turbo codes and conventional turbo codes in terms of pixel error rate (PER.) in Gaussian and power-line environments. The visual effects of PER. for each image are also presented.

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Clarici, Georg. "Multiple quantum well binary-phase modulators : a feasibility study." Thesis, Heriot-Watt University, 2002. http://hdl.handle.net/10399/458.

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Novak, Gregory S. "Simulated galaxy remnants produced by binary and multiple mergers /." Diss., Digital Dissertations Database. Restricted to UC campuses, 2008. http://uclibs.org/PID/11984.

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Kubik, Lauren Ashley. "Simultaneously lifting multiple sets in binary knapsack integer programs." Thesis, Manhattan, Kan. : Kansas State University, 2009. http://hdl.handle.net/2097/1460.

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Crowley, William L. "Lossless compression using binary necklace classes and multiple huffman trees." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2001. http://handle.dtic.mil/100.2/ADA397592.

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Benachour, Phillip. "Trellis decoding techniques for the multiple access binary adder channel." Thesis, Lancaster University, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.314240.

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Merkl, Frank J. "Binary image compression using run length encoding and multiple scanning techniques /." Online version of thesis, 1988. http://hdl.handle.net/1850/8309.

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Baxter, Rodney Charles. "The thermodynamics of binary liquid mixtures of compounds containing multiple bonds." Thesis, Rhodes University, 1989. http://hdl.handle.net/10962/d1016079.

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Excess thermodynamic properties have been determined for several binary liquid mixtures with the aim of testing various thermodynamic theories and postulates. Excess molar enthalpies, HEm, have been determined using an LKB flow microcalorimeter and excess molar volumes, VEm, have been determined using an Anton Paar vibrating tube densitometer. The activity coefficients at infinite dilution ƴ∞₁₃, have been determined using an atmospheric pressure gas-liquid chromatograph. The excess molar enthalpies and the excess molar volumes have been measured at 298.15 K for systems involving the bicyclic compounds decahydronaphthalene (decalin), 1,2,3,4-tetrahydronaphthalene (tetralin), bicyclohexyl, or cyclohexylbenzene mixed with 1- hexene, 1-hexyne, 1-heptene, 1-heptyne, cyclohexene, 1,3-cyclohexadiene, 1,4- cyclohexadiene, or benzene. These excess properties have also been measured for systems where the bicyclic compound has been replaced with benzene, cyclohexane or n-hexane. The results show defmite trends related to the size, shape, and the degree of unsaturation of the component molecules. The Flory theory has been used to predict excess molar enthalpies and excess molar volumes for {(a bicyclic compound or benzene or cyclohexane or n-hexane) +(an n-alkane or a 1-alkene or a 1-alkyne or a cycloalkane or cyclohexene or a cycloalkadiene or benzene)}. The one parameter equations offer reasonably good correlations between the predicted and the experimental results. More insight into the origins of the contnbutions to the excess thermodynamic properties for these systems has been gained by considering the approximate equations of Patterson and co-workers, which separate the interactional and the free volume contributions to the excess molar enthalpy and the excess molar volume. The one parameter equations have adequately rationalized a good deal of the observed behaviour for HEm and VEm. The theory of Liebermann and co-workers, which does not employ any adjustable parameters, has not been as successful at predicting the excess thermodynamic properties for the above systems. The activity coefficients at infinite dilution have been measured at 278.15 K, 288.15 K and 298.15 K for n-bexane, 1-bexene, 1-hexyne, n-heptane, 1-heptene, 1-heptyne, cyclohexane, cyclohexene, 1,3-cyclohexadiene, 1,4-cyclohexadiene, and benzene, in decalin, tetralin, bicyclohexyl, and cyclohexylbenzene. Solvent losses from the column have been accounted for by an extrapolation procedure. The activity coefficient results together with the HEm and VEm values have been used to calculate the partial molar excess thermodynamic properties of mixing at infinite dilution. The partial molar excess properties at infinite dilution for decalin mixtures are similar to those for bicyclohexyl mixtures. There is also a similarity between the properties of the tetralin mixtures and the cyclohexylbenzene mixtures. The cycloalkadienes, benzene and the 1-alkynes exhibit a strong dissociation effect on being mixed with the saturated solvents, decalin and bicyclohexyl, but associate strongly with tetralin and with cyclohexylbenzene. The Flory theory bas been used to predict activity coefficients at infinite dilution from the experimentally determined HEm results for { (n-bexane or 1-hexene or 1-hexyne or naheptane or 1-heptene or 1-beptyne) + (a bicyclic compound)}. The theory is much better at predicting values for mixtures where both components are either saturated molecules or are unsaturated molecules than for {saturated + unsaturated} mixtures.

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Bücher zum Thema "Binary multiplier"

Pirlot, Paul. Brains and behaviours: From binary structures to multiple functions. 2nd ed. Orbis Pub., 1993.

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Symposium, International Astronomical Union. Birth and evolution of binary stars: Poster proceedings of IAU Symposium No. 200 on the formation of binary stars, 10-15 April 2000, Potsdam, Germany. Astrophysikalisches Institut Potsdam, 2000.

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United States. National Aeronautics and Space Administration., ed. NRA, first multiwavelength, multiple layer doppler imaging of an active binary. National Aeronautics and Space Administration, 1998.

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1940-, Eggleton P. P., Podsiadlowski Philipp 1962-, Osservatorio astronomico di Roma, Lawrence Livermore National Laboratory, and Astronomical Society of the Pacific., eds. Evolution of binary and multiple star systems: A meeting in celebration of Peter Eggleton's 60th birthday : proceedings held in Bormio, Italy, 25 June-1 July 2000. Astronomical Society of the Pacific, 2001.

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Green, Catherine E., and Elior Haley. Aether Beyond the Binary. Duck Prints Press LLC, 2024.

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Green, Catherine E., and Elior Haley. Aether Beyond the Binary. Duck Prints Press LLC, 2024.

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Green, Catherine E., and Elior Haley. Aether Beyond the Binary. Duck Prints Press LLC, 2024.

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Green, Catherine E., and Elior Haley. Aether Beyond the Binary. Duck Prints Press LLC, 2024.

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Beyond Binary Memory Circuits: Multiple-Valued Logic. Springer International Publishing AG, 2023.

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Buchteile zum Thema "Binary multiplier"

Pattimi, Hari, and Rajanbabu Mallavarapu. "Pipeline Decimal Multiplier Using Binary Multipliers." In Proceedings of 2nd International Conference on Micro-Electronics, Electromagnetics and Telecommunications. Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-4280-5_22.

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Walker, Alvernon, and Evelyn Sowells-Boone. "Efficient Set-Bit Driven Shift-Add Binary Multiplier." In Advances in Intelligent Systems and Computing. Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-030-01177-2_99.

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Behera, Niharika, Manoranjan Pradhan, and Pranaba K. Mishro. "Analysis of Delay in 16 × 16 Signed Binary Multiplier." In Proceedings of the International Conference on Paradigms of Computing, Communication and Data Sciences. Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-19-8742-7_13.

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Miomo, Takahiro, Koichi Yasuoka, and Masanori Kanazawa. "The Fastest Multiplier on FPGAs with Redundant Binary Representation." In Lecture Notes in Computer Science. Springer Berlin Heidelberg, 2000. http://dx.doi.org/10.1007/3-540-44614-1_56.

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Kelly, P. M., C. J. Thompson, T. M. McGinnity, and L. P. Maguire. "A Binary Multiplier Using RTD Based Threshold Logic Gates." In Artificial Neural Nets Problem Solving Methods. Springer Berlin Heidelberg, 2003. http://dx.doi.org/10.1007/3-540-44869-1_6.

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Barik, Ranjan Kumar, Ashish Panda, and Manoranjan Pradhan. "A High-Speed Booth Multiplier Based on Redundant Binary Algorithm." In Advances in Intelligent Systems and Computing. Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-6875-1_56.

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Maurya, Deepti, and Uma Sharma. "Versatile 4-bit signed binary multiplier for complex digital circuits." In Advances in AI for Biomedical Instrumentation, Electronics and Computing. CRC Press, 2024. http://dx.doi.org/10.1201/9781032644752-29.

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Taverne, Jonathan, Armando Faz-Hernández, Diego F. Aranha, Francisco Rodríguez-Henríquez, Darrel Hankerson, and Julio López. "Software Implementation of Binary Elliptic Curves: Impact of the Carry-Less Multiplier on Scalar Multiplication." In Cryptographic Hardware and Embedded Systems – CHES 2011. Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-23951-9_8.

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Yu, Po-Lung. "Binary Relations." In Multiple-Criteria Decision Making. Springer US, 1985. http://dx.doi.org/10.1007/978-1-4684-8395-6_2.

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Zhou, Yu, and Zhuoyi Song. "Binary Decision Trees for Melanoma Diagnosis." In Multiple Classifier Systems. Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-38067-9_33.

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Konferenzberichte zum Thema "Binary multiplier"

Verma, Manmohan, Suyash Sharma, and Shasanka Sekhar Rout. "A Comparative Study of Wallace Tree Multiplier and Binary Multiplier Performance." In 2024 International Conference on Communication, Control, and Intelligent Systems (CCIS). IEEE, 2024. https://doi.org/10.1109/ccis63231.2024.10932105.

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Neto, Horacio C., and Mario P. Vestias. "Decimal multiplier on FPGA using embedded binary multipliers." In 2008 International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2008. http://dx.doi.org/10.1109/fpl.2008.4629931.

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Haghiri, Saeed, Ali Nemati, Soheil Feizi, Amirali Amirsoleimani, Arash Ahmadi, and Majid Ahmadi. "A memristor based binary multiplier." In 2017 IEEE 30th Canadian Conference on Electrical and Computer Engineering (CCECE). IEEE, 2017. http://dx.doi.org/10.1109/ccece.2017.7946783.

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Bawaskar, Ashish A., Vilas Alagdeve, and Rashmi Keote. "High performance redundant binary multiplier." In 2016 International Conference on Communication and Signal Processing (ICCSP). IEEE, 2016. http://dx.doi.org/10.1109/iccsp.2016.7754358.

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Kumar Kattamuri, R. S. N., and S. K. Sahoo. "Computation sharing multiplier using redundant binary arithmetic." In APCCAS 2010-2010 IEEE Asia Pacific Conference on Circuits and Systems. IEEE, 2010. http://dx.doi.org/10.1109/apccas.2010.5774869.

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Arun, Konduri, and K. Srivatsan. "A binary high speed floating point multiplier." In 2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2). IEEE, 2017. http://dx.doi.org/10.1109/icnets2.2017.8067953.

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Bhattacharjee, Pritam, Arindam Sadhu, and Kunal Das. "A register-transfer-level description of synthesizable binary multiplier and binary divider." In 2016 International Conference on Microelectronics, Computing and Communications (MicroCom). IEEE, 2016. http://dx.doi.org/10.1109/microcom.2016.7522470.

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Shuli Gao, Dhamin Al-Khalili, J. M. Pierre Langlois, and Noureddine Chabini. "Decimal floating-point multiplier with binary-decimal compression based fixed-point multiplier." In 2017 IEEE 30th Canadian Conference on Electrical and Computer Engineering (CCECE). IEEE, 2017. http://dx.doi.org/10.1109/ccece.2017.7946692.

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Bisoyi, Abhyarthana, Mitu Baral, and Manoja Kumar Senapati. "Comparison of a 32-bit Vedic multiplier with a conventional binary multiplier." In 2014 International Conference on Advanced Communication, Control and Computing Technologies (ICACCCT). IEEE, 2014. http://dx.doi.org/10.1109/icaccct.2014.7019410.

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Kim, Dai Hyun, Andrew Kostrzewski, Yao Li, and George Eichmann. "A sign/logarithm number-system-based fast optical binary multiplier." In OSA Annual Meeting. Optica Publishing Group, 1990. http://dx.doi.org/10.1364/oam.1990.tuuu5.

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We will present a new fast binary multiplication scheme based on the use of a nonholographic parallel optical content addressable memory (CAM). The multiplication operation is performed by means of binary logarithmic addition that uses a sign/logarithm number system. Multiplication of two binary numbers a and b begins by converting them into a sign/logarithm number system. Multiplication is accomplished by adding appropriate logarithms. A 3-stage non-holographic CAM is required to implement a sign/logarithm number multiplier. By means of a Quine-McCluskey minimization method, the number of CAM's minterms are reduced. For a 7-bit binary multiplication the first CAM, reduced from 605 to 111 minterms, converts the binary numbers to sign/logarithm numbers. To add the two logarithms, a second CAM, reduced from 2519 to 270 minterms, performs a floating-point binary-carry look-ahead addition. Finally, a third CAM with 329 instead of 891 minterms, does the conversion from sign/logarithm numbers back to binary numbers. In general, the storage capacity needed for each CAM stage depends on the range of input numbers and the calculation accuracy.

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Berichte der Organisationen zum Thema "Binary multiplier"

Pritchard, Katrina, Helen Williams, and Alice Elworthy. Mapping policy understandings of gender & sexuality: thematic analysis. Swansea University, 2023. http://dx.doi.org/10.23889/sureport.64441.

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This second report from the Breaking Binaries Research (BBR) programme extends and develops our first report which offered a preliminary review of mapping understandings of genders and sexualities across policy data (Pritchard et al., 2023). As in our first report, we focus on the implications of these understandings for entrepreneurs and small businesses in relation to how diversity is constructed by policy makers. We define gender and sexuality diversity as including all those who self-identify as not conforming to binary identities and/or bodies, and those who identify in various, and sometimes multiple ways, as part of LGBTQIA+ and non-binary communities. Policy makers labelling of these identities, especially the use of pre-given categories, is problematic (Guyan, 2022). Within the overarching initialisms or acronyms, like LGBTQIA+, sit host of diverse, and in most cases, intersecting communities, which are oversimplified and little understood.

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Knop, R., and R. G. Stokstad. BRANDEX: A FORTRAN/Pascal code to calculate the multiple binary splitting of an excited nucleus. Office of Scientific and Technical Information (OSTI), 1989. http://dx.doi.org/10.2172/5704795.

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Reimus, Paul W. Binary Tracers and Multiple Geophysical Data Set Inversion Methods to Improve EGS Reservoir Characterization and Imaging. Office of Scientific and Technical Information (OSTI), 2014. http://dx.doi.org/10.2172/1130518.

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Pritchard, Katrina, Helen C. Williams, and Alice Elworthy. Mapping policy understandings of gender & sexuality: preliminary review. School of Management, Swansea University, 2023. http://dx.doi.org/10.23889/sureport.63677.

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As part of the wider Breaking Binaries Research (BBR) programme, in this project we aim to map understandings of gender and sexuality diversity across various government policy documents within the UK. We focus on the implications of these understandings for entrepreneurs and small businesses in relation to how diversity is constructed by policy makers. Policy documents provide a visual and written summary with varying focus ranging from statements, directives, advisories and guidance, plans and reviews. Such policies represent a political ideological articulation of how prevailing values intersect with understandings of diverse identities (Ahl & Marlow, 2021). We define gender and sexuality diversity as including all those who self-identify as not conforming to binary identities and/or bodies, and those who identify in various, and sometimes multiple, ways as part of LGBTQIA+ communities. Policy makers labelling of these identities, especially the use of pre-given categories, is problematic (Guyan, 2022) but little is known about the use of different terms and associated understandings. Our initial focus is therefore a mapping exercise to explore both visual and textual data to shed light on policy understandings of these aspects of diversity.

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Maloney, Megan, Sarah Becker, Andrew Griffin, Susan Lyon, and Kristofer Lasko. Automated built-up infrastructure land cover extraction using index ensembles with machine learning, automated training data, and red band texture layers. Engineer Research and Development Center (U.S.), 2024. http://dx.doi.org/10.21079/11681/49370.

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Automated built-up infrastructure classification is a global need for planning. However, individual indices have weaknesses, including spectral confusion with bare ground, and computational requirements for deep learning are intensive. We present a computationally lightweight method to classify built-up infrastructure. We use an ensemble of spectral indices and a novel red-band texture layer with global thresholds determined from 12 diverse sites (two seasonally varied images per site). Multiple spectral indexes were evaluated using Sentinel-2 imagery. Our texture metric uses the red band to separate built-up infrastructure from spectrally similar bare ground. Our evaluation produced global thresholds by evaluating ground truth points against a range of site-specific optimal index thresholds across the 24 images. These were used to classify an ensemble, and then spectral indexes, texture, and stratified random sampling guided training data selection. The training data fit a random forest classifier to create final binary maps. Validation found an average overall accuracy of 79.95% (±4%) and an F1 score of 0.5304 (±0.07). The inclusion of the texture metric improved overall accuracy by 14–21%. A comparison to site-specific thresholds and a deep learning-derived layer is provided. This automated built-up infrastructure mapping framework requires only public imagery to support time-sensitive land management workflows.

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Arhin, Stephen, Babin Manandhar, and Adam Gatiba. Influence of Pavement Conditions on Commercial Motor Vehicle Crashes. Mineta Transportation Institute, 2023. http://dx.doi.org/10.31979/mti.2023.2343.

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Commercial motor vehicle (CMV) safety is a major concern in the United States, including the District of Columbia (DC), where CMVs make up 15% of traffic. This research uses a comprehensive approach, combining statistical analysis and machine learning techniques, to investigate the impact of road pavement conditions on CMV accidents. The study integrates traffic crash data from the Traffic Accident Reporting and Analysis Systems Version 2.0 (TARAS2) database with pavement condition data provided by the District Department of Transportation (DDOT). Data spanning from 2016 to 2020 was collected and analyzed, focusing on CMV routes in DC. The analysis employs binary logistic regression to explore relationships between injury occurrence after a CMV crash and multiple independent variables. Additionally, Artificial Neural Network (ANN) models were developed to classify CMV crash injury severity. Importantly, the inclusion of pavement condition variables (International Roughness Index and Pavement Condition Index) substantially enhanced the accuracy of the logistic regression model, increasing predictability from 0.8% to 41%. The study also demonstrates the potential of Artificial Neural Network models in predicting CMV crash injury severity, achieving an accuracy of 60% and an F-measure of 0.52. These results highlight the importance of considering road pavement conditions in road safety policies and interventions. The study provides valuable insights for policymakers and stakeholders aiming to enhance road safety for CMVs in the District of Columbia and showcases the potential of machine learning techniques in understanding the complex interplay between road conditions and CMV crash occurrences.

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Leslie, Jean, and Kelly Simmons. Leadership Capabilities for Navigating a Polycrisis. Center for Creative Leadership, 2024. http://dx.doi.org/10.35613/ccl.2024.2058.

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In an era of global challenges, leaders face a landscape characterized by what scholars term "polycrisis1" – a convergence of multiple, interconnected crises that amplify each other'simpacts. While the concept of polycrisis is gaining recognition, our study revealed a significant gap. No substantial body of literature currently addresses leadership in the midst of polycrisis. This absence underscores the novelty and importance of our study. To bridge this gap, we turned to the concepts of "grand challenges" and "wicked problems," which share many characteristics with polycrisis and have more established leadership literature. Our study aims to identify the critical leadership capabilities for effectively navigating polycrisis contexts. Through a synthesis of findings from relevant articles on leadership, grand challenges, and wicked problems, followed by expert validation, our analysis yielded six key themes of leadership capabilities: 1. Complex Problem-Solving 2. Collaboration and Relationships 3. Transformative Leadership 4. Inclusivity and Ethics 5. Inner Capabilities 6. Future Orientation These themes represent a shift from current leadership paradigms, emphasizing the need for leaders to develop skills and mindsets that effectively address the complex challenges within a polycrisis. This shift reframes crises from isolated events to be mitigated to a chronic state of instability requiring active engagement and adaptability. It moves beyond mere preservation to transformational leadership that seeks opportunities within the multifaceted aspects of crises to shape more equitable, resilient, and sustainable futures. Our findings recognize that a polycrisis is not a binary state (present or absent) but rather a spectrum of interconnected challenges that can vary in intensity and complexity over time. Leaders must be prepared to navigate and respond to these fluctuating conditions, addressing specific aspects of a polycrisis while maintaining awareness of the broader context. This nuanced approach significantly impacts leadership development in an increasingly complex world. By identifying these critical capabilities and applying them to the concept of polycrisis, this study provides a framework for reimagining leadership education and development. It fills a crucial gap in existing literature and practice by offering a more dynamic and adaptable model of leadership suited to the multifaceted nature of contemporary global challenges.

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Mawassi, Munir, Adib Rowhani, Deborah A. Golino, Avichai Perl, and Edna Tanne. Rugose Wood Disease of Grapevine, Etiology and Virus Resistance in Transgenic Vines. United States Department of Agriculture, 2003. http://dx.doi.org/10.32747/2003.7586477.bard.

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Rugose wood is a complex disease of grapevines, which occurs in all growing areas. The disease is spread in the field by vector transmission (mealybugs). At least five elongated-phloem- limited viruses are implicated in the various rugose wood disorders. The most fully characterized of these are Grapevine virus A (GV A) and GVB, members of a newly established genus, the vitivirus. GVC, a putative vitivirus, is much less well characterized than GV A or GVB. The information regarding the role of GVC in the etiology and epidemiology of rugose wood is fragmentary and no sequence data for GVC are available. The proposed research is aimed to study the etiology and epidemiology of rugose wood disease, and to construct genetically engineered virus-resistant grapevines. The objectives of our proposed research were to construct transgenic plants with coat protein gene sequences designed to induce post-transcriptional gene silencing (pTGS); to study the epidemiology and etiology of rugose wood disease by cloning and sequencing of GVC; and surveying of rugose wood- associated viruses in Californian and Israeli vineyards. In an attempt to experimentally define the role of the various genes of GV A, we utilized the infectious clone, inserted mutations in every ORF, and studied the effect on viral replication, gene expression, symptoms and viral movement. We explored the production of viral RNAs in a GV A-infected Nicotiana benthamiana herbaceous host, and characterized one nested set of three 5'-terminal sgRNAs of 5.1, 5.5 and 6.0 kb, and another, of three 3'-terminal sgRNAs of 2.2, 1.8 and 1.0 kb that could serve for expression of ORFs 2-3, respectively. Several GV A constructs have been assembled into pCAMBIA 230 I, a binary vector which is used for Angrobacterium mediated transformation: GV A CP gene; two copies of the GV A CP gene arranged in the same antisense orientation; two copies of the GV A CP gene in which the downstream copy is in an antigens orientation; GV A replicase gene; GV A replicase gene plus the 3' UTR sequence; and the full genome of GV A. Experiments for transformation of N. benthamiana and grapevine cell suspension with these constructs have been initiated. Transgenic N. benthamiana plants that contained the CP gene, the replicase gene and the entire genome of GV A were obtained. For grapevine transformation, we have developed efficient protocols for transformation and successfully grapevine plantlets that contained the CP gene and the replicase genes of GV A were obtained. These plants are still under examination for expression of the trans genes. The construction of transgenic plants with GV A sequences will provide, in the long run, a means to control one of the most prevalent viruses associated with grapevines. Our many attempts to produce a cDNA library from the genome of GVC failed. For surveying of rugose wood associated viruses in California vineyards, samples were collected from different grape growing areas and tested by RT-PCR for GV A, GVB and GVD. The results indicated that some of the samples were infected with multiple viruses, but overall, we found higher incidence of GVB and GV A infection in California vineyards and new introduction varieties, respectively. In this research we also conducted studies to increase our understanding of virus - induced rootstock decline and its importance in vineyard productivity. Our results provided supporting evidence that the rootstock response to virus infection depends on the rootstock genotype and the virus type. In general, rootstocks are differ widely in virus susceptibility. Our data indicated that a virus type or its combination with other viruses was responsible in virus-induced rootstock decline. As the results showed, the growth of the rootstocks were severely affected when the combination of more than one virus was present.

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Taylor, Bea, Heather Wardle, and Isabel Taylor. Exploring the problem gambling health-harm paradox. Greo Evidence Insights, 2022. https://doi.org/10.33684/2024.002.

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Purpose: Previous research by NatCen identified a potential health-harm paradox for mental wellbeing and gambling, finding that those with poor mental wellbeing or a diagnosed mental health condition were more likely to experience problem gambling despite being less likely to gamble at all. This report aimed to explore this further, testing three specific hypothesis which could account for this association: 1. That people with poorer mental wellbeing who gamble do so more frequently and it is this increased frequency of gambling that drives elevated rates of gambling severity. 2. That people with poorer mental wellbeing who gamble generally take part in higher risk health behaviours (e.g., higher-risk alcohol consumption; cigarette smoking) and this drives the association. 3. That people with poorer mental wellbeing who gamble are more likely to take part in specific types of gambling that are associated with higher rates of harms. This report explores these potential mechanisms, using data collected in recent Health surveys across England and Scotland. Methodology: Data from the 2015-2017 Scottish Health Survey and the 2015, 2016 & 2018 Health Survey for England were combined, and bivariate analysis was conducted first to confirm that the relationships between mental health, moderate risk/problem gambling and gambling patterns did not vary significantly between survey years. With this established, binary logistic regressions using the combined data from both the Scottish and English Health Survey series were employed to investigate explanatory factors of the association between mental health and experiences of moderaterisk/problem gambling. These include gambling and other health-related factors. These were first conducted on the full sample, and then separate models were estimated for men and women to provide further insights by gender. Measures: For the exposure variable, three different established measures of mental health were used: doctor diagnosis of a mental health condition, the Warwick-Edinburgh Mental Wellbeing Scale (WEMWBS; a score of 40 or below indicating probable depression) and the General Health Questionnaire (GHQ-12; a score of 4 or more indicating significant mental distress). The outcome variable of moderate risk/problem gambling was measured by the Canadian Problem Gambling Index’s Problem Gambling Severity Index (PGSI), while gambling activities and frequency were derived from multiple questions in the combined surveys. The PGSI is a measure of the riskiness of a person’s gambling habits. Someone identified as a moderate risk gambler experiences a moderate level of problems with their gambling which can lead to some negative consequences. These might be spending more than they can afford, losing track of time while gambling, or feeling guilty about how much they gamble. A person identified as a problem gambler in the PGSI score will also face negative consequences from their gambling, as well as a possible loss of control. Control variables included socio-demographic characteristics and alcohol and cigarette consumption. Results: Our results confirm previous findings that people with poor mental wellbeing or a diagnosed mental health condition were significantly more likely to experience moderate risk or problem gambling despite being less likely to gamble at all. For example, 50% of those experiencing significant mental distress gambled in the past year compared with 54% of those not experiencing significant mental distress, yet rates of experiencing moderate risk/problem gambling respectively were 2.4% and 1.2%. Logistic regression models showed that the associations between moderate risk and problem gambling and both ‘mental distress’ (measured in the GHQ) and ‘probable depression’ (the WEMWBS) were not fully accounted for by differences in gambling frequency, gambling activity or engagement in other risky health behaviours. Thus, these alternative explanations for the association between mental wellbeing and moderate risk or problem gambling was not supported by any of the three hypotheses tested. In the fully adjusted models, controlling for all these alternative explanations, the odds ratio of moderate risk/problem gambling were 1.86 times higher among those with probable depression and 2.56 times higher among those with significant mental distress. This relationship is not explained by those with poor mental wellbeing who gamble participating in gambling more often, engaging in higher-risk health behaviours or in specific types of gambling activity. However, when looking at doctor-diagnosed mental health conditions and moderate risk or problem gambling, only one hypothesis was rejected – that increased gambling frequency could explain this association. When cigarette smoking and high-risk alcohol consumption were controlled for, and when engagement in specific gambling activities were taken into account, there was no evidence of an association between doctor-diagnosed mental health conditions and moderate risk/problem gambling Finally, gender-stratified analysis revealed that for men with poor mental wellbeing or a diagnosed mental health condition had a similar relationship to moderate risk/problem gambling as the whole population. For women, the study was underpowered to look at this in detail. Implications: Findings from this research suggest that the relationship between poor mental wellbeing and moderate risk/problem gambling is not driven by differences in gambling or other high-risk health behaviour, particularly amongst people experiencing anxiety or depression. The association between poor mental wellbeing and experiences of moderate risk and problem gambling in this data persists when these behaviours are taken into account, though the direction of any causal (or potentially reciprocal) relationship has not been established in this cross-sectional data. Although other factors not measured in study may explain this relationship, it is concerning that people with poor mental wellbeing are more likely to experience gambling harms, despite lower levels of gambling engagement. Therefore, gambling should be embedded within broader strategies for improving mental health (for example, as a risk factor for poor mental wellbeing; for suicidality etc.) and should be considered as both a potential cause and consequence of moderate risk and problem gambling, to help to identify and address this. It also highlights the need for additional research into the specific doctor-diagnosed mental health conditions that increase the risk of moderate risk/problem gambling, as well as further investigations into the causal pathway between both mental distress and depression and moderate risk/problem gambling.

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Inclusion and Advocacy for Women with ADHD: Addressing Inequities and Challenging Diagnostic Bias on International Women’s Day. ACAMH, 2024. http://dx.doi.org/10.13056/acamh.26609.

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March 8th, 2024 is International Women’s Day and this year’s theme is “Inspire Inclusion.” Unfortunately, women who hold multiple intersecting identities that are systemically oppressed world-wide are often excluded from discussions. One example includes women who are neurodiverse, and more specifically for this post, women with attention-deficit/hyperactivity disorder (ADHD). Women and non-binary folks are often excluded from appropriate diagnosis of ADHD due to bias in providers, boy/men-dominated symptoms in the DSM-5 (Barkley, 2023; Hinshaw et al., 2021), socialization to mask and internalize symptoms, and sexism and other forms of discrimination. As with most discrimination, this is even worse for women with ADHD who also hold other systemically oppressed identities. This blog will focus on how to increase equity for women with ADHD with concrete solutions for multiples systems that affect them.

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