Um die anderen Arten von Veröffentlichungen zu diesem Thema anzuzeigen, folgen Sie diesem Link: Binary multiplier.
Zeitschriftenartikel zum Thema „Binary multiplier“
Geben Sie eine Quelle nach APA, MLA, Chicago, Harvard und anderen Zitierweisen an
Machen Sie sich mit Top-50 Zeitschriftenartikel für die Forschung zum Thema "Binary multiplier" bekannt.
Neben jedem Werk im Literaturverzeichnis ist die Option "Zur Bibliographie hinzufügen" verfügbar. Nutzen Sie sie, wird Ihre bibliographische Angabe des gewählten Werkes nach der nötigen Zitierweise (APA, MLA, Harvard, Chicago, Vancouver usw.) automatisch gestaltet.
Sie können auch den vollen Text der wissenschaftlichen Publikation im PDF-Format herunterladen und eine Online-Annotation der Arbeit lesen, wenn die relevanten Parameter in den Metadaten verfügbar sind.
Sehen Sie die Zeitschriftenartikel für verschiedene Spezialgebieten durch und erstellen Sie Ihre Bibliographie auf korrekte Weise.
1
Padmanabhan, Khamalesh Kumar, Umadevi Seerengasamy, and Abraham Sudharson Ponraj. "High-Speed Grouping and Decomposition Multiplier for Binary Multiplication." Electronics 11, no. 24 (2022): 4202. http://dx.doi.org/10.3390/electronics11244202.
Der volle Inhalt der QuelleAnnotation:
In the computation systems that are frequently utilized in Digital Signal Processing (DSP)- and Fast Fourier transform (FFT)-based applications, binary multipliers play a crucial role. Multipliers are one of the basic arithmetic components used, and they require more hardware resources and computational time. Due to this, numerous studies have been performed so as to decrease the computational time and hardware requirements. In this research study on reducing the necessary computational time, a high-speed binary multiplier known as the Grouping and Decomposition (GD) multiplieris proposed. The proposed multiplier aims to achieve competency in processing algorithms over existing multiplier architectures through a combination of the parallel grouping of partial products of the same size and the decomposition of each grouped partial-product bit, with the final summation performed using a 5:2 logic adder (5LA). The usage of parallel processing and decomposition logic reduces the number of computation steps and hence achieves a higher speed in multiplication. The front-end and physical design implementation of the proposed GD multiplier have been executed in the 180 nm technology library using the Cadence® Virtuoso and Cadence® Virtuoso Assura tools. From the front-end design of the 8 × 8 proposed GD multiplier, it was observed that the GD multiplier achieves a reduction of approximately 56% in computation time and a reduction of 53% in power–delay product when compared to existing multiplier architectures. A further reduction in the power–delay product is achieved by the physical design implementation of the proposed multiplier due to the internal routing of subsystems with the shortest-path algorithm. The proposed multiplier works better with higher-order multiplication and is suitable for high-end applications.
2
Madenda, Sarifuddin, Suryadi Harmanto, and Astie Darmayantie. "New Concept of Universal Binary Multiplication and Its Implementation on FPGA." Journal of Southwest Jiaotong University 56, no. 3 (2021): 124–39. http://dx.doi.org/10.35741/issn.0258-2724.56.3.11.
Der volle Inhalt der QuelleAnnotation:
This paper proposes the new improvements of signed binary multiplication equation, signed multiplier, and universal multiplier. The proposed multipliers have low complexity algorithms and are easy to implement into software and hardware. Both signed, and universal multipliers are embedded into FPGA by optimizing the use of LUTs (6-LUT and 5-LUT), carry chain Carry4, and fast carry logics: MUXCYs and XORCYs.Each one is implemented as a serial-parallel multiplier and parallel multiplier. The signed multiplier executes four types of multiplication, i.e., between two operands that each one can be a signed positive (SPN) or signed negative numbers (SNN). The universal multiplier can handle all (nine) types of multiplication, where each operand can be as unsigned(USN), signed positive, and signed negative numbers. For 8x8 bits, signed serial-parallel and signed parallel multipliers occupy19 LUTs and 58 LUTs with a logic time delay of 0.769 ns and 3.600 ns. Besides, for 8x8 bits, serial-parallel and parallel universal multipliers inhabit 21 LUTs and 60 LUTs with a logic time delay of 0.831ns and 3.677 ns, successively.
3
Mokhtar, Anis Shahida, Chew Sue Ping, Muhamad Faiz Md Din, Nazrul Fariq Makmor, and Muhammad Asyraf Che Mahadi. "Implementation of Booth Multiplier Algorithm using Radix-4 in FPGA." Jurnal Kejuruteraan si4, no. 1 (2021): 161–65. http://dx.doi.org/10.17576/jkukm-2021-si4(1)-20.
Der volle Inhalt der QuelleAnnotation:
This paper presentsthe performance of Radix-4 Modified Booth Algorithm. Booth algorithm is a multiplication algorithm that multiplies two signed binary numbers in two's complement notation. Multiplier is a fundamental component in general-purpose microprocessors and in digital signal processors. With advances in technology, researchers design multipliers which offer high speed, low power, and less area implementation. Booth multiplier algorithm is designed to reduce number of partial products as compared to conventional multiplier. The proposed design is simulated by using Verilog HDL in Quartus II and implemented in Cyclone II FPGA. The result shows that the average output delay is 20.78 ns. The whole design has been verified by gate level simulation.
4
Etiemble, Daniel, and Ramzi A. Jaber. "Design of (3,2) and (4,2) CNTFET Ternary Counters for Multipliers." Asian Journal of Research in Computer Science 16, no. 3 (2023): 103–18. http://dx.doi.org/10.9734/ajrcos/2023/v16i3349.
Der volle Inhalt der QuelleAnnotation:
The reduction trees of combinational multipliers are widely applying counters. To be able to compare the ternary and the binary approaches, Nanotube Field-Effect Transistor (CNTFET) ternary (3,2) and ternary (4,2) counters have been designed. The ternary (4,2) counter is compared with the binary (7,3) counter as both compute approximately the same amount of information. The binary counter is more efficient. However, comparing counters is not enough: in the Wallace reduction tree of the ternary multiplier, there are two times more lines to reduce compared to the binary one, as a 1-trit multiplier generates both product and carry terms. Comparing the Wallace tree of an 8*8-trit multiplier and a 12*12-bit binary one also shows that the binary implementation is the most efficient.
5
Alkurwy, Salah. "A novel approach of multiplier design based on BCD decoder." Indonesian Journal of Electrical Engineering and Computer Science 14, no. 1 (2019): 38–43. https://doi.org/10.11591/ijeecs.v14.i1.pp38-43.
Der volle Inhalt der QuelleAnnotation:
A novel approach of multiplier design is presented in this paper. The design idea is implemented based on binary coded decimal (BCD) decoder to seven segment display, by computing all the probability of multiplying 3×3 binary digits bits and grouping in table rows. The obtaining of the combinational logic functions is achieved by simplified the generated columns of [A5: A0], using a Karnaugh map. Then, the 3×3-bits multiplier circuit is used to implement the 6×6- and 12×12-bit multipliers. Comparing with a conventional multiplier, the proposed design outperformed in terms of the time delay by a 32% and 41.8% respectively. It is also reduced the combinational adaptive look-up-tables (ALUTs) by 24.6%, and 46% for both multipliers. Both overmentioned advantages make the proposed multipliers more attractive and suitable for high-speed digital systems.
6
Sharma, Virat, and Manju K. Chattopadhyay. "Implementation of Novel 2x2 Vedic Multiplier using QCA Technology." Journal of Physics: Conference Series 2603, no. 1 (2023): 012045. http://dx.doi.org/10.1088/1742-6596/2603/1/012045.
Der volle Inhalt der QuelleAnnotation:
Abstract Advantages like working at high speed, scalability, and lower power consumption make QCA technology more feasible than modern CMOS technology. QCA Technology uses electrons’ Coulombic interaction and polarization to represent binary information 0 and 1. The present paper proposes a novel XOR Gate and a Half Adder design and uses them to implement a new 2x2 Vedic Multiplier on QCA technology. A 2x2 Vedic Multiplier multiplies two inputs, of two bits each, using Urdhva-Tiryakbhyam Vedic Sutra. The proposed circuit has a reduced cell count and Quantum cost compared Co-planar Vedic Multipliers to available in the literature. QCADesigner 2.0.3 is used for the simulation and verification of all three proposed circuits.
7
Rajkumar, K. "Design and optimization of MSI-enabled multi-precision binary multiplier architecture." i-manager's Journal on Circuits and Systems 11, no. 2 (2023): 27. http://dx.doi.org/10.26634/jcir.11.2.20397.
Der volle Inhalt der QuelleAnnotation:
Arithmetic Logic Units (ALUs) are key elements within processors, executing a variety of operations including multiplication, division, addition, and subtraction. Among these, multiplication stands out as the most frequently utilized function within ALUs. This study presents an innovative MSI-interfaced multiplier architecture designed for integration into a multi-precision floating-point multiplier framework. This novel architecture offers configurations for 24-bit, 53-bit, 113-bit, and 237-bit binary operations, corresponding to single, double, quadruple, and octuple precision modes of floating-point computation. Notably, it enhances throughput by accommodating the multiplication of multiple batches of inputs with each operation initiation, surpassing existing binary multiplication systems. A unique Mantissa Similarity Investigation (MSI) implementation is developed and integrated into the binary multiplier architecture. Comparative analysis of the path delay in 24-bit mode against existing 24-bit multipliers demonstrates that the novel MSI-interfaced binary multiplier architecture, with and without MSI, exhibits reduced path delay compared to all existing systems, as anticipated.
8
Al-Nounou, Abd Al-Rahman, Osama Al-Khaleel, Fadi Obeidat, and Mohammad Al-Khaleel. "FPGA Implementation of Fast Binary Multiplication Based on Customized Basic Cells." JUCS - Journal of Universal Computer Science 28, no. (10) (2022): 1030–57. https://doi.org/10.3897/jucs.86282.
Der volle Inhalt der QuelleAnnotation:
Multiplication is considered one of the most time-consuming and a key operation in wide variety of embedded applications. Speeding up this operation has a significant impact on the overall performance of these applications. A vast number of multiplication approaches are found in the literature where the goal is always to achieve a higher performance. One of these approaches relies on using smaller multiplier blocks which are built based on direct Boolean algebra equations to build large multipliers. In this work, we present a methodology for designing binary multipliers where different sizes customized partial products generation (CPPG) cells are designed and used as smaller building blocks. The sizes of the designed CPPG cells are 2×2, 3×3, 4×4, 5×5, and 6×6. We use these cells to build 8×8, 16×16, 32×32, 64×64, and 128×128 binary multipliers. All of the CPPG cells and the binary multipliers are described using the VHDL language, tested, and implemented using XILINX ISE 14.6 tools targeting different FPGA families. The implementation results show that the best performance is achieved when cell 3×3 is used and Virtex-7 FPGA is targeted. The binary multipliers that are designed using the proposed CPPG cells achieve better performance when compared with the binary multipliers presented in the literature. As an application that utilizes the proposed multiplier, a Multiply-Accumulate (MAC) unit is designed and implemented in Spartan-3E. The implementation results of the MAC unit demonstrate the effectiveness of the proposed multiplier.
9
Kalimoldayev, M., S. Tynymbayev, M. Ibraimov, M. Magzom, Y. Kozhagulov, and T. Namazbayev. "PIPELINE MULTIPLIER OF POLYNOMIALS MODULO WITH ANALYSIS OF HIGH-ORDER BITS OF THE MULTIPLIER." BULLETIN 386, no. 4 (2020): 13–20. http://dx.doi.org/10.32014/2020.2518-1467.98.
Der volle Inhalt der QuelleAnnotation:
Among public-key cryptosystems, cryptosystems built on the basis of a polynomial system of residual classes are special. Because in these systems, arithmetic operations are performed at high speed. There are many algorithms for encrypting and decrypting data presented in the form of polynomials. The paper considers data encryption based on the multiplication of polynomials modulo irreducible polynomials. In such a multiplier, the binary image of a multiply polynomial can serve as a fragment of encrypted text. The binary image of the multiplier polynomial is the secret key and the binary representation of the irreducible polynomial is the module. Existing sequential polynomial multipliers and single-cycle matrix polynomial multipliers modulo do not provide the speed required by the encryption block. The paper considers the possibility of multiplying polynomials modulo on a Pipeline in which architectural techniques are laid in order to increase computing performance. In the conclusion of the work, the time gain of the multiplication modulo is shown by the example of the multiplication of five triples of polynomials. Verilog language was used to describe the scheme of the Pipeline multiplier. Used FPGA Artix-7 from Xilinx companies. The developed Pipeline multiplier can be used for cryptosystems based on a polynomial system of residual classes, which can be implemented in hardware or software.
10
Al-Nounou, Abd Al-Rahman, Osama Al-Khaleel, Fadi Obeidat, and Mohammad Al-Khaleel. "FPGA Implementation of Fast Binary Multiplication Based on Customized Basic Cells." JUCS - Journal of Universal Computer Science 28, no. 10 (2022): 1030–57. http://dx.doi.org/10.3897/jucs.86282.
Der volle Inhalt der QuelleAnnotation:
Multiplication is considered one of the most time-consuming and a key operation in wide variety of embedded applications. Speeding up this operation has a significant impact on the overall performance of these applications. A vast number of multiplication approaches are found in the literature where the goal is always to achieve a higher performance. One of these approaches relies on using smaller multiplier blocks which are built based on direct Boolean algebra equations to build large multipliers. In this work, we present a methodology for designing binary multipliers where different sizes customized partial products generation (CPPG) cells are designed and used as smaller building blocks. The sizes of the designed CPPG cells are 2×2, 3×3, 4×4, 5×5, and 6×6. We use these cells to build 8×8, 16×16, 32×32, 64×64, and 128×128 binary multipliers. All of the CPPG cells and the binary multipliers are described using the VHDL language, tested, and implemented using XILINX ISE 14.6 tools targeting different FPGA families. The implementation results show that the best performance is achieved when cell 3×3 is used and Virtex-7 FPGA is targeted. The binary multipliers that are designed using the proposed CPPG cells achieve better performance when compared with the binary multipliers presented in the literature. As an application that utilizes the proposed multiplier, a Multiply-Accumulate (MAC) unit is designed and implemented in Spartan-3E. The implementation results of the MAC unit demonstrate the effectiveness of the proposed multiplier.
11
Kogut, Ihor, Volodymyr Hryha, Bohdan Dzundza, Liudmyla Hryha, and Iryna Hatala. "Research and design of a matrix multiplier on FPGA." Advances in Cyber-Physical Systems 10, no. 1 (2025): 10–15. https://doi.org/10.23939/acps2025.01.010.
Der volle Inhalt der QuelleAnnotation:
This paper presents a comprehensive investi- gation and hardware implementation of a multi-bit Brawn matrix multiplier architecture. The research focuses on analyzing the system characteristics of binary multipliers realized with both conventional and optimized full and half adders. Particular attention has been given to the applicability of such multipliers within arithmetic logic units (ALUs) for vector and scalar processing architectures. Analytical models have been formulated to quantify hardware resource utilization and computational latency across various logic base configurations. The proposed multiplier has been described using the VHDL hardware description language and validated through functional simulation. The designs have been synthesized and implemented on Xilinx FPGA platforms. It has been established that the use of improved full and partial binary adders as part of the Brown matrix multiplier reduces the hardware complexity by a factor of 1,7 and increases the performance by a factor of 2,9 compared to the known classical structures of binary adders. The use of multibit Brown matrix multipliers with an improved element base allows to significantly speed up the execution time of the multiplication operation of special-purpose processors and vector and scalar supercomputers.
12
Kumar, Harish, Muhammad Rashid, Ahmed Alhomoud, Sikandar Zulqarnain Khan, Ismail Bahkali, and Saud S. Alotaibi. "A Scalable Digit-Parallel Polynomial Multiplier Architecture for NIST-Standardized Binary Elliptic Curves." Applied Sciences 12, no. 9 (2022): 4312. http://dx.doi.org/10.3390/app12094312.
Der volle Inhalt der QuelleAnnotation:
This work presents a scalable digit-parallel finite field polynomial multiplier architecture with a digit size of 32 bits for NIST-standardized binary elliptic fields. First, a dedicated digit-parallel architecture is proposed for each binary field recommended by NIST, i.e., 163, 233, 283, 409 and 571. Then, a scalable architecture having support for all variants of binary fields of elliptic curves is proposed. For performance investigation, we have compared dedicated multiplier architectures with scalable design. After this, the dedicated and scalable architectures are compared with the most relevant state-of-the-art multipliers. All multiplier architectures are implemented in Verilog HDL using the Vivado IDE tool. The implementation results are reported on a 28 nm Virtex-7 FPGA technology. The dedicated multipliers utilize slices of 1182 (for m=163), 1451 (for m=233), 1589 (for m=283), 2093 (for m=409) and 3451 (for m=571). Moreover, our dedicated designs can operate at a maximum frequency of 500, 476, 465, 451 and 443 MHz. Similarly, for all supported binary fields, our scalable architecture (i) utilizes 3753 slices, (ii) achieves 305 MHz clock frequency, (iii) takes 0.013 μs for one finite field multiplication and (iv) consumes 3.905 W power. The proposed scalable digit-parallel architecture is more area-efficient than most recent state-of-the-art multipliers. Consequently, the reported results and comparison to the state of the art reveal that the proposed architectures are well suited for cryptographic applications.
13
Kumar, Harish, Muhammad Rashid, Ahmed Alhomoud, Sikandar Zulqarnain Khan, Ismail Bahkali, and Saud S. Alotaibi. "A Scalable Digit-Parallel Polynomial Multiplier Architecture for NIST-Standardized Binary Elliptic Curves." Applied Sciences 12, no. 9 (2022): 4312. http://dx.doi.org/10.3390/app12094312.
Der volle Inhalt der QuelleAnnotation:
This work presents a scalable digit-parallel finite field polynomial multiplier architecture with a digit size of 32 bits for NIST-standardized binary elliptic fields. First, a dedicated digit-parallel architecture is proposed for each binary field recommended by NIST, i.e., 163, 233, 283, 409 and 571. Then, a scalable architecture having support for all variants of binary fields of elliptic curves is proposed. For performance investigation, we have compared dedicated multiplier architectures with scalable design. After this, the dedicated and scalable architectures are compared with the most relevant state-of-the-art multipliers. All multiplier architectures are implemented in Verilog HDL using the Vivado IDE tool. The implementation results are reported on a 28 nm Virtex-7 FPGA technology. The dedicated multipliers utilize slices of 1182 (for m=163), 1451 (for m=233), 1589 (for m=283), 2093 (for m=409) and 3451 (for m=571). Moreover, our dedicated designs can operate at a maximum frequency of 500, 476, 465, 451 and 443 MHz. Similarly, for all supported binary fields, our scalable architecture (i) utilizes 3753 slices, (ii) achieves 305 MHz clock frequency, (iii) takes 0.013 μs for one finite field multiplication and (iv) consumes 3.905 W power. The proposed scalable digit-parallel architecture is more area-efficient than most recent state-of-the-art multipliers. Consequently, the reported results and comparison to the state of the art reveal that the proposed architectures are well suited for cryptographic applications.
14
Shetty, P. Akshatha, and Dr Kiran V. "Area Efficient Modified Array Multiplier." Journal of University of Shanghai for Science and Technology 23, no. 09 (2021): 288–91. http://dx.doi.org/10.51201/jusst/21/09531.
Der volle Inhalt der QuelleAnnotation:
Multipliers are widely used for various application like signal processing. Multipliers are used for multiplication two binary data .There are different kinds of multipliers with their own advantages and disadvantages. In this paper we implemented Array multiplier which has considerably more speed but also more area, it was implemented using pseudo NMOS logic in Cadence software and the number of transistors was reduced from 2N to N+1 which also lead to reduction in area.
15
Choubey, Abhishek, and Shruti Bhargava Choubey. "An area-delay efficient Radix-8 12x12 Booth multiplier in CMOS for ML accelerator." ITM Web of Conferences 74 (2025): 02007. https://doi.org/10.1051/itmconf/20257402007.
Der volle Inhalt der QuelleAnnotation:
The multiplier is a significant module of graphics processing units (GPUs) and digital signal processing (DSP). These applications need low power consumption. This paper proposes a low-power radix-8 12-by-12 Booth multiplier. The proposed radix-8 Booth multiplier is implemented using an optimized Binary to 2-’s complement (B2C), convertor, and optimized multiplexer at each stage of the Booth multiplier architecture. The proposed architecture uses 23% less power and 12% less delay compared to existing architecture. To validate the results, all designs are synthesized using Cadence CMOS technology 45nm.
16
Dattatraya, Kore Sagar, Belgudri Ritesh Appasaheb, Ramdas Bhanudas Khaladkar, and V. S. Kanchana Bhaaskaran. "Low Power, High Speed and Area Efficient Binary Count Multiplier." Journal of Circuits, Systems and Computers 25, no. 04 (2016): 1650027. http://dx.doi.org/10.1142/s0218126616500274.
Der volle Inhalt der QuelleAnnotation:
Multiplier forms the core building block of any processor, such as the digital signal processor (DSP) and a general purpose microprocessor. As the word length increases, the number of adders or compressors required for the partial product addition also increases. The addition operation of the derived partial products determines the circuit latency, area and speed performance of wider word-length multipliers. Binary count multiplier (BCM) aims to reduce the number of adders and compressors through the use of a uniquely structured binary counter and by suitably altering the logical flow of partial product addition by using binary adders is proposed in this paper. The binary counters for varying bit count values are derived by modifying the basic 4:2 compressor circuit. A [Formula: see text] bit multiplier has been developed to validate the proposed computation method. This logic structure demonstrates lower power operation, reduced device count and lesser delay in comparison against the conventional Wallace tree multiplier structure found in the literature. The BCM implementation realizes 29.17% reduction in the device count, 66% reduction in the delay and 70% reduction in the power dissipation. Furthermore, it realizes 90% reduction in the power delay product (PDP) in comparison against the Wallace tree structure. The multiplier circuits have been implemented and the validation of results has been carried out using Cadence[Formula: see text] EDA tool. Forty five nanometer technology files have been employed for the designs and exhaustive SPICE simulations.
17
Chukkaluru, Ravi Shankar Reddy, Venkata Gopi Kumar Padavala, Manikandan Radhakrishnan, and Bhavana Kuruva. "A high speed and power efficient multiplier based on counterbased stacking." A high speed and power efficient multiplier based on counterbased stacking 32, no. 1 (2023): 98–106. https://doi.org/10.11591/ijeecs.v32.i1.pp98-106.
Der volle Inhalt der QuelleAnnotation:
High speed and competent addition of various operands is an essential operation in the design any computational unit. The swiftness and power competence of multiplier circuits plays vital role in enlightening the overall performance of microprocessors. Multipliers play crucial role in the design of arithmetic logic unit (ALU) or any digital signal processor (DSP) that are effectively employed for filtering and convolution operations. The process of multiplication either binary numbers or fixed-point numbers yields in enormous partial products that are to be added to get final product. These partial products in number and the process of summing up partial products dictate the latency and power consumption of the multiplier design. Here, we present a novel binary counter design that hires stacking circuits, that groups all logic “1” bits as one, followed by a novel symmetric method to merge pairs of 3-bit stacks into 6-bit stacks and then changes them to binary counts. This results in drastic improvements in power and area utilization of the multiplier. Additionally, this paper also focuses on implementation of novel approximate compressor and exploits the same for the design of approximate multipliers that can be effectively employed in any electronic systems that are characterized by power and speed constraints.
18
Arechabala, J., E. I. Boemo, J. Meneses, F. Moreno, and C. Lopez Barrio. "Full systolic binary multiplier." IEE Proceedings G Circuits, Devices and Systems 139, no. 2 (1992): 188. http://dx.doi.org/10.1049/ip-g-2.1992.0032.
Der volle Inhalt der Quelle
19
Alkurwy, Salah. "A novel approach of multiplier design based on BCD decoder." Indonesian Journal of Electrical Engineering and Computer Science 14, no. 1 (2019): 38. http://dx.doi.org/10.11591/ijeecs.v14.i1.pp38-43.
Der volle Inhalt der QuelleAnnotation:
<p><span>A novel approach of multiplier design is presented in this paper. The design </span>idea is implemented based on binary coded decimal (BCD) decoder to seven segment display, by computing all the probability of multiplying 3 3 binary digits bits and grouping in table rows. The obtaining of the combinational logic functions is achieved by simplified the generated columns of [A<sub>5: </sub>A<sub>0</sub>]<sub>, </sub>using a Karnaugh map. Then, the 3 3-bits multiplier circuit is used to implement the 6x6- and 12x 12-bit multipliers. Comparing with a conventional multiplier, the proposed design outperformed in terms of the time delay by a 32% and 41.8% respectively. It is also reduced the combinational adaptive look-up-tables (ALUTs) by 24.6%, and 46% for both multipliers. Both overmentioned advantages make the proposed multipliers more attractive and suitable for high-speed digital systems</p><p> </p><p> </p><p> </p><p> </p><p> </p><p> </p>
20
Faraji, S. Rasoul, Pierre Abillama, and Kia Bazargan. "Approximate Constant-Coefficient Multiplication Using Hybrid Binary-Unary Computing for FPGAs." ACM Transactions on Reconfigurable Technology and Systems 15, no. 3 (2022): 1–25. http://dx.doi.org/10.1145/3494570.
Der volle Inhalt der QuelleAnnotation:
Multipliers are used in virtually all Digital Signal Processing (DSP) applications such as image and video processing. Multiplier efficiency has a direct impact on the overall performance of such applications, especially when real-time processing is needed, as in 4K video processing, or where hardware resources are limited, as in mobile and IoT devices. We propose a novel, low-cost, low energy, and high-speed approximate constant coefficient multiplier (CCM) using a hybrid binary-unary encoding method. The proposed method implements a CCM using simple routing networks with no logic gates in the unary domain, which results in more efficient multipliers compared to Xilinx LogiCORE IP CCMs and table-based KCM CCMs (Flopoco) on average. We evaluate the proposed multipliers on 2-D discrete cosine transform algorithm as a common DSP module. Post-routing FPGA results show that the proposed multipliers can improve the {area, area × delay, power consumption, and energy-delay product} of a 2-D discrete cosine transform on average by {30%, 33%, 30%, 31%}. Moreover, the throughput of the proposed 2-D discrete cosine transform is on average 5% more than that of the binary architecture implemented using table-based KCM CCMs. We will show that our method has fewer routability issues compared to binary implementations when implementing a DCT core.
21
Shankar Reddy, Chukkaluru Ravi, Padavala Venkata Gopi Kumar, Radhakrishnan Manikandan, and Kuruva Bhavana. "A high speed and power efficient multiplier based on counter-based stacking." Indonesian Journal of Electrical Engineering and Computer Science 32, no. 1 (2023): 98. http://dx.doi.org/10.11591/ijeecs.v32.i1.pp98-106.
Der volle Inhalt der QuelleAnnotation:
<span>High speed and competent addition of various operands is an essential operation in the design any computational unit. The swiftness and power competence of multiplier circuits plays vital role in enlightening the overall performance of microprocessors. Multipliers play crucial role in the design of <a name="_Hlk140074299"></a>arithmetic logic unit (ALU) or any digital signal processor (DSP) that are effectively employed for filtering and convolution operations. The process of multiplication either binary numbers or fixed-point numbers yields in enormous partial products that are to be added to get final product. These partial products in number and the process of summing up partial products dictate the latency and power consumption of the multiplier design. Here, we present a novel binary counter design that hires stacking circuits, that groups all logic “1” bits as one, followed by a novel symmetric method to merge pairs of 3-bit stacks into 6-bit stacks and then changes them to binary counts. This results in drastic improvements in power and area utilization of the multiplier. Additionally, this paper also focuses on implementation of novel approximate compressor and exploits the same for the design of approximate multipliers that can be effectively employed in any electronic systems that are characterized by power and speed constraints.</span>
22
Shaik, Maznu. "Design and Performance Evaluation of Brent Kung Adder based 8-Bit Vedic Multiplier." International Journal for Research in Applied Science and Engineering Technology 12, no. 12 (2024): 825–30. https://doi.org/10.22214/ijraset.2024.65922.
Der volle Inhalt der QuelleAnnotation:
Multiplier is an essential functional block of a microprocessor because multiplication is needed to be performed repeatedly in almost all scientific calculations. Therefore, design of fast and low power binary multiplier is very important particularly for Digital Signal Processors. Vedic mathematics has improved the performance of multiplier. Vedic mathematics, a system of ancient Indian mathematics, which has a unique technique of solutions based on only 16 sutras. The novel point is the efficient use of Vedic algorithm (sutras) that reduces the number of computational steps considerably compared with any conventional method. This paper presents design and Performance Evaluation of Brent Kung Adder based 8-Bit Vedic Multiplier. Urdhva Tiryagbhyam sutra has been used for multiplication purpose. The partial product addition in Vedic multiplier is realized using Brent Kung Adder. Simulation results shows that described Brent Kung Adder based 8-Bit Vedic Multiplier is efficiently decreases the Delay, power consumption and Area than other multipliers.
23
Umer, Usama, Muhammad Rashid, Adel R. Alharbi, Ahmed Alhomoud, Harish Kumar, and Atif Raza Jafri. "An Efficient Crypto Processor Architecture for Side-Channel Resistant Binary Huff Curves on FPGA." Electronics 11, no. 7 (2022): 1131. http://dx.doi.org/10.3390/electronics11071131.
Der volle Inhalt der QuelleAnnotation:
This article presents an efficient crypto processor architecture for point multiplication acceleration of side-channel secured Binary Huff Curves (BHC) on FPGA (field-programmable gate array) over GF(2233). We have implemented six finite field polynomial multiplication architectures, i.e., (1) schoolbook, (2) hybrid Karatsuba, (3) 2-way-karatsuba, (4) 3-way-toom-cook, (5) 4-way-toom-cook and (6) digit-parallel-least-significant. For performance evaluation, each implemented polynomial multiplier is integrated with the proposed BHC architecture. Verilog HDL is used for the implementation of all the polynomial multipliers. Moreover, the Xilinx ISE design suite tool is employed as an underlying simulation platform. The implementation results are presented on Xilinx Virtex-6 FPGA devices. The achieved results show that the integration of a hybrid Karatsuba multiplier with the proposed BHC architecture results in lower hardware resources. Similarly, the use of a least-significant-digit-parallel multiplier in the proposed design results in high-speed (in terms of both clock frequency and latency). Consequently, the proposed BHC architecture, integrated with a least-significant-digit-parallel multiplier, is 1.42 times faster and utilizes 1.80 times lower FPGA slices when compared to the most recent BHC accelerator architectures.
24
Kumar, P. Sai, R. Swapna, and A. M. Siddhartha. "Design Analysis of Approximate Redundant Binary Multipliers." International Journal of Computer Science and Mobile Computing 11, no. 1 (2022): 74–94. http://dx.doi.org/10.47760/ijcsmc.2022.v11i01.010.
Der volle Inhalt der QuelleAnnotation:
As innovation scaling is arriving at its cutoff points, new methodologies have been proposed for computational effectiveness. Inexact processing is a promising method for elite execution and low power circuits as utilized in blunder lenient applications. Among surmised circuits, rough number juggling plans have drawn in huge exploration interest. In this paper, the plan of rough excess twofold (RB) multipliers is contemplated. Two inexact Booth encoders and two RB 4:2 blowers dependent on RB (full and half) adders are proposed for the RB multipliers. The inexact plan of the RB-Normal Binary (NB) converter in the RB multiplier is additionally concentrated by considering the mistake qualities of both the estimated Booth encoders and the RB blowers. Both rough and accurate ordinary incomplete item clusters are utilized in the surmised RB multipliers to meet distinctive exactness prerequisites. Mistake investigation and equipment reenactment results are given. The proposed surmised RB multipliers are contrasted and past rough Booth multipliers; the outcomes show that the estimated RB multipliers are superior to inexact NB Booth multipliers particularly when the word size is huge. Contextual investigations of blunder tough applications are likewise introduced to show the legitimacy of the proposed plans.
25
Chandrasekharan, Raji, and Sarappadi Narasimha Prasad. "Fault tolerant design for 8-bit Dadda multiplier for neural network applications." International Journal of Electrical and Computer Engineering (IJECE) 15, no. 3 (2025): 2697. https://doi.org/10.11591/ijece.v15i3.pp2697-2705.
Der volle Inhalt der QuelleAnnotation:
As digital electronic systems continue to shrink in size, they face increased susceptibility to transient errors, especially in critical applications like neural networks, which are not inherently error-resilient. Multipliers, fundamental components of neural networks, must be both fault tolerant and efficient. However, traditional fault free designs consume excessive power and require substantial silicon real estate. Among existing multiplier architectures, the Dadda multiplier stands out for its speed and efficiency, but it lacks fault tolerance needed for robust neural network applications. Therefore, there is need to design a power efficient and fault free Dadda multiplier that can address these challenges without significantly increasing power consumption or hardware complexity. In this paper a solution involving a fault tolerant Dadda multiplier optimized for neural network applications is proposed. Because of its speed and efficiency when compared to other multipliers Dadda multiplier is used as the base architecture which is designed using carry select adder (CSA) in conjunction with binary to excess one converter to reduce power and complexity. To enhance fault tolerance, self-repairing full adder is used to implement the CSA. This allows the system to detect and correct errors, ensuring robust operation in the presence of transient faults. This combination achieves a power efficient, fault tolerant multiplier with a power consumption of 52.3 mW, reflecting a 3% reduction in power compared to existing designs.
26
S, Chaitanya CV, Sundaresan C, P. R. Venkateswaran, and Keerthana Prasad. "ASIC design of low power-delay product carry pre-computation based multiplier." Indonesian Journal of Electrical Engineering and Computer Science 13, no. 2 (2019): 845–52. https://doi.org/10.11591/ijeecs.v13.i2.pp845-852.
Der volle Inhalt der QuelleAnnotation:
High speed and efficient multipliers are essential components in today’s computational circuits like digital signal processing, algorithms for cryptography and high performance processors. Invariably, almost all processing units will contain hardware multipliers based on some algorithm that fits the application requirement. Tremendous advances in VLSI technology over the past several years resulted in an increased need for high speed multipliers and compelled the designers to go for trade-offs among speed, power consumption and area. Amongst various methods of multiplication, Vedic multipliers are gaining ground due to their expected improvement in performance. A novel multiplier design for high speed VLSI applications using Urdhva-Tiryagbhyam sutra of Vedic Multiplication has been presented in this paper. The proposed architecture modeled using Verilog HDL, simulated using Cadence NCSIM and synthesized using Cadence RTL Compiler with 65nm TSMC library.The proposed multiplier architecture is compared with the existing multipliers and the results show significant improvement in speed and power dissipation.
27
Berezin, N. M., I. E. Chernetskaya, V. S. Panishchev, and A. M. Shabarov. "Development of a device for multiplying numbers by means of FPGA." Journal of Physics: Conference Series 2142, no. 1 (2021): 012001. http://dx.doi.org/10.1088/1742-6596/2142/1/012001.
Der volle Inhalt der QuelleAnnotation:
Abstract The authors propose the description of the development of a device for multiplying numbers. The device for multiplying numbers on the field-programmable gate array (FPGA) includes two input and one output registers, fifty-six single-digit adders, sixty four logic elements AND, one exclusive OR gate. The main scientific and technical task in developing a device for multiplying numbers is to reduce hardware complexity using single-bit adders and logic elements. Introduction includes description of works of scientists and researchers whose publications are devoted to design and development of multiplier construction methods, multiplier FIR performance improvement by right-shift and addition method on FPGA (field-programmable gate array) basis. The implementation of MAC-block, hardware implementation of binary multiplier on the basis of multi operand adder, multiplier design by right-sliding and addition with control automaton in the FPGA basis is the actual research tasks presented in a number of papers. The description of features of multiplier implementation, high-speed multipliers with variable bit rate, studies of approaches for designing modular multipliers, FPGA image processing using Brown multiplier for performing convolution operation find application in problems of performance and speed. Also, a number of authors describe implementation of conveyorization method, design of dual multiplier, construction method of 8-bit multiplier with reduced delay, 8-bit high-density systolic multiplier arrays on FPGA and development of high-performance 8-bit multiplier using McCMOS technology. A fragment of a developed device for multiplying numbers is presented in the work by the authors. The principle of operation of a device for multiplication is described. The description of connected elements of the device is given. The timing diagrams of operation of a device for multiplication of numbers are presented.
28
Etiemble, Daniel, and Ramzi Jaber. "Comparing Unbalanced and Balanced CNTFET Ternary Adders and Multipliers with the Corresponding Binary Ones." Asian Journal of Research in Computer Science 16, no. 4 (2023): 396–417. http://dx.doi.org/10.9734/ajrcos/2023/v16i4400.
Der volle Inhalt der QuelleAnnotation:
This paper compares the performance of the ternary adders and multipliers using balanced and unbalanced set of values. We use the 1-trit adders to evaluate the two versions of a 4-trit propagate adder, which are comparedwith a 6-bit corresponding propagate adder. Similarly, we compare the two types of 2*2 trit multipliers with a3*3 bit multiplier. The simulations with a 32-nm Carbon Nanotuble Field-Effect Transistor (CNTFET) technology show that the binary adders and multipliers are more efficient than the ternary ones that compute the same amount of information
29
Gao, Shuli, Dhamin Al-Khalili, J. M. Pierre Langlois, and Noureddine Chabini. "Efficient Realization of BCD Multipliers Using FPGAs." International Journal of Reconfigurable Computing 2017 (2017): 1–12. http://dx.doi.org/10.1155/2017/2410408.
Der volle Inhalt der QuelleAnnotation:
In this paper, a novel BCD multiplier approach is proposed. The main highlight of the proposed architecture is the generation of the partial products and parallel binary operations based on 2-digit columns. 1 × 1-digit multipliers used for the partial product generation are implemented directly by 4-bit binary multipliers without any code conversion. The binary results of the 1 × 1-digit multiplications are organized according to their two-digit positions to generate the 2-digit column-based partial products. A binary-decimal compressor structure is developed and used for partial product reduction. These reduced partial products are added in optimized 6-LUT BCD adders. The parallel binary operations and the improved BCD addition result in improved performance and reduced resource usage. The proposed approach was implemented on Xilinx Virtex-5 and Virtex-6 FPGAs with emphasis on the critical path delay reduction. Pipelined BCD multipliers were implemented for 4 × 4, 8 × 8, and 16 × 16-digit multipliers. Our realizations achieve an increase in speed by up to 22% and a reduction of LUT count by up to 14% over previously reported results.
30
Chaitanya, CVS, C. Sundaresan, R. Venkateswaran P, and Prasad Keerthana. "Design of modified booth based multiplier with carry pre-computation." Indonesian Journal of Electrical Engineering and Computer Science 13, no. 3 (2019): 1048–55. https://doi.org/10.11591/ijeecs.v13.i3.pp1048-1055.
Der volle Inhalt der QuelleAnnotation:
Arithmetic unit is the most important component of modern embedded computer systems. Arithmetic unit generally includes floating point and fixedpoint arithmetic operations and trigonometric functions. Multipliers units are the most important hardware structures in a complex arithmetic unit. With increase in chip frequency, the designer must be able to find the best set of trade-offs. The ability for faster computation is essential to achieve high performance in many DSP and Graphic processing algorithms and is why there is at least one dedicated Multiplier unit in all of the modern commercial DSP processors. Tremendous advances in VLSI technology over the past several years resulted in an increased need for high speed multipliers and compelled the designers to go for trade-offs among speed, power consumption and area. A novel modified booth multiplier design for high speed VLSI applications using pre-computation logic has been presented in this paper. The proposed architecture modeled using Verilog HDL, simulated using Cadence NCSIM and synthesized using Cadence RTL Compiler with 65nm TSMC library.The proposed multiplier architecture is compared with the existing multipliers and the results show significant improvement in speed and power dissipation.
31
Rashidi, Bahram, and Mohammad Abedini. "Efficient Lightweight Hardware Structures of Point Multiplication on Binary Edwards Curves for Elliptic Curve Cryptosystems." Journal of Circuits, Systems and Computers 28, no. 09 (2019): 1950149. http://dx.doi.org/10.1142/s0218126619501494.
Der volle Inhalt der QuelleAnnotation:
This paper presents efficient lightweight hardware implementations of the complete point multiplication on binary Edwards curves (BECs). The implementations are based on general and special cases of binary Edwards curves. The complete differential addition formulas have the cost of [Formula: see text] and [Formula: see text] for general and special cases of BECs, respectively, where [Formula: see text] and [Formula: see text] denote the costs of a field multiplication, a field squaring and a field multiplication by a constant, respectively. In the general case of BECs, the structure is implemented based on 3 concurrent multipliers. Also in the special case of BECs, two structures by employing 3 and 2 field multipliers are proposed for achieving the highest degree of parallelization and utilization of resources, respectively. The field multipliers are implemented based on the proposed efficient digit–digit polynomial basis multiplier. Two input operands of the multiplier proceed in digit level. This property leads to reduce hardware consumption and critical path delay. Also, in the structure, based on the change of input digit size from low digit size to high digit size the number of clock cycles and input words are different. Therefore, the multiplier can be flexible for different cryptographic considerations such as low-area and high-speed implementations. The point multiplication computation requires field inversion, therefore, we use a low-cost Extended Euclidean Algorithm (EEA) based inversion for implementation of this field operation. Implementation results of the proposed architectures based on Virtex-5 XC5VLX110 FPGA for two fields [Formula: see text] and [Formula: see text] are achieved. The results show improvements in terms of area and efficiency for the proposed structures compared to previous works.
32
Shikha, Singh, and B. Shukla Yagnesh. "Implementation of FinFET technology based low power 4×4 Wallace tree multiplier using hybrid full adder." TELKOMNIKA 21, no. 05 (2023): 1139–46. https://doi.org/10.12928/telkomnika.v21i5.24304.
Der volle Inhalt der QuelleAnnotation:
Many systems, including digital signal processors, finite impulse response (FIR) filters, application-specific integrated circuits, and microprocessors, use multipliers. The demand for low power multipliers is gradually rising day by day in the current technological trend. In this study, we describe a 4×4 Wallace multiplier based on a carry select adder (CSA) that uses less power and has a better power delay product than existing multipliers. HSPICE tool at 16 nm technology is used to simulate the results. In comparison to the traditional CSA-based multiplier, which has a power consumption of 1.7 µW and power delay product (PDP) of 57.3 fJ, the results demonstrate that the Wallace multiplier design employing CSA with first zero finding logic (FZF) logic has the lowest power consumption of 1.4 µW and PDP of 27.5 fJ.
33
Joe, Hounghun, and Youngmin Kim. "Novel Stochastic Computing for Energy-Efficient Image Processors." Electronics 8, no. 6 (2019): 720. http://dx.doi.org/10.3390/electronics8060720.
Der volle Inhalt der QuelleAnnotation:
Stochastic computing, which is based on probability, involves a trade-off between accuracy and power and is a promising solution for energy-efficiency in error-tolerance designs. In this paper, adder and multiplier circuits based on the proposed stochastic computing architecture are studied and analyzed. First, we propose an efficient yet simple stochastic computation technique for multipliers and adders by exchanging the wires used for their operation. The results demonstrate that the proposed design reduces the relative error in computation compared with the conventional designs and has smaller area compared to conventional designs. Then, a new energy-efficient and high-performance stochastic adder with acceptable error metrics is investigated. The proposed multiplier shows better error metrics than other existing stochastic multipliers, and significantly improves area utilization and power consumption compared to the exact binary multiplier. Finally, we apply the proposed stochastic architecture to an edge detection algorithm and achieve a significant reduction in area utilization (64%) and power consumption (96%). It is therefore demonstrated that the proposed stochastic architecture is suitable for energy-efficient hardware designs.
34
Gnanasekaran. "A Fast Serial-Parallel Binary Multiplier." IEEE Transactions on Computers C-34, no. 8 (1985): 741–44. http://dx.doi.org/10.1109/tc.1985.1676620.
Der volle Inhalt der Quelle
35
Lin, Rong. "A Regularly Structured Parallel Multiplier with Low-power Non-binary-logic Counter Circuits." VLSI Design 12, no. 3 (2001): 377–90. http://dx.doi.org/10.1155/2001/97598.
Der volle Inhalt der QuelleAnnotation:
A highly regular parallel multiplier architecture along with the novel low-power, high-performance CMOS implementation circuits is presented. The superiority is achieved through utilizing a unique scheme for recursive decomposition of partial product matrices and a recently proposed non-binary arithmetic logic as well as the complementary shift switch logic circuits.The proposed 64×64-b parallel multiplier possesses the following distinct features: (1) generating 64 8×8-b partial product matrices instead of a single large one; (2) comprising only four stages of bit reductions: first, by 8×8-b small parallel multipliers, then, by small parallel counters in each of the remaining three stages. A family of shift switch parallel counters, including non-binary (6, 3)∗ and complementary (k, 2) for 2 ≤ k ≤ 8, are proposed for the efficient bit reductions; (3) using a simple final adder.The non-binary logic operates 4-bit state signals (representing integers ranging from (0 to 3), where no more than half of the signal bits are subject to value-change at any logic stage. This and others including minimum transistor counts, fewer inverters, and low-leakage logic structure, significantly reduce circuit power dissipation.
36
Abdul-Hadi, Alaa Mohammed, Yousraa Abdul-sahib Saif-aldeen, and Firas Ghanim Tawfeeq. "Performance Evaluation of Scalar Multiplication in Elliptic Curve Cryptography Implementation using Different Multipliers Over Binary Field GF (2233)." Journal of Engineering 26, no. 9 (2020): 45–64. http://dx.doi.org/10.31026/j.eng.2020.09.04.
Der volle Inhalt der QuelleAnnotation:
This paper presents a point multiplication processor over the binary field GF (2233) with internal registers integrated within the point-addition architecture to enhance the Performance Index (PI) of scalar multiplication. The proposed design uses one of two types of finite field multipliers, either the Montgomery multiplier or the interleaved multiplier supported by the additional layer of internal registers. Lopez Dahab coordinates are used for the computation of point multiplication on Koblitz Curve (K-233bit). In contrast, the metric used for comparison of the implementations of the design on different types of FPGA platforms is the Performance Index.
 The first approach attains a performance index of approximately 0.217610202 when its realization is over Virtex-6 (6vlx130tff1156-3). It uses an interleaved multiplier with 3077 register slices, 4064 lookup tables (LUTs), 2837 flip-flops (FFs) at a maximum frequency of 221.6Mhz. This makes it more suitable for high-frequency applications. The second approach, which uses the Montgomery multiplier, produces a PI of approximately 0.2228157 when its implementation is on Virtex-4 (6vlx130tff1156-3). This approach utilizes 3543 slices, 2985 LUTs, 3691 FFs at a maximum frequency of 190.47MHz. Thus, it is found that the implementation of the second approach on Virtex-4 is more suitable for applications with a low frequency of about 86.4Mhz and a total number of slices of about 12305.
37
Rahul Pal. "Novel low PDP CMOS Double-Base Multiplier." Journal of Electrical Systems 20, no. 3 (2024): 6207–15. https://doi.org/10.52783/jes.6683.
Der volle Inhalt der QuelleAnnotation:
Multipliers play a vital role on digital low power communication system. This present study introduced a new novel strategy of multiplication that can improve speed-power efficiency with a double-based number system multiplier. Designing with a Double base number system multiplier is a suitable alternation due to its two important properties redundancy & sharpness. Extensive simulations has been done to examine the competency of proposed designs under three different test conditions to test . It then compares some of the critical parameters with excising single base number system (i.e. Binary number system) & Multi-value number system (i.e. Ternary Number system). All the design optimization & evaluations performed are based on the BSIM4 device parameter of TSMC 0.18µm CMOS technology with 0.9V supply at 27oC temperature using S. Edit of Tanner EDA..
38
Al-Khaleel, Osama, Zakaria Al-Qudah, Mohammad Al-Khaleel, Raed Bani-Hani, Christos Papachristou, and Francis Wolff. "Efficient Hardware Implementations of Binary-to-BCD Conversion Schemes for Decimal Multiplication." Journal of Circuits, Systems and Computers 24, no. 02 (2014): 1550019. http://dx.doi.org/10.1142/s021812661550019x.
Der volle Inhalt der QuelleAnnotation:
This paper proposes two high performance binary-to-binary coded decimal (BCD) conversion algorithms for use in BCD multiplication. These algorithms are based on splitting the 7-bit binary partial product of two BCD digits into two groups, computing the contribution of each group to the equivalent BCD partial product, and adding these contributions to compute the final BCD partial product. Designs for the proposed architectures and their implementations targeting both ASIC and FPGA are compared with others. Implementations of BCD array multipliers using both our conversion circuits and existing conversion circuits have been performed. The synthesis results for both ASIC and FPGA show that the proposed designs are faster and occupying less area than the state-of-the-art conversion circuits. Furthermore, the results obtained from comparing BCD multipliers of various sizes show that the enhancement in the area of the conversion circuit grows into a sizable area improvement in the multiplier circuit.
39
Vozna, Natalia, Yaroslav Nykolaychuk, and Alina Davletova. "Multi-bit structure improvement methods for multiplier devices of matrix type." Physico-mathematical modelling and informational technologies, no. 32 (July 7, 2021): 80–85. http://dx.doi.org/10.15407/fmmit2021.32.080.
Der volle Inhalt der QuelleAnnotation:
The article proposes methods for improving the structures of matrix multipliers of multi-digit numbers. Advanced single-bit total adders with paraphrase switched inputs and paraphrase outputs are used, intended as components of high-speed matrix multipliers. Based on the use of such single-bit adders, the structures of matrix multipliers are proposed, characterized by 2 times increased speed, 5 times reduced structural complexity compared to known multipliers based on classical single-bit adders. Optimization of structures of multi-bit matrix multipliers is offered. Comparative estimates of structural and temporal complexities of their circuit implementations depending on the bit size of multiplied binary numbers are given. The use of optimized circuit solutions of matrix multipliers can significantly improve the system characteristics of complex computing devices with many such components in the crystals of microelectronic technologies.
40
Hänninen, Ismo, and Jarmo Takala. "Binary multipliers on quantum-dot cellular automata." Facta universitatis - series: Electronics and Energetics 20, no. 3 (2007): 541–60. http://dx.doi.org/10.2298/fuee0703541h.
Der volle Inhalt der QuelleAnnotation:
This article describes the design of ultra-low-power multipliers on quantum dot cellular automata (QCA) nanotechnology, promising very dense circuits and high operating frequencies, using a single homogeneous layer of the basic cells. We construct structures without the earlier noise problems, verified by the QCA Designer coherence vector simulation. Our results show that the wiring overhead of the arithmetic circuits grows quadratically with the operand word length, and our pipelined array multiplier has linearly better performance-area efficiency than the previously proposed serial-parallel structure. Power analysis at the fundamental Landauer's limit shows, that the operating frequencies will indeed be bound by the energy dissipated in information erasure: under irreversible operation, the limits for the clock rates on molecular QCA are much lower, than the switching speeds of the technology.
41
Balasubramanian, Padmanabhan, Raunaq Nayar, Okkar Min, and Douglas L. Maskell. "Digital Image Blending by Inexact Multiplication." Electronics 11, no. 18 (2022): 2868. http://dx.doi.org/10.3390/electronics11182868.
Der volle Inhalt der QuelleAnnotation:
Digital image blending is commonly used in applications such as photo editing and computer graphics where two images are combined to produce a desired blended image. Digital images can be blended by addition or multiplication, and usually exact addition or multiplication is performed for image blending. In this paper, we evaluate the usefulness of inexact multiplication for digital image blending. Towards this, we describe how an exact array multiplier can be made inexact by introducing vertical cut(s) in it and assigning distinct combinations of binary values to the dangling inputs and product bits. We considered many 8-bit digital images for blending and the blended images obtained using exact and inexact multipliers are shown, which demonstrates the usefulness of inexact multiplication for image blending. For 8 × 8 image blending, one of our inexact array multipliers viz. IAM01-VC8 was found to achieve 63.3% reduction in area, 21% reduction in critical path delay, 72.3% reduction in power dissipation, and 78.1% reduction in energy compared to the exact array multiplier. In addition, IAM01-VC8 achieved 60.6% reduction in area, 9.7% reduction in critical path delay, 64.7% reduction in power dissipation, and 68.1% reduction in energy compared to the high-speed exact 8 × 8 multiplier that was automatically synthesized using a logic synthesis tool. The exact and inexact multipliers were physically realized using 32/28 nm CMOS process technology.
42
Xiao, Shuying. "Enhancing ASIC chip performance through integrated algorithm optimization." Applied and Computational Engineering 38, no. 1 (2024): 274–79. http://dx.doi.org/10.54254/2755-2721/38/20230563.
Der volle Inhalt der QuelleAnnotation:
As a crucial arithmetic logic unit, the multiplier plays a significant role in digital signal processing. However, multiplication operations often require a large number of calculations and logic gates, leading to increased circuit complexity and power consumption. To enhance the performance and efficiency of multipliers, this paper presents an optimization analysis based on the Wallace Tree and Booth algorithms. The Wallace Tree algorithm decomposes multiplication operations into multiple stages and employs both separate operations and bit-level parallelism to accelerate multiplication, achieving efficient parallel multiplication computations and reducing both latency and area complexity of multiplication. On the other hand, the Booth algorithm is an optimization method for signed binary multiplication. By introducing the concept of Booth encoding, it transforms signed multiplication into unsigned multiplication, thereby reducing the number of multiplication operations. This paper analyses the application and research progress of the Wallace Tree and Booth algorithms in the field of multiplier optimization to improve computational speed and reduce power consumption of multipliers.
43
Saha, Aloke, Rahul Pal, and Jayanta Ghosh. "Novel Self-Pipelining Approach for Speed-Power Efficient Reliable Binary Multiplication." Micro and Nanosystems 12, no. 3 (2020): 149–58. http://dx.doi.org/10.2174/1876402911666190916155445.
Der volle Inhalt der QuelleAnnotation:
Background: The present study explores a novel self-pipelining strategy that can enhance speed-power efficiency as well as the reliability of a binary multiplier as compared to state-of-art register and wavepipelining. Method: Proper synchronization with efficient clocking between the subsequent self-pipelining stages has been assured to design a self-pipelined multiplier. Each self-pipelining stage consists of self-latching leaf cells that are designed, optimized and evaluated by TSMC 0.18μm CMOS technology with 1.8V supply rail and at 25°C temperature. The T-Spice transient response and simulated results for the designed circuits are presented. The proposed idea has been applied to design 4-b×4-b self-pipelined Wallace- tree multiplier. The multiplier was validated for all possible test patterns and the transient response was evaluated. The circuit performance in terms of propagation delay, average power and Power-Delay- Product (PDP) is recorded. Next, the decomposition logic is applied to design a higher-order multiplier (i.e., 8-bit×8-bit and 16-bit×16-bit) based on the proposed strategy using 4-bit×4-bit self-pipelined multiplier. The designed multiplier was also validated through extensive TSpice simulation for all the required test patterns using W-Edit and the evaluated performance is presented. All the designs, optimizations and evaluations performed are based on BSIM3 device parameter of TSMC 0.18μm CMOS technology with 1.8V supply rail at 25°C temperature using S-Edit of Tanner EDA. Results: The reliability was investigated of the proposed 4-b×4-b multiplier in the temperature range - 40°C to 100°C for maximum PDP variation. Conclusion: A benchmarking analysis in terms of speed-power performance with recent competitive design reveals preeminence of the proposed technique.
44
Saundatti, Yasmeen. "Design and Implementation of Four Bit Binary Array Multiplier." International Journal of Scientific Engineering and Research 4, no. 11 (2016): 25–27. https://doi.org/10.70729/ijser151038.
Der volle Inhalt der Quelle
45
M, A. Sayyad, and S. Agarkar B. "Modified Architecture for Nikhilam Navatshcaramam Dashath (NND) Vedic Multiplier." Indian Journal of Science and Technology 16, no. 42 (2023): 3727–34. https://doi.org/10.17485/IJST/v16i42.733.
Der volle Inhalt der QuelleAnnotation:
Abstract <strong>Objectives:</strong> Speed of multiplication in Digital Signal Processing (DSP) applications plays an important role in generating the result quickly. There is scope for reducing the propagation delay in multiplication by designing the multiplier circuit based on the Vedic mathematics (formulas) sutras. This study aims to design the multiplier circuit based on Nikhilam Navatshcaramam Dashath (NND) of Vedic mathematics for improvement in speed, power, and area. <strong>Methods:</strong> The multiplier circuit based on NND method is designed for the multiplier and multiplicand less than as well as greater than the nearest base in the binary number system. The architecture is designed for both. The proposed multiplier is implemented with VHDL on Vertex-7, Device: XC7VX485T Package: FFG1157, FPGA board using Xilinx ISE 14.7, and its power dissipation is calculated using XPower analyzer. The performance of the proposed multiplier is compared with the conventional array multiplier, Vedic multiplier and also compared with the architecture reported in the literature.<strong> Findings:</strong> In the proposed architecture n bit multiplier and multiplicand are divided into n/2 bits, two parts, and processed through n/2 bit multiplier and n bit adder. This method converted the n bit multiplication into n/2 bit multiplication and n bit addition. The proposed architecture is efficient in terms of area, delay and power as compared to the array and Vedic Urdhva Tiryakbyham (UT) multiplier. The 4 bit NND multiplier is 26.72 % delay and 47.05 % area efficient as compared to the reported architecture 1. To compare with other reported architecture, the results are also taken on Artix-7, Device: XC7A100T Package: CSG324, and Spartan-6, Device: XC6SLX4 Package: TQG144 FPGA. The results demonstrate an improvement in processing speed as well as power consumption. This method is a special case of multiplication and is efficient if the multiplicand and multiplier are close to the base value. In this implementation, the multiplier and multiplicand are split into two parts and processed; hence, the algorithm will give the correct result for a specific range of multipliers and multiplicands. The accuracy analysis of the proposed multiplier is also performed for multipliers and multiplicands far away from the base value. The maximum error is 7.94%. <strong>Novelty:</strong> The architecture used in this system converts n-bit multiplication into n bit addition and n/2 bit multiplication, which can be used for the numbers below the base value. For values greater than the base value, on which very little work has been documented in the literature, the NND multiplier is implemented in this study. <strong>Keywords:</strong> Array Multiplier, Vedic Multiplier, Urdhva Tiryakbyham(UT) Multiplier, Nikhilam Navatshcaramam Dashath (NND), Filed Programmable Gate Array (FPGA)
46
Aaron D’costa, Mr, Dr Abdul Razak, and Dr Shazia Hasan. "Analysis and comparison of fast multiplier circuits based on different parameters." International Journal of Engineering & Technology 7, no. 3 (2018): 1189. http://dx.doi.org/10.14419/ijet.v7i3.12945.
Der volle Inhalt der QuelleAnnotation:
Digital multiplier circuits are used in computers. A multiplier is an electronic circuit used in digital electronics to multiply two binary numbers. Multiplier circuits are used in ALU for binary multiplication of signed and unsigned numbers. The delay, area and power consumption are the 3 most important design specifications a chip designer has to consider. Delay of the circuit is directly proportional to the delay of a multiplier. Increased delay in the multiplier leads to higher delay in the circuit. Therefore research is carried out as to how to reduce the delay of the multiplier block so as to reduce the delay of whole circuit. The main purpose is to deal with high speed and lower power consumption even after decreasing the silicon area. This makes them well-suited for numerous complex and convenient VLSI circuit implementations. The fact however, remains that area and speed are two contradictory performance restrictions. Hence, increase in speed always results in the use of more and complex hardware. Different arithmetic techniques can be used to implement different multiplier circuits. The focus of this paper is to implement various multiplier circuit and compare them. The timing signals can be observed using software such as Modelsim and Xilinx.
47
Baesler, Malte, Sven-Ole Voigt, and Thomas Teufel. "A Decimal Floating-Point Accurate Scalar Product Unit with a Parallel Fixed-Point Multiplier on a Virtex-5 FPGA." International Journal of Reconfigurable Computing 2010 (2010): 1–13. http://dx.doi.org/10.1155/2010/357839.
Der volle Inhalt der QuelleAnnotation:
Decimal Floating Point operations are important for applications that cannot tolerate errors from conversions between binary and decimal formats, for instance, commercial, financial, and insurance applications. In this paper, we present a parallel decimal fixed-point multiplier designed to exploit the features of Virtex-5 FPGAs. Our multiplier is based on BCD recoding schemes, fast partial product generation, and a BCD-4221 carry save adder reduction tree. Pipeline stages can be added to target low latency. Furthermore, we extend the multiplier with an accurate scalar product unit for IEEE 754-2008decimal64data format in order to provide an important operation with least possible rounding error. Compared to a previously published work, in this paper, we improve the architecture of the accurate scalar product unit and migrate to Virtex-5 FPGAs. This decreases the fixed-point multiplier's latency by a factor of two and the accurate scalar product unit's latency even by a factor of five.
48
Reddy, K. Swetha, Surabhi Seethai, Akanksha, Meenakshi, and V. Sagar Reddy. "ASIC Implementation of Bit Matrix Multiplier." E3S Web of Conferences 391 (2023): 01028. http://dx.doi.org/10.1051/e3sconf/202339101028.
Der volle Inhalt der QuelleAnnotation:
In computer science and digital electronics, a bit matrix multiplier (BMM) is a mathematical operation that is used to quickly multiply binary matrices. BMM is a basic component of many computer algorithms and is utilized in fields including machine learning, image processing, and cryptography. BMM creates a new matrix that represents the product of the two input matrices by performing logical AND and XOR operations on each matrix element’s binary value. BMM is a crucial method for large-scale matrix operations since it has a lower computational complexity than conventional matrix multiplication. Reduced computational complexity: When compared to conventional matrix multiplication algorithms, BMM has a lower computational complexity since it performs matrix multiplication using bitwise operations like logical AND and XOR. Faster processing speeds are the result, particularly for complex matrix computations. Less memory is needed to store the binary values of the matrices in BMM because these values can be expressed using Boolean logic. As a result, less memory is needed, and the resources can be used more effectively.
49
Abdulbaqia, Alaa Ghazi, and Yasir Hashim. "Design and Implementation of General Hardware Binary Multiplier (2n x 2n) Bits." Journal of Physics: Conference Series 2312, no. 1 (2022): 012084. http://dx.doi.org/10.1088/1742-6596/2312/1/012084.
Der volle Inhalt der QuelleAnnotation:
Abstract In this paper, a new general 2n x 2n bits hardware multiplier based on combinatorial has been designed, implemented and analysed. First, a new design for circuit to multiply two binary numbers with 2n bits length, this new design starts with basic 2x2 bits circuit multiplier, n here equal to 1. Then based on this circuit, the 4x4 bits circuit multiplier has been designed. And based on 4x4, the 8x8 bits multiplier has been designed and continually the 16x16 bits multiplier. The final design for general 2nx2n bits multiplier has been presented. All these circuits have been mathematically proved and tested to get the final results.
50
Utsav, Kumar Malviya. "High-speed radix-10 multiplication using partial shifter adder tree-based convertor." TELKOMNIKA Telecommunication, Computing, Electronics and Control 19, no. 2 (2021): pp. 556~563. https://doi.org/10.12928/TELKOMNIKA.v19i2.14991.
Der volle Inhalt der QuelleAnnotation:
A radix-10 multiplication is the foremost frequent operations employed by several monetary business and user-oriented applications, decimal multiplier using in state of art digital systems are significantly good but can be upgraded with time delay and area optimization. This work is proposed a more area and time delay optimized new design of overloaded decimal digit set (ODDS) architecture-based radix-10 multiplier for signed numbers. Binary coded decimal (BCD) to binary followed by binary multiplication and finally binary to BCD conversion are 3 major modules employed in radix-10 multiplication. This paperwork presents a replacement technique for binary coded decimal (BCD) to binary and vice-versa convertors in radix-10 multiplication. A novel addition tree structure called as partial shifter adder (PSA) tree-based approach has been developed for BCD to binary conversion, and it is used to add partially generated products. To meet our major concern i.e. speed, we need particular high-speed multiplication, hence the proposed PSA based radix-10 multiplier is using vertical cross binary multiplication and concurrent shifter based addition method. The design has been tested on 45nm technology-based Zynq-7 field programmable gate array (FPGA) devices with a 6-input lookup table (LUTs). A combinational implementation maps quite well into the slice structure of the Xilinx Zynq-7 families field programmable gate array. The synthesis results for a Zynq-7 device indicate that our design outperforms in terms of the area and time delay.