Thematische Bibliographien / Circuits - computer hardware

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Auswahl der wissenschaftlichen Literatur zum Thema „Circuits - computer hardware“

Autor: Grafiati

Veröffentlicht am 28. Juli 2024

Zuletzt aktualisiert am 31. Juli 2025

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Zeitschriftenartikel zum Thema "Circuits - computer hardware"

Curtis, K. M. "Warnier-Orr: An Electronic Hardware Design Methodology." International Journal of Electrical Engineering & Education 26, no. 3 (1989): 197–205. http://dx.doi.org/10.1177/002072098902600302.

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The paper considers the application of a well-known computer programming methodology to the design of electronic circuits. Parallels are drawn between real-life situations, computer programs and electronic circuit design. Examples of the application of the methodology are given in each case.

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Weder, Benjamin, Johanna Barzen, Frank Leymann, and Marie Salm. "Automated Quantum Hardware Selection for Quantum Workflows." Electronics 10, no. 8 (2021): 984. http://dx.doi.org/10.3390/electronics10080984.

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The execution of a quantum algorithm typically requires various classical pre- and post-processing tasks. Hence, workflows are a promising means to orchestrate these tasks, benefiting from their reliability, robustness, and features, such as transactional processing. However, the implementations of the tasks may be very heterogeneous and they depend on the quantum hardware used to execute the quantum circuits of the algorithm. Additionally, today’s quantum computers are still restricted, which limits the size of the quantum circuits that can be executed. As the circuit size often depends on th

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Kreppel, Fabian, Christian Melzer, Diego Olvera Millán, et al. "Quantum Circuit Compiler for a Shuttling-Based Trapped-Ion Quantum Computer." Quantum 7 (November 8, 2023): 1176. http://dx.doi.org/10.22331/q-2023-11-08-1176.

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The increasing capabilities of quantum computing hardware and the challenge of realizing deep quantum circuits require fully automated and efficient tools for compiling quantum circuits. To express arbitrary circuits in a sequence of native gates specific to the quantum computer architecture, it is necessary to make algorithms portable across the landscape of quantum hardware providers. In this work, we present a compiler capable of transforming and optimizing a quantum circuit targeting a shuttling-based trapped-ion quantum processor. It consists of custom algorithms set on top of the quantum

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Castro, Lucas, and Rodolfo Azevedo. "Circuitly: A visual and constructive framework for teaching digital circuits." International Journal of Computer Architecture Education 9, no. 1 (2020): 10–15. http://dx.doi.org/10.5753/ijcae.2020.4839.

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This paper describes an interactive and student-friendly framework for teaching digital circuits and computer architecture topics. It aims to improve students learning process by providing a visual drag-and-drop circuit design editor, interactive simulation, signal monitoring and testbench tools - all integrated in a widely accessible application that runs in the browser. Circuitly does so in a programmatic way, to help students better understand the Hardware Description Languages they will encounter in the future.

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Odame, K., and P. E. Hasler. "Nonlinear Circuit Analysis via Perturbation Methods and Hardware Prototyping." VLSI Design 2010 (March 18, 2010): 1–8. http://dx.doi.org/10.1155/2010/687498.

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Nonlinear signal processing is necessary in many emerging applications where form factor and power are at a premium. In order to make such complex computation feasible under these constraints, it is necessary to implement the signal processors as analog circuits. Since analog circuit design is largely based on a linear systems perspective, new tools are being introduced to circuit designers that allow them to understand and exploit circuit nonlinearity for useful processing. This paper discusses two such tools, which represent nonlinear circuit behavior in a graphical way, making it easy to de

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Zhu, D., N. M. Linke, M. Benedetti, et al. "Training of quantum circuits on a hybrid quantum computer." Science Advances 5, no. 10 (2019): eaaw9918. http://dx.doi.org/10.1126/sciadv.aaw9918.

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Generative modeling is a flavor of machine learning with applications ranging from computer vision to chemical design. It is expected to be one of the techniques most suited to take advantage of the additional resources provided by near-term quantum computers. Here, we implement a data-driven quantum circuit training algorithm on the canonical Bars-and-Stripes dataset using a quantum-classical hybrid machine. The training proceeds by running parameterized circuits on a trapped ion quantum computer and feeding the results to a classical optimizer. We apply two separate strategies, Particle Swar

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Gao, Hua Qiang, Yu Jing Wang, Shou Qiang Kang, Zhang Le, Jian Qing Wang, and Jing Jing Wei. "Realization of Digital Chaotic Signal Generation Circuits." Applied Mechanics and Materials 716-717 (December 2014): 1352–55. http://dx.doi.org/10.4028/www.scientific.net/amm.716-717.1352.

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To overcome the shortcomings of realizing chaotic system by analog circuits, digital chaotic signal generation circuits based on DSP are designed. Computer simulation of chaotic system is performed firstly, and the discrete equations are obtained using discretization algorithm. On this basis, the design of hardware circuits based on DSP is made, and the corresponding C programs are constructed. Through the debugging of software and hardware, digital design of chaotic system based on DSP is achieved, and chaotic attractor is observed through an oscilloscope by digital-to-analog conversion circu

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Tezak, Nikolas, Armand Niederberger, Dmitri S. Pavlichin, Gopal Sarma, and Hideo Mabuchi. "Specification of photonic circuits using quantum hardware description language." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 370, no. 1979 (2012): 5270–90. http://dx.doi.org/10.1098/rsta.2011.0526.

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Following the simple observation that the interconnection of a set of quantum optical input–output devices can be specified using structural mode VHSIC hardware description language, we demonstrate a computer-aided schematic capture workflow for modelling and simulating multi-component photonic circuits. We describe an algorithm for parsing circuit descriptions to derive quantum equations of motion, illustrate our approach using simple examples based on linear and cavity-nonlinear optical components, and demonstrate a computational approach to hierarchical model reduction.

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Li, Zeyu, Junjie Wang, Zhao Huang, Nan Luo, and Quan Wang. "Towards Trust Hardware Deployment of Edge Computing: Mitigation of Hardware Trojans based on Evolvable Hardware." Applied Sciences 12, no. 13 (2022): 6601. http://dx.doi.org/10.3390/app12136601.

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Hardware Trojans (HTs) are malicious hardware components designed to leak confidential information or cause the chip/circuit on which they are integrated to malfunction during operation. When we deploy such hardware platforms for edge computing, FPGA-based implementations of Coarse-Grained Reconfigurable Array (CGRA) are also currently falling victim to HT insertion. However, for CGRA, an evolvable hardware (EHW) platform, which has the ability to dynamically change its configuration and behavioral characteristics based on inputs from the environment, provides us with a new way to mitigate HT

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Hu, Wei, Armaiti Ardeshiricham, and Ryan Kastner. "Hardware Information Flow Tracking." ACM Computing Surveys 54, no. 4 (2021): 1–39. http://dx.doi.org/10.1145/3447867.

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Information flow tracking (IFT) is a fundamental computer security technique used to understand how information moves through a computing system. Hardware IFT techniques specifically target security vulnerabilities related to the design, verification, testing, manufacturing, and deployment of hardware circuits. Hardware IFT can detect unintentional design flaws, malicious circuit modifications, timing side channels, access control violations, and other insecure hardware behaviors. This article surveys the area of hardware IFT. We start with a discussion on the basics of IFT, whose foundations

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Dissertationen zum Thema "Circuits - computer hardware"

Stamoulis, Iakovos. "Computer graphics hardware using ASICs, FPGAs and embedded logic." Thesis, University of Sussex, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.313943.

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The introduction of new technologies such as Field Programmable Gate Arrays (FPGAs) with high gate counts and embedded memory Applications Specific Integrated Circuits (ASICs) gives greater scope to the design of computer graphics hardware. This thesis investigates the features of the current generation of FPGAs and complex programmable logic devices (CPLD) and assesses their suitability as replacements for ASIC technologies, and as prototyping tools for their verification prior to fabrication. The traditional methodologies and techniques used for digital systems are examined for application t

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Dutta, Sumit Ph D. Massachusetts Institute of Technology. "Magnetic logic circuits with high bit resolution for hardware acceleration." Thesis, Massachusetts Institute of Technology, 2017. http://hdl.handle.net/1721.1/111997.

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Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2017. This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections. Cataloged from student-submitted PDF version of thesis. Includes bibliographical references (pages 109-120). The ever-increasing demand for high-performance and low-power computing warrants an investigation of technologies beyond conventional digital transistor circuits. We explore a logic device based on magnetic domai

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Staunstrup, Jørgen. "A formal approach to hardware design /." Boston [u.a.] : Kluwer Acad. Publ, 1994. http://www.loc.gov/catdir/enhancements/fy0820/93043582-d.html.

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Wang, Xiao-Lin 1955. "A TRANSLATER OF CLOCK MODE VHDL HARDWARE DESCRIPTION LANGUAGE." Thesis, The University of Arizona, 1986. http://hdl.handle.net/10150/291295.

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Taesopapong, Somboon. "A VLSI-nMOS hardware implementation of a high speed parallel adder." Ohio : Ohio University, 1986. http://www.ohiolink.edu/etd/view.cgi?ohiou1183379787.

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Basak, Abhishek. "INFRASTRUCTURE AND PRIMITIVES FOR HARDWARE SECURITY IN INTEGRATED CIRCUITS." Case Western Reserve University School of Graduate Studies / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=case1458787036.

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Meana, Richard William Piper. "Approximate Sub-Graph Isomorphism For Watermarking Finite State Machine Hardware." Scholar Commons, 2013. http://scholarcommons.usf.edu/etd/4728.

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We present a method of mitigating theft of sequential circuit Intellectual Property hardware designs through means of watermarking. Hardware watermarking can be performed by selectively embedding a watermark in the state encoding of the Finite State Machine. This form of watermarking can be achieved by matching a directed graph representation of the watermark with a sub-graph in state transition graph representation of the FSM. We experiment with three approaches: a brute force method that provides a proof of concept, a greedy algorithm that provides excellent runtime with a drawback of sub-op

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Imvidhaya, Ming. "VHDL simulation of the implementation of a costfunction circuit." Thesis, Monterey, California : Naval Postgraduate School, 1990. http://handle.dtic.mil/100.2/ADA240430.

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Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, September 1990. Thesis Advisor(s): Lee, Chin-Hwa. Second Reader: Butler, Jon T. "September 1990." Description based on title screen as viewed on December 29, 2009. DTIC Identifier(s): Computerized simulation, computer aided design, logic circuits, subroutines, theses, integrated circuits. Author(s) subject terms: VHDL, costfunction, hardware description language. Includes bibliographical references (p. 77). Also available in print.

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Chu, Ming-Cheung. "Hazard detection with VHDL in combinational logic circuits with fixed delays." Thesis, This resource online, 1992. http://scholar.lib.vt.edu/theses/available/etd-10062009-020040/.

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Moseley, Ralph. "Transcending static deployment of circuits : dynamic run-time systems and mobile hardware processes for FPGAs." Thesis, University of Kent, 2002. https://kar.kent.ac.uk/13733/.

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The usefulness of reconfigurable hardware has been shown in research and commercial applications. Unquestionably, this has and will lead to, unique avenues of thought within computer science being explored. The interest by researchers in some specific areas has led to manufacturers developing devices which were enhanced in their ability to dynamically be configured within a run-time context. These improvements are on-going and rapid progress is being made, producing high density, system-on-a-chip capable devices, with fast run-time reconfiguration. The advancements in this technology have part

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Bücher zum Thema "Circuits - computer hardware"

1953-, Sanchez Eduardo, and Tomassini Marco 1949-, eds. Towards evolvable hardware: The evolutionary engineering approach. Springer, 1996.

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Kropf, Thomas. Introduction to Formal Hardware Verification. Springer Berlin Heidelberg, 1999.

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Wang, Li-Guo. Abstraction of hardware construction. LFCS, Dept. of Computer Science, University of Edinburgh, 1995.

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Drechsler, Rolf. Formal Verification of Circuits. Springer US, 2000.

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Luís, Gomes, Lavagno Luciano 1959-, and Yakovlev Alex, eds. Hardware design and petri nets. Kluwer Academic, 2000.

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R, Kime Charles, ed. Logic and computer design fundamentals. 2nd ed. Prentice Hall, 2000.

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R, Kime Charles, ed. Logic and computer design fundamentals. 3rd ed. Prentice Hall, 2004.

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R, Kime Charles, ed. Logic and computer design fundamentals. Prentice Hall, 1997.

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Carlos, Delgado Kloos, and Damm Werner, eds. Practical formal methods for hardware design. Springer, 1997.

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Goossens, K. G. W. Structure and behaviour in hardware verification. LFCS, Dept. of Computer Science, University of Edinburgh, 1993.

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Buchteile zum Thema "Circuits - computer hardware"

Tan, Huiyu, Xi Yang, Fu Song, Taolue Chen, and Zhilin Wu. "Compositional Verification of Cryptographic Circuits Against Fault Injection Attacks." In Lecture Notes in Computer Science. Springer Nature Switzerland, 2024. http://dx.doi.org/10.1007/978-3-031-71177-0_13.

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AbstractFault injection attack is a class of active, physical attacks against cryptographic circuits. The design and implementation of countermeasures against such attacks are intricate, error-prone and laborious, necessitating formal verification to guarantee their correctness. In this paper, we propose the first compositional verification approach for round-based hardware implementations of cryptographic algorithms. Our approach decomposes a circuit into a set of single-round sub-circuits which are verified individually by either SAT/SMT- or BDD-based tools. Our approach is implemented as an

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Leander, Gregor, Christof Paar, Julian Speith, and Lukas Stennes. "HAWKEYE – Recovering Symmetric Cryptography From Hardware Circuits." In Lecture Notes in Computer Science. Springer Nature Switzerland, 2024. http://dx.doi.org/10.1007/978-3-031-68385-5_11.

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Galindez Olascoaga, Laura I., Wannes Meert, Nimish Shah, and Marian Verhelst. "Dynamic Complexity Tuning for Hardware-Aware Probabilistic Circuits." In Communications in Computer and Information Science. Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-66770-2_21.

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Cullen, Jamie. "Evolving Digital Circuits in an Industry Standard Hardware Description Language." In Lecture Notes in Computer Science. Springer Berlin Heidelberg, 2008. http://dx.doi.org/10.1007/978-3-540-89694-4_52.

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Tang, Yongkang, Jianye Wang, Shaoqing Li, Jihua Chen, and Binbin Yang. "Microsecond-Level Temperature Variation of Logic Circuits and Influences of Infrared Cameras’ Parameters on Hardware Trojans Detection." In Communications in Computer and Information Science. Springer Singapore, 2016. http://dx.doi.org/10.1007/978-981-10-3159-5_7.

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Li, Hui, and He Bai. "Overview of Co-Governed Multi-Identifier Network." In Principle of Architecture, Protocol, and Algorithms for CoG-MIN. Springer Nature Singapore, 2025. https://doi.org/10.1007/978-981-96-3596-2_2.

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Abstract The Internet architecture, established in the 1960s and 1970s, addressed the challenge of resource sharing among hosts during an era limited by hardware constraints. With subsequent advances in integrated circuits, network equipment evolved to offer enhanced computing power at a lower cost. This progress fueled the rapid expansion of computer networks, leading to the proliferation of applications like e-commerce, digital media, social networking, and content distribution in the last decade. Today’s Internet users care more about the content itself than how and where to get it. Consequ

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Jabbari, Tahereh, Yerzhan Mustafa, Eby G. Friedman, and Selçuk Köse. "Hardware Security of SFQ Circuits." In Design Automation of Quantum Computers. Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-031-15699-1_7.

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Yu, Emily, Armin Biere, and Keijo Heljanko. "Progress in Certifying Hardware Model Checking Results." In Computer Aided Verification. Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-81688-9_17.

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AbstractWe present a formal framework to certify k-induction-based model checking results. The key idea is the notion of a k-witness circuit which simulates the given circuit and has a simple inductive invariant serving as proof certificate. Our approach allows to check proofs with an independent proof checker by reducing the certification problem to pure SAT checks and checking a simple QBF with one quantifier alternation. We also present Certifaiger, the resulting certification toolkit, and evaluate it on instances from the hardware model checking competition. Our experiments show the practi

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Bharath, R., G. Arun Sabari, Dhinesh Ravi Krishna, et al. "Malicious Circuit Detection for Improved Hardware Security." In Communications in Computer and Information Science. Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-22915-7_42.

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Cortadella, Jordi, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, and Alex Yakovlev. "Hardware and Petri Nets Application to Asynchronous Circuit Design." In Lecture Notes in Computer Science. Springer Berlin Heidelberg, 2000. http://dx.doi.org/10.1007/3-540-44988-4_1.

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Konferenzberichte zum Thema "Circuits - computer hardware"

Su, Wenqiang, and Wei Zhang. "Design of ECT Hardware Circuit for Complex Flow." In 2024 8th International Symposium on Computer Science and Intelligent Control (ISCSIC). IEEE, 2024. https://doi.org/10.1109/iscsic64297.2024.00099.

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Chang, Leland. "Short Course: Architecture and Design Approaches to ML Hardware Acceleration: Performance Compute Environment." In 2024 IEEE International Solid-State Circuits Conference (ISSCC). IEEE, 2024. https://doi.org/10.1109/isscc49657.2024.11007241.

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Tong, Fu, and Jiang Shaojun. "Hardware Circuit Design of Intelligent Door Lock Based on C Language." In 2024 IEEE 2nd International Conference on Sensors, Electronics and Computer Engineering (ICSECE). IEEE, 2024. http://dx.doi.org/10.1109/icsece61636.2024.10729549.

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Li, Zhenghao, Yang Zhang, Xing Hu, Shaoqing Li, and Bin Liang. "Hardware Trojan Detection Based on Circuit Sequence Features with GRU Neural Network." In 2024 IEEE Symposium on Computers and Communications (ISCC). IEEE, 2024. http://dx.doi.org/10.1109/iscc61673.2024.10733599.

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Jin, Wenjing, Jeonghun Gong, and Jae W. Lee. "FPGA Implementation of Hardware-based Demand Paging on RISC- V Architecture." In 2024 International Technical Conference on Circuits/Systems, Computers, and Communications (ITC-CSCC). IEEE, 2024. http://dx.doi.org/10.1109/itc-cscc62988.2024.10628195.

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Huang, Da, Huimin Liu, Qiang Dou, and Zhuo Ma. "Hardware Design of Single-Precision Floating-Point Number Squaring Circuit Based on Modified Non-Restoring Algorithm." In 2024 6th International Conference on Communications, Information System and Computer Engineering (CISCE). IEEE, 2024. http://dx.doi.org/10.1109/cisce62493.2024.10653319.

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Knichel, David, and Amir Moradi. "Low-Latency Hardware Private Circuits." In CCS '22: 2022 ACM SIGSAC Conference on Computer and Communications Security. ACM, 2022. http://dx.doi.org/10.1145/3548606.3559362.

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Qian, Yiwen, and Hongshi Sang. "Binary network design for dedicated hardware circuits." In Pattern Recognition and Computer Vision, edited by Zhong Chen, Yang Xiao, Hanyu Hong, et al. SPIE, 2024. http://dx.doi.org/10.1117/12.2692626.

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Korenek, J. "Hardware acceleration in computer networks." In 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). IEEE, 2013. http://dx.doi.org/10.1109/ddecs.2013.6549780.

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Hu, Dong, Dong Zhou, and Ping Li. "Research on Hardware Built-in Computer Safety." In 2006 International Conference on Communications, Circuits and Systems. IEEE, 2006. http://dx.doi.org/10.1109/icccas.2006.284976.

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