Dissertationen zum Thema „Clock network design“

The main objective of this thesis is to design reliable clock-distribution networks and power-delivery networks for three-dimensional integrated circuits (3D ICs) using through-silicon vias (TSVs). This dissertation supports this goal by addressing six research topics. The first four works focus on 3D clock tree synthesis for low power, pre-bond testability, TSV-induced obstacle avoidance, and TSV utilization. The last two works develop modeling approaches for reliability analysis on 3D power-delivery networks. In the first work, a clock synthesis algorithm is developed for low-power and low-slew 3D clock network design. The impact of various design parameters on clock performance, including the wirelength, clock power, clock slew, and skew, is investigated. These parameters cover the TSV count, TSV parasitics, the maximum loading capacitance of the clock buffers, and the supply voltage. In the second work, a clock synthesis algorithm is developed to construct 3D clock networks for both pre-bond testability and post-bond operability. Pre-bond testing of 3D stacked ICs involves testing each individual die before bonding, which can improve the overall yield of 3D ICs by avoiding stacking defective dies with good ones. Two key techniques including TSV-buffer insertion and redundant tree generation are implemented to minimize clock skew and ensure pre-bond testing. The impact of TSV utilization and TSV parasitics on clock power is also investigated. In the third work, an obstacle-aware clock tree synthesis method is presented for through-silicon-via (TSV)-based 3D ICs. A unique aspect of this problem lies in the fact that various types of TSVs become obstacles during 3D clock routing including signal, power/ground, and clock TSVs. These TSVs may occupy silicon area or routing layers. The generated clock tree does not sacrifice wirelength or clock power too much and avoids TSV-induced obstacles. In the fourth work, a decision-tree-based clock synthesis (DTCS) method is developed for low-power 3D clock network design, where TSVs form a regular 2D array. This TSV array style is shown to be more manufacturable and practical than layouts with TSVs located at irregular spots. The DTCS method explores the entire solution space for the best TSV array utilization in terms of low power. Close-to-optimal solutions can be found for power efficiency with skew minimization in short runtime. In the fifth work, current crowding and its impact on 3D power grid integrity is investigated. Due to the geometry of TSVs and connections to the global power grid, significant current crowding can occur. The current density distribution within a TSV and its connections to the global power grid is explored. A simple TSV model is implemented to obtain current density distributions within a TSV and its local environment. This model is checked for accuracy by comparing with identical models simulated using finite element modeling methods. The simple TSV models are integrated with the global power wires for detailed chip-scale power analysis. In the sixth work, a comprehensive multi-physics modeling approach is developed to analyze electromigration (EM) in TSV-based 3D connections. Since a TSV has regions of high current density, grain boundaries play a significant role in EM dominating atomic transport. The transient analysis is performed on atomic transport including grain and grain boundary structures. The evolution of atomic depletion and accumulation is simulated due to current crowding. And the TSV resistance change is modeled.

Clock Distribution Networks play a vital role in performance and reliability of a system. However, temperature gradients observed in 3D ICs hamper the functionality of CDNs in terms of varying skew and propagation delay. This thesis presents two compensation techniques, Adaptive Voltage and Controllable Delay, to overcome these problems. The compensation methods are validated using a FPGA-based test vehicle. Modification in traditional buffer design are also presented and the performance as well as the area and power overhead of both the implementations is compared.

A low-cost radio direction finding (RDF) VHF receiver has been investigated for development into a radio direction finding network (RDFN) with a particular focus towards public service and commercial asset tracking applications. The primary design criteria were reproducibility, low-cost, and simplicity such that public service and volunteer organizations can benefit from the technology. Two receiver designs were built and tested to allow for comparison of practicality, cost, and accuracy. A pseudo-Doppler RDF and a time difference of arrival (TDOA) receiver were built as proof-of-concept for a system design based on commercial off-the-shelf (COTS) components. The pseudo-Doppler system is a less practical implementation due to the necessity for custom hardware, a large antenna system, and an increased directional error due to multipath and weak signals. The TDOA system has potential as a very simple and low-cost RDFN implementation, but requires extremely accurate time synchronization that is difficult to achieve using COTS GPS receiver modules. The final proposed solution takes advantage of the simple TDOA hardware and multiple detection techniques (including signal strength) to produce improved locational data and ultimately provide a more accurate estimate of position. Further development and improvements to this receiver design have the potential for implementation as a low-cost radio direction finding network.

Power consumption of CMOS digital logic designs has increased rapidly for the last several years. It has become an important issue, not only in battery-powered applications, but also in high-performance digital designs because of packaging and cooling requirements. At multi-GHz clock rates in use today, charging and discharging CMOS gates and wires, especially in clocks with their relatively large capacitances, leads to significant power consumption. Recovering and recycling the stored charge or energy about to be lost when these nodes are discharged to ground is a potentially good strategy that must be explored for use in future energy-efficient design methodologies. This dissertation investigates a number of novel clock energy recycling techniques to improve the overall power dissipation of high-performance logic circuits. If efficient recycling energy of the clock network can be demonstrated, it might be used in many high-performance chip designs, to lower power and save energy. A number of chip prototypes were designed and constructed to demonstrate that this energy can be successfully recycled or recovered in different ways: • Recycling clock network energy by supplying a secondary DC-DC power converter: the output of this power converter can be used to supply another region of the chip, thereby avoiding the need to draw additional energy from the primary supply. One test chip demonstrates energy in the final clock load can be recycled, while another demonstrates that clock distribution energy can be recycled. • Recovering clock network energy and returning it back to the power grid: each clock cycle, a portion of the energy just drawn from the supply is transferred back at the end of the cycle, effectively reducing the power consumption of the clock network. The recycling methods described in this thesis are able to preserve the more ideal square clock shape which has been a limitation of previous work in this area. Overall, the results provided in this thesis demonstrate that energy recycling is very promising and must be pursued in a number of other areas of the chip in order to obtain an energy-efficient design.

All-Optical networks have been proposed as a solution to meet growing demand for broadband access. An essential component in these networks will be new Clock and Data Recovery devices which can recover burst-mode traffic. This a significantly different challenge from conventional, continuous-mode CDR. Burst-mode data originates at various sources and arrives at the receiver with different phases, potentially changing by +/-pi Rads. Therefore, new CDR designs are required to adapt to large steps in phase upon each new burst to maintain BER integrity. This must be accomplished on the order of ns if All-Optical networks are to be viable. While several such designs have been proposed, a clear solution has yet to emerge. This thesis proposes broadband PLLs as a new solution for burst-mode Clock and Data Recovery. The design of a completed broadband Phase-locked CDR ASIC is presented, from original device modeling to implementation and testing.

In this work, the synthesis of biopolymer-based hydrogel networks with defined architecture is presented. In order to obtain materials with defined properties, the chemoselective copper-catalyzed azide-alkyne cycloaddition (or Click Chemistry) was used for the synthesis of gelatin-based hydrogels. Alkyne-functionalized gelatin was reacted with four different diazide crosslinkers above its sol-gel transition to suppress the formation of triple helices. By variation of the crosslinking density and the crosslinker flexibility, the swelling (Q: 150-470 vol.-%;) and the Young’s and shear moduli (E: 50 kPa - 635 kPa, G’: 0.1 kPa - 16 kPa) could be tuned in the kPa range. In order to understand the network structure, a method based on the labelling of free functional groups within the hydrogel was developed. Gelatin-based hydrogels were incubated with alkyne-functionalized fluorescein to detect the free azide groups, resulting from the formation of dangling chains. Gelatin hydrogels were also incubated with azido-functionalized fluorescein to check the presence of alkyne groups available for the attachment of bioactive molecules. By using confocal laser scanning microscopy and fluorescence spectroscopy, the amount of crosslinking, grafting and free alkyne groups could be determined. Dangling chains were observed in samples prepared by using an excess of crosslinker and also when using equimolar amounts of alkyne:azide. In the latter case the amount of dangling chains was affected by the crosslinker structure. Specifically, 0.1% of dangling chains were found using 4,4’-diazido-2,2’-stilbene-disulfonic acid as cosslinker, 0.06% with 1,8-diazidooctane, 0.05% with 1,12-diazidododecane and 0.022 % with PEG-diazide. This observation could be explained considering the structure of the crosslinkers. During network formation, the movements of the gelatin chains are restricted due to the formation of covalent netpoints. A further crosslinking will be possible only in the case of crosslinker that are flexible and long enough to reach another chain. The method used to obtain defined gelatin-based hydrogels enabled also the synthesis of hyaluronic acid-based hydrogels with tailorable properties. Alkyne-functionalized hyaluronic acid was crosslinked with three different linkers having two terminal azide functionalities. By variation of the crosslinking density and crosslinker type, hydrogels with elastic moduli in the range of 0.5-3 kPa have been prepared. The variation of the crosslinking density and crosslinker type had furthermore an influence also on the hydrolytic and enzymatic degradation of gelatin-based hydrogels. Hydrogels with a low crosslinker amount experienced a faster decrease in mass loss and elastic modulus compared to hydrogels with higher crosslinker content. Moreover, the structure of the crosslinker had a strong influence on the enzymatic degradation. Hydrogels containing a crosslinker with a rigid structure were much more resistant to enzymatic degradation than hydrogels containing a flexible crosslinker. During hydrolytic degradation, the hydrogel became softer while maintaining the same outer dimensions. These observations are in agreement with a bulk degradation mechanism, while the decrease in size of the hydrogels during enzymatic degradation suggested a surface erosion mechanism. Because of the use of small amount of crosslinker (0.002 mol.% 0.02 mol.%) the networks synthesized can still be defined as biopolymer-based hydrogels. However, they contain a small percentage of synthetic residues. Alternatively, a possible method to obtain biopolymer-based telechelics, which could be used as crosslinkers, was investigated. Gelatin-based fragments with defined molecular weight were obtained by controlled degradation of gelatin with hydroxylamine, due to its specific action on asparaginyl-glycine bonds. The reaction of gelatin with hydroxylamine resulted in fragments with molecular weights of 15, 25, 37, and 50 kDa (determined by SDS-PAGE) independently of the reaction time and conditions. Each of these fragments could be potentially used for the synthesis of hydrogels in which all components are biopolymer-based materials.
In dieser Arbeit wird die Synthese Biopolymer-basierter Hydrogelnetzwerke mit definierter Architektur beschrieben. Um Materialien mit definierten und einstellbaren Eigenschaften zu erhalten, wurde die chemoselektive Kupferkatalysierte Azid-Alkin-Cycloadditionsreaktion (auch als Click-Chemie bezeichnet) für die Synthese Gelatine-basierter Netzwerke eingesetzt. Alkin-funktionalisierte Gelatine wurde mit vier verschiedenen Diazid-Quervernetzern oberhalb der Gel-Sol-Übergangstemperatur umgesetzt, um die Formierung tripelhelikaler Bereiche durch Gelatineketten zu unterdrücken. Durch Variation der Menge an Quervernetzer (und damit der Netzdichte) sowie der Länge und Flexibilität der Quervernetzer konnten u.a. die Quellung (Q: 150-470 vol.-%) sowie der Young’s - und Schermodul im kPa Bereich eingestellt werden (E: 50 kPa - 635 kPa, G’: 0.1 kPa - 16 kPa). Um die Netzwerkarchitektur zu verstehen, wurde eine Methode basierend auf dem Labeln unreagierter Azid- und Alkingruppen im Hydrogel entwickelt. Die Gelatine-basierten Hydrogele wurden mit Alkin-funktionalisiertem Fluorescein umgesetzt, um freie Azidgruppen zu detektieren, die bei einem Grafting entstehen. Darüber hinaus wurden die Hydrogele mit Azid-funktionalisiertem Fluorescein reagiert, um die Menge an freien Alkingruppen zu bestimmen, die zudem potentiell für die Anbindung bioaktiver Moleküle geeignet sind. Quervernetzung, Grafting, und die Anzahl freier Alkingruppen konnten dann mit Hilfe der konfokalen Laser Scanning Mikroskopie und der Fluoreszenzmikroskopie qualitativ und quantitativ nachgewiesen werden. Gegraftete Ketten wurden in Systemen nachgewiesen, die mit einem Überschuss an Quervernetzer hergestellt wurden, entstanden aber auch beim Einsatz äquimolarer Mengen Alkin- und Azidgruppen. Im letzteren Fall wurde in Abhängigkeit von der Struktur des Diazids unterschiedliche Anteile gegrafteter Ketten festgestellt. 0.1 mol-% von gegrafteten Ketten wurden für 4,4’-Diazido-2,2’-stilbendisulfonsäure gefunden, 0.06 mol-% für 1,8-Diazidooktan, 0.05 mol% für 1,12-diazidododecan und 0.022 mol-% für PEG-Diazid. Diese Beobachtung kann durch die unterschiedliche Flexibilität der Vernetzer erklärt werden. Während der Netzwerkbildung werden die Bewegungen der Gelatineketten eingeschränkt, so dass kovalente Netzpunkte nur erhalten werden können, wenn der Vernetzer lang und flexibel genug ist, um eine andere Alkingruppe zu erreichen. Die Strategie zur Synthese von Biopolymer-basierten Hydrogelen mit einstellbaren Eigenschaften wurde von Gelatine- auf Hyaluronsäure-basierte Gele übertragen. Alkin-funktionalisierte Hyaluronäure wurde mit drei verschiedenen Diaziden quervernetzt, wobei Menge, Länge, und Flexibilität des Quervernetzers variiert wurden. In dieser Weise wurden sehr weiche Hydrogele mit E-Moduli im Bereich von 0.5-3 kPa hergestellt. Die Variation der Vernetzungsdichte und des Vernetzertyps beeinflusste weiterhin den hydrolytischen und enzymatischen Abbau der Hydrogele. Hydrogele mit einem geringerem Anteil an Quervernetzer wurden schneller abgebaut als solche mit einem höheren Quervernetzeranteil. Darüber hinaus konnte gezeigt werden, dass Hydrogele mit Quervernetzern mit einer rigiden Struktur deutlich langsamer degradierten als Hydrogele mit flexibleren Quervernetzern. Während des hydrolytischen Abbau wurden die Materialien weicher, behielten aber ihre Form bei, was mit einem Bulk-Abbau-Modell übereinstimmt. Während des enzymatischen Abbaus hingegen änderten sich die Materialeigenschaften kaum, jedoch wurden die Proben kleiner. Diese Beobachtung stimmt mit einem Oberflächenabbaumechanismus überein. Da in allen vorgestellten Systemen nur eine kleine Menge synthetischer Vernetzer eingesetzt wurde (0.002 – 0.02 mol%), können die Materialien noch als Biopolymer-basierte Materialien klassifiziert werden. Jedoch enthalten die Materialien synthetische Abschnitte. In Zukunft könnte es interessant sein, einen Zugang zu Materialien zu haben, die ausschließlich aus Biopolymeren aufgebaut sind. Daher wurde der Zugang zu Biopolymer basierten Telechelen untersucht, die potentiell als Vernetzer dienen können. Dazu wurden durch die kontrollierte Spaltung von Gelatine mit Hydroxylamin Gelatinefragmente mit definiertem Molekulargewicht hergestellt. Hydroxalamin reagiert unter Spaltung mit der Amidbindung zwischen Asparagin und Glycin, wobei Aspartylhydroxamate und Aminoendgruppen entstehen. Die Reaktion von Gelatine mit Hydroxylamin ergab Fragmente mit Molekulargewichten von 15, 25, 37, und 50 kDa (bestimmt mit SDS-PAGE), und die Formierung dieser Fragmente war unabhängig von den weiteren Reaktionsbedingungen und der Reaktionszeit. Jedes dieser Fragmente kann potentiell für die Synthese von Hydrogelen eingesetzt werden, die ausschließlich aus Biopolymeren bestehen.

Les arbres classiques de distribution du signal d'horloge au sein des microprocesseurs synchrones présentent un certain nombre de limitations : skew, jitter, limitation de la fréquence, influence de perturbations et de dispersions quelles que soient leurs natures. Ces facteurs, critiques pour les microprocesseurs modernes complexes, sont devenus la raison principale qui a poussé à la recherche d'autres types d'architecture de génération et de distribution du signal d'horloge. Un exemple d'un tel système alternatif est le réseau de PLLs couplées, où les PLLs sont géographiquement distribuées sur la puce, et génèrent des signaux d'horloge locaux qui sont ensuite synchronisés, en temps réel, par un échange d'information entre les PLLs voisines et une rétroaction locale réalisé par leur correcteurs. La nature active du réseau de PLLs de génération et de distribution du signal d'horloge, qui peut permettre de surpasser les limitations mentionnées plus tôt, oblige à sortir du cadre classique des outils et des méthodes de la Microélectronique habituellement appliqués à l'étude et à la conception de ce type de systèmes. En effet, les aspects dynamiques de bouclage et de transformation de signaux au sein de tels systèmes complexes rendent leur conception extrêmement difficile voire parfois impossible. La difficulté principale consiste en un changement des propriétés d'un sous-système local indépendant par rapport aux propriétés du même sous-système faisant partie du réseau. Effectivement, il existe beaucoup de méthodes et d'outils de conception d'une PLL isolée garantissant un comportement et des propriétés locales désirés. Néanmoins, ces propriétés désirées locales, selon la topologie d'interconnexion considérée, ne sont pas forcément conservées quand il s'agit d'un réseau de PLLs interconnectées et de son comportement global. Le but principal de cette thèse est ainsi de développer une méthode de synthèse de la loi de commande décentralisée réalisée au sein de chaque sous-système (tel qu'une PLL) assurant le comportement désiré pour le réseau global. Une méthode de transformation du problème de synthèse globale en un problème équivalent de synthèse d'une loi de commande locale est proposée en se basant sur l'hypothèse des sous-systèmes identiques interconnectés en réseau. Le lien entre les propriétés locales et globales est établi grâce aux approches d'Automatique avancée telles que les approches entrée-sortie et la dissipativité. Ce choix de méthode permet non seulement de réduire considérablement la complexité du problème initial mais aussi de ramener le problème de synthèse à une forme proche des méthodes de conception locale utilisées en Microélectronique, ce qui garantit une continuité logique de leur évolution. Ensuite la méthode proposée est combinée avec la commande H∞ et l'optimisation sous contraintes LMIs conduisant au développement d'algorithmes efficaces de résolution du problème posé. Elles sont à la fois particulièrement bien adaptées à l'application considérée, c'est-à-dire à la synchronisation d'un réseau de PLLs, et sont facilement généralisables aux autres types de problèmes de commande de systèmes de grande dimension. Le premier aspect permet une intégration naturelle et aisée de la méthode dans le flux de conception existant en Microélectronique, très riche et mature à ce jour, alors que le deuxième offre une solution à d'autres problèmes de commande de systèmes interconnectés en réseau, un champ d'application aujourd'hui en plein essor.

Integrated systems with billions of transistors on a single chip are a now reality. These systems include multi-core microprocessors and are built today using deca-nanometer devices organized into synchronous digital circuits. The movement of data within such systems is regulated by a set of predictable timing signals, called clocks, which must be distributed to a large number of sequential elements. Collectively, these clocks have a significant impact on the frequency of operation and, consequently, on the performance of the systems. The clocks are also responsible for a large fraction of the power consumed by these systems. The objective of this dissertation is to better understand clock distribution in order to identify opportunities and strategies for improvement by analyzing the conditions under which the optimal tradeoff between power and performance can be achieved, by modeling the constraints associated with local and global clocking, by evaluating the impact of noise, and by investigating promising new design strategies for future integrated systems.

This research work focuses mainly on the design and synthesis of Differential Clock Distribution Networks (DCDNs). The Clock Distribution Network (CDN) plays an important role in synchronous systems. The network is spread all over the chip to synchronize its sub-systems. The system performance is influenced by the performance of its clock network. As technology advances and the complexity increases, a drastic growth in the chip complexity in the near future is expected. Thus designing a reliable CDN is becoming a must, and therefore all the design efforts should be utilized to efficiently design clock distribution networks. Of importance in chip design are low power and low noise concepts. Differential signaling scheme offers high noise immunity and since it is associated with signal amplitudes lower than the usual, it may contribute to reduce power consumption as well. Due to these potentials, the design and analysis of DCDN has been the focus of this research work. First, a line equivalent delay model based on the decoupling method is proposed to be able to route DCDNs with minimum skew. This part refers to the routing and synthesis of DCDNS. Later, new configurations for differential buffers based on body-biased transistors are proposed, which show better performance for future low voltage applications. Finally, a circuit and system design method that reduces the power consumption of DCDNs is proposed. This is accomplished in two steps: First circuit configurations that reduce the differential voltage swing giving less power consumption are introduced. Later, by reducing the supply voltage, a DCDN is designed which has the same power consumption as single-node CDNs, but has less skew variation in the presence of external noises such as power supply fluctuations.

碩士
國立臺北科技大學
電腦與通訊研究所
99
The multicore system is more popular architecture in recently. The NoC (Network-on-Chip) architecture is proposed to solve the problem of high performance and throughput in a multicore system but it derived some problems such as of power consumption, area and deadlock, etc. This paper proposes a buffer clock-gating (BCG) architecture to improve the power consumption and area of buffers in Network-on-Chip. When buffer content is full or empty, the BCG uses clock-gating technology to gating buffer period to reduce power consumption. When data packet length is 10 bits: comparison with IntelliBuffer [2], the proposed method reduced 16.8% on power consumption, 45.9% on area and 2.7% on time delay and comparison with [3], the proposed method reduced 38% on power consumption and 15.2% on area. When data packet length is 18 bits: comparison with IntelliBuffer [2], the proposed method reduced 22.4% on power consumption, 40.9% on area and 2% on time delay and comparison with [3], the proposed method reduced 32.9% on power consumption, 13% on area and 2% on time delay.

As VLSI fabrication technology scales, an increasing number of processing elements (cores) on a chip makes on-chip communication a new performance bottleneck. The Network-on-Chip (NoC) paradigm has emerged as an efficient and scalable infrastructure to handle the communication needs for such multi-core systems. In most existing NoCs, design decisions are made assuming that the NoC operates at the same or lower clock speed as the cores, which slows down the communication system. A major challenge in designing a high speed NoC is the difficulty of distributing a high speed, low power clock across the chip. In this dissertation, we first propose several techniques to address the issue of distributing a high-speed, low power, low jitter clock across the IC. We primarily focus our attention on resonant standing wave oscillators (SWOs), which have recently emerged as a promising technique for high-speed, low power clock generation. In addition, we also present a dynamic programming based approach to synthesize a low jitter, low power buffered H-tree for clock distribution. In the second part of this dissertation, we use these efficient clock distribution schemes to present a novel fast NoC design that relies on source synchronous data transfer over a ring. In our source-synchronous design, the clock and data NoC are routed in parallel yielding a fast, robust design. Architectural simulations on synthetic and real traffic show that our source-synchronous NoC designs can provide significantly lower latency while achieving the same or better bandwidth compared to a state of the art mesh, while consuming lower area. The fact that the our ring-based NoC runs significantly faster than the mesh contributes to these improvements. Moreover, since our proposed NoC designs are fully synchronous, they are very amenable to testing as well. In the last part of this dissertation, we explore an alternate scheme of achieving high-speed on-chip data transfer using sinusoidal signals of different frequencies. The key advantage of our method is the ability to superimpose such sinusoids and thereby effectively send multiple logic values along the same wire in a clock cycle. Experimental results show that for the same throughput as that of a traditional scheme, we require significantly fewer wires.

Clock skew caused by variation is one of the most important problems in clock network synthesis today. Even if a clock network is designed to have zero skew, variation such as capacitive load and power supply will cause differences in arrival time of a clock signal. Non-tree clock network is considered to be an effective way to address the skew variation problem. Due to its inherent redundancy, clock mesh is very tolerant to variation. However, it costs much excessive amount of power compared to a clock tree. Link based non-tree clock network is an economic way to reduce clock skew caused by variation. Instead of using a dense mesh, only a number of links are inserted into a tree, so the power increase is small. Several existing works focus on the effect of cross link as well as the construction of such cross link structure. However, it is still not very clear where cross links should be inserted to achieve the most clock skew reduction with small wire resources. In this thesis, we propose a new method using linear program to solve this problem. In our approach, clock skew in a non-tree clock network is computed using an idea of load redistribution and non-tree decomposition. The delay information obtained is then used to select the node pairs for cross link insertion. Our methodology tries to insert cross links where skew can be reduced most effectively. Our method also considers tradeoff between cross link length and skew reduction effect. We compare our result with the most similar work on this problem [1] and a recent work [4] which inserts links between internal nodes of a tree. Experiments show that our method can reduce skew under variation effectively. We achieve 28% clock skew reduction with only 40% link resources.
Qian, Fuqiang.
Thesis (M.Phil.)--Chinese University of Hong Kong, 2012.
Includes bibliographical references (leaves 51-55).
Abstract --- p.i
Acknowledgement --- p.iii
Chapter 1 --- Introduction --- p.1
Chapter 1.1 --- Clock Distribution Network --- p.1
Chapter 1.2 --- Our Contributions --- p.6
Chapter 1.3 --- Organization of the Thesis --- p.8
Chapter 2 --- Literature Review --- p.9
Chapter 2.1 --- Exact Zero Skew --- p.9
Chapter 2.2 --- DME Algorithm --- p.11
Chapter 2.3 --- Combinatorial Algorithms for Fast Clock Mesh Optimization --- p.12
Chapter 2.4 --- MeshWorks: An Efficient Framework for Planning, Synthesis and Optimization of Clock Mesh Networks --- p.14
Chapter 2.5 --- Reducing Clock Skew variability via Cross Links --- p.16
Chapter 2.6 --- Statistical Based Link Insertion for Robust Clock Network Design --- p.18
Chapter 2.7 --- Variation Tolerant Buffered Clock Network Synthesis with Cross Links --- p.20
Chapter 2.8 --- Cross Link Insertion for Improving Tolerance to Variations in Clock Network Synthesis --- p.22
Chapter 3 --- Clock Network Construction with Cross Links --- p.24
Chapter 3.1 --- Signal Delay and Clock Skew in Non-tree Clock Network --- p.24
Chapter 3.1.1 --- Computing Delay in Non-tree Network --- p.25
Chapter 3.1.2 --- Effect of a Cross Link on Clock Skew --- p.27
Chapter 3.2 --- Link Insertion for Non-tree Clock Network --- p.28
Chapter 3.2.1 --- Motivation of Computing Delay for Link Insertion --- p.29
Chapter 3.2.2 --- Overall Flow for Cross Link Insertion --- p.30
Chapter 3.2.3 --- Linear Program for Selecting Node Pairs --- p.31
Chapter 3.2.4 --- Reducing the Number of Optimizations --- p.35
Chapter 3.2.5 --- Experimental Results --- p.37
Chapter 4 --- Buffered Clock Network with Cross Links --- p.41
Chapter 4.1 --- Link Insertion in Buffered Clock Network --- p.41
Chapter 4.1.1 --- Delay Calculation in Buffered Clock Network --- p.42
Chapter 4.1.2 --- Linear Program Formulation for Buffered Clock Network --- p.43
Chapter 4.2 --- Experimental Results and Comparison --- p.44
Chapter 4.3 --- Possible Extensions --- p.46
Chapter 4.3.1 --- Link Insertion at Internal Nodes --- p.46
Chapter 4.3.2 --- Modeling Clock Buffer Delay Variation --- p.47
Chapter 5 --- Conclusion --- p.49
Bibliography --- p.51

碩士
中原大學
資訊工程研究所
99
Power consumption is an important issue in modern high-frequency and low power design. Multi-bit flip-flops are used to reduce the clock system power. The scaling with multiple supply voltage is an effective way to minimize the dynamic power consumption. In this paper, we propose an effective multi-bit flip-flops merging approach to deal with the clock network power minimization problem and an efficient placement method while considering the placement density and timing slack constraint. Moreover, the proposed approach can be applied to both single and multiple supply voltage designs. Our approach is includes three main steps (1) determining the feasible regions, (2) flip-flops selection and grouping, (3) flip-flops placement. In determining the feasible regions step, we find the feasible region of each flip-flop according to the timing slack of each pin. In flip-flops selection and grouping step, proper flip-flops are selected to be merged as a group. In flip-flops placement step, the multi-bit flip-flop will be placed in the appropriate location to reduce the power consumption of clock network. Experimental results show that our proposed approach can reduced the clock power up to 25% for both problems compared with the original design using only 1-bit flip-flop. In addition, for multiple supply voltage designs, the proposed approach can reduce the number of level shifters significantly.

In the sub-65nm VLSI technology, the variation effects like manufacturing variation, power supply noise and temperature variation become very significant. As one of the most vital components in any synchronous VLSI chip, the Clock Distribution Network (CDN) is especially sensitive to these variations. The unwanted clock skews caused by the variation effects consume increasing proportion of the clock cycle, thereby limiting chip performance and yield. Thus, making the clock network variation-tolerant is a key objective in the chip designs of today. In this dissertation, we propose several techniques that can be used to synthesize variation-tolerant clock networks. Our contributions can be broadly classified into following four categories: (i) Efficient algorithms for synthesizing link based non-tree clock networks. (ii) A methodology for synthesizing a balanced, variation tolerant, buffered clock network with cross-links. (iii) A comprehensive framework for planning, synthesis and optimization of clock mesh networks. (iv) A chip-level clock tree synthesis technique to address issues unique to hierarchical System-On-a-Chip (SOC) designs that are becoming more and more frequent today. Depending on the performance requirements and resource constraints of a given chip, the above techniques can be used separately or in combination to synthesize a variation tolerant clock network.
text

碩士
中國科技大學
視覺傳達設計系
104
In 2008, there are only 500 Apps in Apple App Store, but up to 2015, there are more than 1.5 million Apps in it. Averagely, a person owns about 119 Apps. Recognizable App icon design is one of the cognitive factors affecting consumer’s selection, image more recognizable than naming. Thus, in this research, we would like to explore whether App users may classify an unknown App into some sort of category, which may result from color and image stereotype based on previous Appinvolvement. The objects of this research are(1) Investigate the current color design of Social Networking Apps.(2) Investigate the relationship of Gender and Social NetworkingApps icon color stereotype.(3) Investigate the relationship of Gender and Social Networking Apps icon color click intention.(4) Investigate the relationship of Social Networking Apps involvement and the icon color stereotype.(5) Investigate the relationship of image design and Social Networking Apps icon stereotype.(6) Investigate the relationship of image design and Social Networking Apps icon click intention.Nine basic colors and Image Elemennts(Chang, 1992) are adopted to testify in this research. First, a content analysis is used to explore the current trend of icon color and image design for Social Networking Apps. A questionnaire of survey is based on the results of content analysis. 427 samples are collected from website questionnaire. The data is analyzed by Pearson's chi-squared test, Logistic regression and Analysis of Variance,and the results shows:(1) Blue color is mostly used in Community Apps design;Red color is mostly used in Dating Apps design.(2) "Gender" and color stereotype (men like blue, women like red) no association. Just look at "color suitable for Community Apps icon design" has statistical significance. Men are more likely to recognize "Black" and Women are more likely to recognize "Red" and "Purple" as Community Apps icon design. "Gender" and color stereotype (men like blue, women like red) no association. Just look at "more eye-catching" has statistical significance. Men are more likely to recognize "Red" and "Brown" , and Women are more likely to recognize "Purple" and "White" as Community Apps icon design. "Gender" and color stereotype (men like blue, women like red) no association. Just look at "color suitable fordating Apps icon design" has statistical significance. Women are more likely to recognize "Purple" as Dating Apps icon design. (3) "Gender" and "more likely to attract me to read more(Community Apps ) " has statistical significance. Men are more likely to recognize "Black", and Women are more likely to recognize "Purple" and "Gery". (4) The variables of "BeeTalk App (Yellow Design) involvement" and "yellow design icon will attract my attention" have a positive relationship. The variables of "Paktor App (Red Design) involvement" and "Red-designed icon is considered as Dating App icon" have a positive relationship.(5) "Community Apps Image Design" and five questions has statistical significance.The recognition level of Symbols(Dialog Box) is apparently higher than other image design.(6) "Dating Apps Image Design" and five questions has statistical significance.The recognition level of Pictogram(Heart) is apparently higher than other image design.

Packaging is an important element responsible for brand growth and one of the main rea-sons for producers to gain competitive advantages through technological innovation. In this re-gard, the aim of this work is to design a fully autonomous electronic system for a smart bottle packaging, being integrated in a European project named ROLL-OUT. The desired application for the smart bottle is to act as a fill-level sensor system in order to determine the liquid content level that exists inside an opaque bottle, so the consumer can exactly know the remaining quantity of the product inside. An in-house amorphous indium–gallium–zinc oxide thin-film transistor (a-IGZO TFT) model, previously developed, was used for circuit designing purposes. This model was based in an artificial neural network (ANN) equivalent circuit approach. Taking into account that only n-type oxide TFTs were used, plenty of electronic building-blocks have been designed: clock generator, non-overlapping phase generator, a capacitance-to-voltage converter and a comparator. As it was demonstrated by electrical simulations, it has been achieved good functionality for each block, having a final system with a power dissipation of 2.3 mW (VDD=10 V) not considering the clock generator. Four printed circuit boards (PCBs) have been also designed in order to help in the testing phase. Mask layouts were already designed and are currently in fabrication, foreseeing a suc-cessful circuit fabrication, and a major step towards the design and integration of complex trans-ducer systems using oxide TFTs technology.

Minimum cycle mean (MCM) is an important concept in directed graphs. From clock period optimization, timing analysis to layout optimization, minimum cycle mean algorithms have found widespread use in VLSI system design optimization. With transistor size scaling to 10nm and below, complexities and size of the systems have grown rapidly over the last decade. Scalability of the algorithms both in terms of their runtime and memory usage is therefore important.

Among the few classical MCM algorithms, the algorithm by Young, Tarjan, and Orlin (YTO), has been particularly popular. When implemented with a binary heap, the YTO algorithm has the best runtime performance although it has higher asymptotic time complexity than Karp's algorithm. However, as an efficient implementation of YTO relies on data redundancy, its memory usage is higher and could be a prohibitive factor in large size problems. On the other hand, a typical implementation of Karp's algorithm can also be memory hungry. An early termination technique from Hartmann and Orlin (HO) can be directly applied to Karp's algorithm to improve its runtime performance and memory usage. Although not as efficient as YTO in runtime, HO algorithm has much less memory usage than YTO. We propose several improvements to HO algorithm. The proposed algorithm has comparable runtime performance to YTO for circuit graphs and dense random graphs while being better than HO algorithm in memory usage.

Minimum balancing of a directed graph is an application of the minimum cycle mean algorithm. Minimum balance algorithms have been used to optimally distribute slack for mitigating process variation induced timing violation issues in clock network. In a conventional minimum balance algorithm, the principal subroutine is that of finding MCM in a graph. In particular, the minimum balance algorithm iteratively finds the minimum cycle mean and the corresponding minimum-mean cycle, and uses the mean and cycle to update the graph by changing edge weights and reducing the graph size. The iterations terminate when the updated graph is a single node. Studies have shown that the bottleneck of the iterative process is the graph update operation as previous approaches involved updating the entire graph. We propose an improvement to the minimum balance algorithm by performing fewer changes to the edge weights in each iteration, resulting in better efficiency.

We also apply the minimum cycle mean algorithm in latency insensitive system design. Timing violations can occur in high performance communication links in system-on-chips (SoCs) in the late stages of the physical design process. To address the issues, latency insensitive systems (LISs) employ pipelining in the communication channels through insertion of the relay stations. Although the functionality of a LIS is robust with respect to the communication latencies, such insertion can degrade system throughput performance. Earlier studies have shown that the proper sizing of buffer queues after relay station insertion could eliminate such performance loss. However, solving the problem of maximum performance buffer queue sizing requires use of mixed integer linear programming (MILP) of which runtime is not scalable. We formulate the problem as a parameterized graph optimization problem where for every communication channel there is a parameterized edge with buffer counts as the edge weight. We then use minimum cycle mean algorithm to determine from which edges buffers can be removed safely without creating negative cycles. This is done iteratively in the similar style as the minimum balance algorithm. Experimental results suggest that the proposed approach is scalable. Moreover, quality of the solution is observed to be as good as that of the MILP based approach.