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Thematische Bibliographien / Complementary Electronic circuit design

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Auswahl der wissenschaftlichen Literatur zum Thema „Complementary Electronic circuit design“

Autor: Grafiati

Veröffentlicht am 4. Juni 2021

Zuletzt aktualisiert am 11. Februar 2022

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Zeitschriftenartikel zum Thema "Complementary Electronic circuit design"

1

Grout, Ian A., Muhaned Zaidi, Karel L. Sterckx, and Abu Khari Bin A'ain. "RGB LED Driver Circuit Design for an Optical Fiber Sensor System." ECTI Transactions on Computer and Information Technology (ECTI-CIT) 11, no. 2 (2017): 163–77. http://dx.doi.org/10.37936/ecti-cit.2017112.63707.

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In this paper, the design of a programmable mixed-signal electronic circuit to control the light output of a red-green-blue (RGB) light emitting diode (LED) to be used in an optical fiber sensor system is presented and discussed. The LED is to be used as a light transmitter (light source) within the sensor system. The output of each LED color is to be independently controlled using either a d.c. current or a pulse width modulation (PWM) encoded current. The idea for, and architecture of, the mixed-signal electronic circuit design is considered as both a discrete implementation using off-the-sh

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2

Sharma, Vijay Kumar. "Design of Low Leakage PVT Variations Aware CMOS Bootstrapped Driver Circuit." Journal of Circuits, Systems and Computers 26, no. 09 (2017): 1750137. http://dx.doi.org/10.1142/s0218126617501377.

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This paper describes a novel complementary metal oxide semiconductor (CMOS) bootstrapped driver circuit for driving large resistive capacitive (RC) loads. The proposed bootstrapped driver reduces the leakage as well as process, voltage and temperature (PVT) variations from the boosted nodes with higher switching speed. Very large scale integration (VLSI) designers need boosted output for the logic circuits which are operating in ultra-deep submicron regime under widespread use of low voltage. Proposed CMOS bootstrapped driver circuit is easy in design; built with minimum number of transistors

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3

Wang, Songlin, Shuang Feng, Hui Wang, Yu Yao, Jinhua Mao, and Xinquan Lai. "A novel high accuracy bandgap reference voltage source." Circuit World 43, no. 4 (2017): 141–44. http://dx.doi.org/10.1108/cw-04-2017-0019.

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Purpose This paper aims to design a new bandgap reference circuit with complementary metal–oxide–semiconductor (CMOS) technology. Design/methodology/approach Different from the conventional bandgap reference circuit with operational amplifiers, this design directly connects the two bases of the transistors with both the ends of the resistor. The transistor acts as an amplifier to amplify the change of voltage, which is convenient for the feedback regulation of low dropout regulator (LDO) regulator circuit, at last to realize the temperature control. In addition, introducing the depletion-type

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4

Lee, Chau-Han, Shan Zhong, Xiao Lin, J. F. Young, and Y. J. Chen. "Planar lightwave circuit design for programmable complementary spectral keying encoder and decoder." Electronics Letters 35, no. 21 (1999): 1813. http://dx.doi.org/10.1049/el:19991263.

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5

Busaba, Fadi, Parag K. Lala, and Alvernon Walker. "On Self-Checking Design of CMOS Circuits for Multiple Faults." VLSI Design 7, no. 2 (1998): 151–61. http://dx.doi.org/10.1155/1998/37237.

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A technique for designing totally self-checking (TSC) FCMOS (Fully Complementary MOS) designs for multiple faults is presented in this paper. The existing techniques for self checking design consider only single faults, and suffer from high silicon area overhead. The multiple faults considered in this paper are multiple breaks, multiple transistors stuck-offs and multiple transistors stuck-ons. Starting from FCMOS design, small modifications (addition of two-weak transistors) make the original circuit totally self-checking. Experiemntal results show the overhead, delay and power consumption fo

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6

Walker, James Alfred, Richard Sinnott, Gordon Stewart, James A. Hilder, and Andy M. Tyrrell. "Optimizing electronic standard cell libraries for variability tolerance through the nano-CMOS grid." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 368, no. 1925 (2010): 3967–81. http://dx.doi.org/10.1098/rsta.2010.0150.

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The project Meeting the Design Challenges of nano-CMOS Electronics ( http://www.nanocmos.ac.uk ) was funded by the Engineering and Physical Sciences Research Council to tackle the challenges facing the electronics industry caused by the decreasing scale of transistor devices, and the inherent variability that this exposes in devices and in the circuits and systems in which they are used. The project has developed a grid-based solution that supports the electronics design process, incorporating usage of large-scale high-performance computing (HPC) resources, data and metadata management and sup

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Saman, B., R. H. Gudlavalleti, R. Mays, J. Chandy, Evan Heller, and F. Jain. "3-Bit Analog-to-Digital Converter Using Multi-State Spatial Wave-Function Switched FETs." International Journal of High Speed Electronics and Systems 29, no. 01n04 (2020): 2040014. http://dx.doi.org/10.1142/s0129156420400145.

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Multi-valued logic using multi-state spatial wavefunction switched (SWS)-FETs offers overall reduction in size and power as compared to conventional FET based circuits. This paper presents the design of compact 3-bit Analog-to-Digital Converters (ADC) implemented with SWS-FETs. A novel multi-valued Threshold Inverter Quantization (TIQ) based voltage comparator using SWS FET transistors has been proposed. Unlike conventional FETs, SWS-FETs are comprised of two or more vertically stacked coupled quantum well or quantum dot channels, and the spatial location of carriers within these channels is u

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Huang, Chao, and Wan-Jun Yin. "Design of High Performance Low-Noise Amplifier Circuit Based on Complementary Metal Oxide Semiconductor Technology." Journal of Nanoelectronics and Optoelectronics 16, no. 4 (2021): 559–64. http://dx.doi.org/10.1166/jno.2021.2949.

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This paper designs a body-biased (BB) differential cascode low-noise amplifier (LNA) with current bias (CR) and capacitor cross-coupling (CCC) technology that meets the bandwidth requirements of 5 GHz wireless applications. In the design, the CCC technology in the differential cascode topology is used to effectively suppress the common mode noise, thereby improving the noise figure. The series resonant network eliminates parasitic capacitance at the input and output ends, thereby improving the power transmission efficiency. The CR technology formed by the intermediate capacitor shares the DC c

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Kushwah, Preeti, Saurabh Khandelwal, and Shyam Akashe. "Multi-Threshold Voltage CMOS Design for Low-Power Half Adder Circuit." International Journal of Nanoscience 14, no. 05n06 (2015): 1550022. http://dx.doi.org/10.1142/s0219581x15500222.

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The new era of portable electronic devices demands lesser power dissipation for longer battery life and design compactability. Leakage current and leakage power are dominating factors which greatly affect the power consumption in low voltage and low power applications. For many numerical representations of binary numbers, combinational circuits like adder, encoder, multiplexer, etc. are useful circuits for arithmetic operation. A novel high speed and low power half adder cell is introduced here which consists of AND gate and OR gate. This cell shows high speed, lower power consumption than con

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Pal, Shishu, and Ashutosh Nandi. "Design of High Power Supply Rejection Ratio Complementary Metal-Oxide-Semiconductor Bandgap Voltage Reference Using Single Node Approach." Sensor Letters 17, no. 10 (2019): 777–83. http://dx.doi.org/10.1166/sl.2019.4136.

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This paper describes a compact, low voltage and high power supply rejection ratio (PSRR) Bandgap voltage reference circuit by using subthreshold MOSFETs. The proposed reference circuit is implemented using 0.18 μm CMOS technology. The circuit simulation is performed using the Cadence Spectre and Synopsys Hspice. The circuit generates the mean output reference voltage of 164 mV and temperature coefficient of 15.5 ppm/°C when temperature is swept from –40 °C to 120 °C at power supply of 1.2 V. For better PSRR, a feed forward mechanism is used. The proposed design has only single transistor for s

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Dissertationen zum Thema "Complementary Electronic circuit design"

1

Balachandran, Ganesh Kumar. "A switched-current filter in digital-CMOS technology with low charge-injection errors." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/15405.

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2

Wang, Dan. "Design and integration of a single-chip low-power single-conversion CMOS cable TV tuner /." View abstract or full-text, 2005. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202005%20WANG.

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3

Li, Xiaoyong. "Low noise design techniques for radio frequency integrated circuits /." Thesis, Connect to this title online; UW restricted, 2004. http://hdl.handle.net/1773/6013.

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4

Tennakoon, Hiran Kasturiratne. "Efficient and accurate gate sizing with piecewise convex delay models /." Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/5999.

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5

Zhang, Pengbei. "Circuit and system design for fully integrated CMOS direct-conversion multi-band OFDM ultra-wideband receivers." Columbus, Ohio : Ohio State University, 2007. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1172692934.

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6

Bartholomew, David Ray. "Design of a High Speed Mixed Signal CMOS Mutliplying Circuit." Diss., CLICK HERE for online access, 2004. http://contentdm.lib.byu.edu/ETD/image/etd362.pdf.

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7

Killens, Jacob. "Utilizing standard CMOS process floating gate devices for analog design." Master's thesis, Mississippi State : Mississippi State University, 2001. http://library.msstate.edu/etd/show.asp?etd=etd-04092001-110957.

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Neveu, Florian. "Design and implementation of high frequency 3D DC-DC converter." Thesis, Lyon, INSA, 2015. http://www.theses.fr/2015ISAL0133/document.

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L’intégration ultime de convertisseurs à découpage repose sur deux axes de recherche. Le premier axe est de développer les convertisseurs à capacités commutées. Cette approche est compatible avec une intégration totale sur silicium, mais limitée en terme de densité de puissance. Le second axe est l’utilisation de convertisseurs à inductances, qui pâtissent d’imposants composants passifs. Une augmentation de la fréquence permet de réduire les valeurs des composants passifs. Cependant une augmentation de la fréquence implique une augmentation des pertes par commutation, ce qui est contrebalan

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9

Chun, Sungjun. "Methodologies for modeling simultaneous switching noise in multi-layered packages and boards." Diss., Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/15452.

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10

Chen, Chih-Hung. "CMOS RF front-end design of a very narrowband transceiver with 0.18[micrometers]." To access this resource online via ProQuest Dissertations and Theses @ UTEP, 2008. http://0-proquest.umi.com.lib.utep.edu/login?COPT=REJTPTU0YmImSU5UPTAmVkVSPTI=&clientId=2515.

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Bücher zum Thema "Complementary Electronic circuit design"

1

Allen, P. E. CMOS analog circuit design. 2nd ed. Oxford University Press, 2002.

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2

R, Holberg Douglas, ed. CMOS analog circuit design. Holt, Rinehart and Winston, 1987.

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3

Allen, P. E. CMOS analog circuit design. Saunders College Publishing, 1987.

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4

R, Holberg Douglas, ed. CMOS analog circuit design. Oxford University Press Inc., 1987.

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5

CMOS: Mixed signal circuit design. 2nd ed. IEEE Press, 2009.

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6

CMOS: Mixed signal circuit design. Wiley, 2002.

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7

Baker, R. Jacob. CMOS: Mixed signal circuit design. 2nd ed. John Wiley & Sons, 2009.

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8

Baker, R. Jacob. CMOS: Mixed signal circuit design. 2nd ed. IEEE Press, 2009.

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9

Circuit design for CMOS VLSI. Kluwer Academic Publishers, 1992.

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10

Kursun, Volkan. Multi-voltage CMOS Circuit Design. John Wiley & Sons, Ltd., 2006.

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Buchteile zum Thema "Complementary Electronic circuit design"

1

Rülling, Wolfgang. "Circuit Verification." In The Electronic Design Automation Handbook. Springer US, 2003. http://dx.doi.org/10.1007/978-0-387-73543-6_9.

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2

Schott, Christian, Robert Racz, Samuel Huber, Angelo Manco, Markus Gloor, and Nicolas Simonne. "CMOS Single-Chip Electronic Compass with Microcontroller." In Analog Circuit Design. Springer Netherlands, 2008. http://dx.doi.org/10.1007/978-1-4020-8263-4_4.

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3

Albert, Gerhard. "Integrated Circuit Techniques." In The Electronic Design Automation Handbook. Springer US, 2003. http://dx.doi.org/10.1007/978-0-387-73543-6_20.

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4

Kohlhammer, Bernd. "Printed Circuit Board Design." In The Electronic Design Automation Handbook. Springer US, 2003. http://dx.doi.org/10.1007/978-0-387-73543-6_25.

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5

Foitzik, Andreas. "Printed Circuit Board Technologies." In The Electronic Design Automation Handbook. Springer US, 2003. http://dx.doi.org/10.1007/978-0-387-73543-6_24.

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6

Barnes, John R. "Designing Power Supply Circuit." In Robust Electronic Design Reference Book. Springer US, 2004. http://dx.doi.org/10.1007/1-4020-7830-7_24.

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7

Fish, Peter J. "Noise Circuit Analysis." In Electronic Noise and Low Noise Design. Macmillan Education UK, 1993. http://dx.doi.org/10.1007/978-1-349-23060-0_5.

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8

Lu, Wei, Sung-Hyun Jo, Yuchao Yang, et al. "Nanosession: Logic Devices and Circuit Design." In Frontiers in Electronic Materials. Wiley-VCH Verlag GmbH & Co. KGaA, 2013. http://dx.doi.org/10.1002/9783527667703.ch40.

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9

Gift, Stephan J. G., and Brent Maundy. "Semiconductor Diode." In Electronic Circuit Design and Application. Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-46989-4_1.

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Gift, Stephan J. G., and Brent Maundy. "Power Supplies." In Electronic Circuit Design and Application. Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-46989-4_10.

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Konferenzberichte zum Thema "Complementary Electronic circuit design"

1

Milovanovic, Vladimir, and Horst Zimmermann. "Complementary edge alignment and digital output signal speed-up CMOS positive feedback latches." In 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). IEEE, 2012. http://dx.doi.org/10.1109/ddecs.2012.6219088.

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Koyuncuog˘lu, Aziz, Tuba Okutucu, and Haluk Ku¨lah. "A CMOS Compatible Metal-Polymer Microchannel Heat Sink for Monolithic Chip Cooling Applications." In 2010 14th International Heat Transfer Conference. ASMEDC, 2010. http://dx.doi.org/10.1115/ihtc14-23212.

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A novel complementary metal oxide semiconductor (CMOS) compatible microchannel heat sink is designed and fabricated for monolithic liquid cooling of electronic circuits. The microchannels are fabricated with full metal walls between adjacent channels with a polymer top layer for easy sealing and optical visibility of the channels. The use of polymer also provides flexibility in adjusting the width of the channels allowing better management of the pressure drop. The proposed microchannel heat sink requires no design change of the electronic circuitry underneath, hence, can be produced by adding

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3

Bartenstein, Thomas, Bernd Koenemann, Lee Todd, and Lisa Vallerie. "Integrating Logical and Physical Analysis Capabilities for Diagnostics." In ISTFA 2004. ASM International, 2004. http://dx.doi.org/10.31399/asm.cp.istfa2004p0521.

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Abstract This paper describes and shows some anticipated application examples for an integrated logical/physical analysis environment that utilizes the public-domain OpenAccess database as a key infrastructure element. Using an electronic design automation (EDA) database makes it possible to enrich the failure analysis and debug environment with useful EDA-type utilities and applications. The article introduces the industry-standard OpenAccess data base and illustrates how this database can be used for better integration of a more comprehensive postsilicon debug, diagnostics, and characterizat

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4

Hattori, Yukio, Hiroki Sato, Akira Hyogo, and Keitaro Sekine. "A Design Approach for Low Phase Noise 5GHz Complementary Quadrature Oscillator." In 13th IEEE International Conference on Electronics, Circuits and Systems. IEEE, 2006. http://dx.doi.org/10.1109/icecs.2006.379760.

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Carlet, Claude, Abderrahman Daif, Jean-Luc Danger, et al. "Optimized linear complementary codes implementation for hardware trojan prevention." In 2015 European Conference on Circuit Theory and Design (ECCTD). IEEE, 2015. http://dx.doi.org/10.1109/ecctd.2015.7300075.

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6

Tsiolakis, T., N. Konofaos, and G. Ph Alexiou. "A complementary single-electron 4-bit multiplexer." In 2010 2nd Asia Symposium on Quality Electronic Design (ASQED 2010). IEEE, 2010. http://dx.doi.org/10.1109/asqed.2010.5548250.

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7

Ezanuddin, A. A. M., and A. H. Ismail. "Complementary asymmetric split ring as surface wave beam separator." In 2016 3rd International Conference on Electronic Design (ICED). IEEE, 2016. http://dx.doi.org/10.1109/iced.2016.7804612.

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Gang-Neng Sung, Chun-Ying Juan, and Chua-Chin Wang. "A 32-bit carry lookahead adder design using complementary all-N-transistor logic." In 2008 15th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2008). IEEE, 2008. http://dx.doi.org/10.1109/icecs.2008.4674951.

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Matsumoto, Tsutomu, Hidenobu Mimura, and Daisuke Suzuki. "Complementary logics vs masked logics: Which countermeasure is a better selection?" In 2009 European Conference on Circuit Theory and Design (ECCTD 2009). IEEE, 2009. http://dx.doi.org/10.1109/ecctd.2009.5274989.

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Ezanuddin, A. A. M., and A. H. Ismail. "Complementary asymmetric split rings as a surface impedance transmission line." In 2016 3rd International Conference on Electronic Design (ICED). IEEE, 2016. http://dx.doi.org/10.1109/iced.2016.7804613.

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Berichte der Organisationen zum Thema "Complementary Electronic circuit design"

1

Fuqua, Norman B. Introduction to Concurrent Engineering: Electronic Circuit Design and Production Applications. Defense Technical Information Center, 1992. http://dx.doi.org/10.21236/ada278405.

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