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Thematische Bibliographien / Complementary Electronic circuit design / Dissertationen

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Dissertationen zum Thema „Complementary Electronic circuit design“

Autor: Grafiati

Veröffentlicht am 4. Juni 2021

Zuletzt aktualisiert am 11. Februar 2022

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1

Balachandran, Ganesh Kumar. "A switched-current filter in digital-CMOS technology with low charge-injection errors." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/15405.

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2

Wang, Dan. "Design and integration of a single-chip low-power single-conversion CMOS cable TV tuner /." View abstract or full-text, 2005. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202005%20WANG.

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3

Li, Xiaoyong. "Low noise design techniques for radio frequency integrated circuits /." Thesis, Connect to this title online; UW restricted, 2004. http://hdl.handle.net/1773/6013.

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4

Tennakoon, Hiran Kasturiratne. "Efficient and accurate gate sizing with piecewise convex delay models /." Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/5999.

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5

Zhang, Pengbei. "Circuit and system design for fully integrated CMOS direct-conversion multi-band OFDM ultra-wideband receivers." Columbus, Ohio : Ohio State University, 2007. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1172692934.

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6

Bartholomew, David Ray. "Design of a High Speed Mixed Signal CMOS Mutliplying Circuit." Diss., CLICK HERE for online access, 2004. http://contentdm.lib.byu.edu/ETD/image/etd362.pdf.

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7

Killens, Jacob. "Utilizing standard CMOS process floating gate devices for analog design." Master's thesis, Mississippi State : Mississippi State University, 2001. http://library.msstate.edu/etd/show.asp?etd=etd-04092001-110957.

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8

Neveu, Florian. "Design and implementation of high frequency 3D DC-DC converter." Thesis, Lyon, INSA, 2015. http://www.theses.fr/2015ISAL0133/document.

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L’intégration ultime de convertisseurs à découpage repose sur deux axes de recherche. Le premier axe est de développer les convertisseurs à capacités commutées. Cette approche est compatible avec une intégration totale sur silicium, mais limitée en terme de densité de puissance. Le second axe est l’utilisation de convertisseurs à inductances, qui pâtissent d’imposants composants passifs. Une augmentation de la fréquence permet de réduire les valeurs des composants passifs. Cependant une augmentation de la fréquence implique une augmentation des pertes par commutation, ce qui est contrebalan

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9

Chun, Sungjun. "Methodologies for modeling simultaneous switching noise in multi-layered packages and boards." Diss., Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/15452.

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10

Chen, Chih-Hung. "CMOS RF front-end design of a very narrowband transceiver with 0.18[micrometers]." To access this resource online via ProQuest Dissertations and Theses @ UTEP, 2008. http://0-proquest.umi.com.lib.utep.edu/login?COPT=REJTPTU0YmImSU5UPTAmVkVSPTI=&clientId=2515.

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11

Remund, Craig Timothy. "Design of CMOS Four-Quadrant Gilbert Cell Multiplier Circuits in Weak and Moderate Inversion." Diss., CLICK HERE for online access, 2004. http://contentdm.lib.byu.edu/ETD/image/etd611.pdf.

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12

Song, Indal. "Multi-Gbit/s CMOS Transimpedance Amplifier with Integrated Photodetector for Optical Interconnects." Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/4902.

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Trends toward increased integration and miniaturization of optical system components have created pressure to consolidate widely disparate analog and digital functions onto fewer and fewer chips with a goal of eventually built into a single mixed-signal chip. Yet, because of those performance requirements, the frontend circuit has traditionally used III-V compound semiconductor technologies, but the low-level of integration with other digital ICs limits the sustainability of such end products for short-distance applications. On the other hand, their CMOS counter parts, despite having such adva

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13

Ritter, Philipp. "Design and optimization of high speed flash analog-to-digital converters in SiGe BiCMOS technologies." Thesis, Lyon, INSA, 2013. http://www.theses.fr/2013ISAL0052.

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Le Convertisseur Analogique Numérique (CAN) est une brique essentielle de la ré- ception et du traitement des données à très haut débit. L’architecture de type "flash" effectue la quantification en comparant simultanément le signal analogique d’entrée à l’ensemble des références du codeur, ce qui en fait, par construction, l’architecture la plus rapide de CAN. Par le passé, cette architecture a démontré des capacités de codage supérieures à 20GS/s dans les conditions de Nyquist. Cependant, cette capac- ité à travailler à très haute vitesse a donné le jour à des réalisations très consommantes (

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14

Finn, Steven Ernest. "Interface circuit designs for extreme environments using SiGe BiCMOS technology." Thesis, Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/22679.

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SiGe BiCMOS technology has many advantageous properties that, when leveraged, enable circuit design for extreme environments. This work will focus on designs targeted for space system avioinics platforms under the NASA ETDP program. The program specifications include operation under temperatures ranging from -180 C to +125 C and with radiation tolerance up to total ionizing dose of 100 krad with built-in single-event latch-up tolerance. To the author's knowledge, this work presents the first design and measurement of a wide temperature range enabled, radiation tolerant as built, RS-485 wirelin

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15

Groves, Michael Peter. "A soliton circuit design system /." Title page, contents and summary only, 1987. http://web4.library.adelaide.edu.au/theses/09PH/09phg884.pdf.

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16

Venkataraman, Sunitha. "Systematic Analysis of the Small-Signal and Broadband Noise Performance of Highly Scaled Silicon-Based Field-Effect Transistors." Diss., Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/16232.

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The objective of this work is to provide a comprehensive analysis of the small-signal and broadband noise performance of highly scaled silicon-based field-effect transistors (FETs), and develop high-frequency noise models for robust radio frequency (RF) circuit design. An analytical RF noise model is developed and implemented for scaled Si-CMOS devices, using a direct extraction procedure based on the linear two-port noise theory. This research also focuses on investigating the applicability of modern CMOS technologies for extreme environment electronics. A thorough analysis of the DC, small-

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17

Bond, Steven Winfred. "Through-silicon circuit optical communications links." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/15390.

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18

Venjum, Kai André. "Embedded System for Electronic Circuit Education." Thesis, Norwegian University of Science and Technology, Department of Electronics and Telecommunications, 2010. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-10961.

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Embedded systems are ideal as electronic demonstrators because they provides the designer with wide possibilities for optimization through codesign. In many situations, like school visits at the Norwegian University of Science and Technology (NTNU), Forskningstorget and Elektronikk- & Telekommunikasjonsdagen, it is desirable for the Department of Electronics and Telecommunication to both motivate and recruit new students to a future career in electronics. Thus, a demonstrator with an interesting presentation may give students an insight in what is possible when studying electronics at NTNU

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19

Owadally, Muhammud Asaad. "Robust electronic circuit design using evolutionary and Taguchi methods." Master's thesis, University of Cape Town, 1997. http://hdl.handle.net/11427/21761.

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Bibliography: pages 80-81.<br>In engineering, there is a wide range of applications where genetic optimizers are used. Two genetic optimizers used in this thesis namely, Population Based Incremental Learning ( PBIL ) and Cross generational selection Heterogeneous crossover Cataclysmic mutation ( CHC ), are tested on a series of circuit problems to fmd if robust electronic circuits can be built from evolutionary methods. The evolutionary algorithms were used to search the space of discrete component values from a range of manufactured preferred values to obtain robust electronic circuits. Paras

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20

Yan, Rong Shen. "Circuit techniques for CMOS amplifier accuracy and robustness improvement in high-side current sensing Read-out circuit." Thesis, University of Macau, 2017. http://umaclib3.umac.mo/record=b3691122.

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21

Marble, William J. "Design and analysis of charge-transfer amplifiers for low-power analog-to-digital converter applications /." Diss., CLICK HERE for online access, 2004. http://contentdm.lib.byu.edu/ETD/image/etd418.pdf.

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22

Mills, Richard P. III. "Design and optimization of RF test structures for mm-wave circuit design." Thesis, Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/42922.

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23

Zhang, Xibo. "RF integrated circuit design options : from technology to layout /." View Abstract or Full-Text, 2003. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202003%20ZHANG.

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Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2003.<br>Includes bibliographical references (leaves 59-61). Also available in electronic version. Access restricted to campus users.

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24

Lui, Siu-hong. "Analog circuit design by nonconvex polynomial optimization two design examples /." Click to view the E-thesis via HKUTO, 2007. http://sunzi.lib.hku.hk/HKUTO/record/B39557418.

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25

Zhan, Song. "A development gene regulation network model for Electronic Circuit design." Thesis, University of York, 2009. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.516396.

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26

Ghahroodi, Massoud. "Variation and reliability in digital CMOS circuit design." Thesis, University of Southampton, 2014. https://eprints.soton.ac.uk/365136/.

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The silicon chip industry continues to provide devices with feature sizes at Ultra-Deep-Sub-Micron (UDSM) dimensions. This results in higher device density and lower power and cost per function. While this trend is positive, there are a number of negative side effects, including the increased device parameter variation, increased sensitivity to soft errors, and lower device yields. The lifetime of next- generation devices is also decreasing due to lower reliability margins and shorter product lifetimes. This thesis presents an investigation into the challenges of UDSM CMOS circuit design, with

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27

Long, John R. (John Robert) Carleton University Dissertation Engineering Electrical. "High frequency integrated circuit design in BICMOS for monolithic timing recovery." Ottawa, 1992.

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28

Farsaei, Ahmadreza. "On the electronic-photonic integrated circuit design automation : modelling, design, analysis, and simulation." Thesis, University of British Columbia, 2017. http://hdl.handle.net/2429/61272.

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Photonic networks form the backbone of the data communication infrastructure. In particular, in current and future wireless communication systems, photonic networks are becoming increasingly popular for data distribution between the central office and the remote antenna units at base stations. As wireless-photonic systems become increasingly more popular, not only low-cost implementation of such systems is desirable, but also a reliable electronic-photonic design automation (EPDA) framework supporting such complex circuits and systems is crucial. This work investigates the foundation and prese

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29

Lui, Siu-hong, and 呂小康. "Analog circuit design by nonconvex polynomial optimization: two design examples." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2007. http://hub.hku.hk/bib/B39557418.

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30

Ramirez, Ortiz Rolando Carleton University Dissertation Engineering Electronics. "Circuit design rules for mixed static and dynamics CMOS logic circuits." Ottawa, 1999.

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31

Odame, Kofi. "Exploiting device nonlinearity in analog circuit design." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/29751.

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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.<br>Committee Chair: Hasler, Paul; Committee Member: Anderson, David; Committee Member: Butera, Robert; Committee Member: Minch, Bradley; Committee Member: Taylor, David. Part of the SMARTech Electronic Thesis and Dissertation Collection.

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32

Baker, Eric Albert. "The design of a CMOS sensor camera system for a nanosatellite." Thesis, Stellenbosch : University of Stellenbosch, 2006. http://hdl.handle.net/10019/493.

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33

Wang, Yong. "Frequency domain coupled circuit-electromagnetic simulation /." Thesis, Connect to this title online; UW restricted, 2004. http://hdl.handle.net/1773/6071.

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34

McCalib, David Jr. "Design method of a modular electronic printed circuit board testing system." Thesis, Massachusetts Institute of Technology, 2013. http://hdl.handle.net/1721.1/85790.

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Thesis: M. Eng. in Manufacturing, Massachusetts Institute of Technology, Department of Mechanical Engineering, 2013.<br>Cataloged from PDF version of thesis.<br>Includes bibliographical references (pages 52-54).<br>The failure rate of the printed circuit board electronic testing process is higher than acceptable at a Lenze Americas factory. This thesis will understand the root causes of failure, and use system engineering methods to decide what course of action should be taken. A Tradespace analysis is used to help decompose some of the complexity into a visualization that simplifies the decis

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35

Taylor, Katherine P. "Noise models of A/D and D/A converters for determination of fundamental noise limitations." Diss., Georgia Institute of Technology, 1991. http://hdl.handle.net/1853/16910.

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36

Corey, Steven D. "Automatic measurement-based characterization of off-chip interconnect circuitry using lumped elements /." Thesis, Connect to this title online; UW restricted, 1997. http://hdl.handle.net/1773/6008.

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37

Taylor, David. "Design of certain silicon semi-customised structures incorporating self-test." Thesis, University of Huddersfield, 1989. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.329218.

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38

Gope, Dipanjan. "Integral equation based fast electromagnetic solvers for circuit applications /." Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/6116.

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39

Patel, M. V. "An investigation into concurrent processing and its application to electronic circuit design." Thesis, University of Essex, 1985. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.356048.

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40

Seth, Sachin. "Using complementary silicon-germanium transistors for design of high-performance rf front-ends." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/44721.

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The objective of the research presented in this dissertation is to explore the achievable dynamic range limits in high-performance RF front-ends designed using SiGe HBTs, with a focus on complementary (npn + pnp) SiGe technologies. The performance requirements of RF front-ends are high gain, high linearity, low dc power consumption, very low noise figure, and compactness. The research presented in this dissertation shows that all of these requirements can easily be met by using complementary SiGe HBTs. Thus, a strong case is made in favor of using SiGe technologies for designing high dynamic r

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41

Diestelhorst, Ryan M. "Silicon-germanium BiCMOS device and circuit design for extreme environment applications." Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/28180.

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Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.<br>Committee Chair: Cressler, John; Committee Member: Papapolymerou, John; Committee Member: Ralph, Stephen.

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42

Eben-Chaime, Moshe. "The physical design of printed circuit boards : a mathematical programming approach." Diss., Georgia Institute of Technology, 1989. http://hdl.handle.net/1853/25505.

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43

Diestelhorst, Ryan Matthew. "The design of SiGe integrated circuit components for extreme environment systems and sensors." Diss., Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/50262.

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A background investigation of the total-dose radiation tolerance of a third generation complementary SiGe:C BiCMOS technology platform was performed. Tolerance was quantified under proton and X-ray radiation sources for both the npn and pnp HBT, as well as for an operational amplifier built with these devices. Furthermore, a technique known as junction isolation radiation hardening was proposed and tested with the goal of improving the SEE sensitivity of the npn by reducing the charge collected by the subcollector in the event of a direct ion strike. Three independent systems were designed, i

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44

Shina, Sammy G. "A design quality and cost model for printed circuit board assembly /." Thesis, Connect to Dissertations & Theses @ Tufts University, 1998.

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Thesis (Ph.D.)--Tufts University, 1998.<br>Adviser: Anil Saigal. Submitted to the Dept. of Mechanical Engineering. Includes bibliographical references. Access restricted to members of the Tufts University community. Also available via the World Wide Web;

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45

Ozalevli, Erhan. "Exploiting Floating-Gate Transistor Properties in Analog and Mixed-Signal Circuit Design." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/14048.

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With the downscaling trend in CMOS technology, it has been possible to utilize the advantages of high element densities in VLSI circuits and systems. This trend has readily allowed digital circuits to predominate VLSI implementations due to their ease of scaling. However, high element density in integrated circuit technology has also entailed a decrease in the power consumption per functional circuit cell for the use of low-power and reconfigurable systems in portable equipment. Analog circuits have the advantage over digital circuits in designing low-power and compact VLSI circuits for signal

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46

Chen, Ruijun. "Fixturing analysis and synthesis for flexible circuit board assembly." Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/17866.

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47

Chakrapani, Lakshmi Narasimhan. "Probabilistic boolean logic, arithmetic and architectures." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/26706.

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Thesis (Ph.D)--Computing, Georgia Institute of Technology, 2009.<br>Committee Chair: Palem, Krishna V.; Committee Member: Lim, Sung Kyu; Committee Member: Loh, Gabriel H.; Committee Member: Mudge, Trevor; Committee Member: Yalamanchili, Sudhakar. Part of the SMARTech Electronic Thesis and Dissertation Collection.

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48

Lamontagne, Maurice. "Development of a statistical model for NPN bipolar transistor mismatch." Link to electronic thesis, 2007. http://www.wpi.edu/Pubs/ETD/Available/etd-053007-105648/.

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49

Chakraborty, Swagato. "Integral-equation modeling of distributed effects in penetrable objects for micro-electronic applications /." Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/6072.

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50

Serrano, Guillermo J. "High Performance Analog Circuit Design Using Floating-Gate Techniques." Diss., Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/19819.

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The programmability property of floating-gate transistors is exploited in this work to compensate for mismatch and device parameter variations in various high performance analog circuits. A careful look is taken at the characteristics and behavior of floating-gate transistors; issues such as programming, precision, accuracy, and charge retention are addressed. An alternate approach to reduce the offset voltage of the amplifier is presented. The proposed approach uses floating-gate transistors as programmable current sources that provide offset compensation while being a part of the amplifier

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