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Thematische Bibliographien / Complementary Electronic circuit design / Zeitschriftenartikel

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Zeitschriftenartikel zum Thema „Complementary Electronic circuit design“

Autor: Grafiati

Veröffentlicht am 4. Juni 2021

Zuletzt aktualisiert am 11. Februar 2022

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1

Grout, Ian A., Muhaned Zaidi, Karel L. Sterckx, and Abu Khari Bin A'ain. "RGB LED Driver Circuit Design for an Optical Fiber Sensor System." ECTI Transactions on Computer and Information Technology (ECTI-CIT) 11, no. 2 (2017): 163–77. http://dx.doi.org/10.37936/ecti-cit.2017112.63707.

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In this paper, the design of a programmable mixed-signal electronic circuit to control the light output of a red-green-blue (RGB) light emitting diode (LED) to be used in an optical fiber sensor system is presented and discussed. The LED is to be used as a light transmitter (light source) within the sensor system. The output of each LED color is to be independently controlled using either a d.c. current or a pulse width modulation (PWM) encoded current. The idea for, and architecture of, the mixed-signal electronic circuit design is considered as both a discrete implementation using off-the-sh

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Sharma, Vijay Kumar. "Design of Low Leakage PVT Variations Aware CMOS Bootstrapped Driver Circuit." Journal of Circuits, Systems and Computers 26, no. 09 (2017): 1750137. http://dx.doi.org/10.1142/s0218126617501377.

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This paper describes a novel complementary metal oxide semiconductor (CMOS) bootstrapped driver circuit for driving large resistive capacitive (RC) loads. The proposed bootstrapped driver reduces the leakage as well as process, voltage and temperature (PVT) variations from the boosted nodes with higher switching speed. Very large scale integration (VLSI) designers need boosted output for the logic circuits which are operating in ultra-deep submicron regime under widespread use of low voltage. Proposed CMOS bootstrapped driver circuit is easy in design; built with minimum number of transistors

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Wang, Songlin, Shuang Feng, Hui Wang, Yu Yao, Jinhua Mao, and Xinquan Lai. "A novel high accuracy bandgap reference voltage source." Circuit World 43, no. 4 (2017): 141–44. http://dx.doi.org/10.1108/cw-04-2017-0019.

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Purpose This paper aims to design a new bandgap reference circuit with complementary metal–oxide–semiconductor (CMOS) technology. Design/methodology/approach Different from the conventional bandgap reference circuit with operational amplifiers, this design directly connects the two bases of the transistors with both the ends of the resistor. The transistor acts as an amplifier to amplify the change of voltage, which is convenient for the feedback regulation of low dropout regulator (LDO) regulator circuit, at last to realize the temperature control. In addition, introducing the depletion-type

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Lee, Chau-Han, Shan Zhong, Xiao Lin, J. F. Young, and Y. J. Chen. "Planar lightwave circuit design for programmable complementary spectral keying encoder and decoder." Electronics Letters 35, no. 21 (1999): 1813. http://dx.doi.org/10.1049/el:19991263.

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5

Busaba, Fadi, Parag K. Lala, and Alvernon Walker. "On Self-Checking Design of CMOS Circuits for Multiple Faults." VLSI Design 7, no. 2 (1998): 151–61. http://dx.doi.org/10.1155/1998/37237.

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A technique for designing totally self-checking (TSC) FCMOS (Fully Complementary MOS) designs for multiple faults is presented in this paper. The existing techniques for self checking design consider only single faults, and suffer from high silicon area overhead. The multiple faults considered in this paper are multiple breaks, multiple transistors stuck-offs and multiple transistors stuck-ons. Starting from FCMOS design, small modifications (addition of two-weak transistors) make the original circuit totally self-checking. Experiemntal results show the overhead, delay and power consumption fo

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Walker, James Alfred, Richard Sinnott, Gordon Stewart, James A. Hilder, and Andy M. Tyrrell. "Optimizing electronic standard cell libraries for variability tolerance through the nano-CMOS grid." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 368, no. 1925 (2010): 3967–81. http://dx.doi.org/10.1098/rsta.2010.0150.

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The project Meeting the Design Challenges of nano-CMOS Electronics ( http://www.nanocmos.ac.uk ) was funded by the Engineering and Physical Sciences Research Council to tackle the challenges facing the electronics industry caused by the decreasing scale of transistor devices, and the inherent variability that this exposes in devices and in the circuits and systems in which they are used. The project has developed a grid-based solution that supports the electronics design process, incorporating usage of large-scale high-performance computing (HPC) resources, data and metadata management and sup

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Saman, B., R. H. Gudlavalleti, R. Mays, J. Chandy, Evan Heller, and F. Jain. "3-Bit Analog-to-Digital Converter Using Multi-State Spatial Wave-Function Switched FETs." International Journal of High Speed Electronics and Systems 29, no. 01n04 (2020): 2040014. http://dx.doi.org/10.1142/s0129156420400145.

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Multi-valued logic using multi-state spatial wavefunction switched (SWS)-FETs offers overall reduction in size and power as compared to conventional FET based circuits. This paper presents the design of compact 3-bit Analog-to-Digital Converters (ADC) implemented with SWS-FETs. A novel multi-valued Threshold Inverter Quantization (TIQ) based voltage comparator using SWS FET transistors has been proposed. Unlike conventional FETs, SWS-FETs are comprised of two or more vertically stacked coupled quantum well or quantum dot channels, and the spatial location of carriers within these channels is u

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Huang, Chao, and Wan-Jun Yin. "Design of High Performance Low-Noise Amplifier Circuit Based on Complementary Metal Oxide Semiconductor Technology." Journal of Nanoelectronics and Optoelectronics 16, no. 4 (2021): 559–64. http://dx.doi.org/10.1166/jno.2021.2949.

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This paper designs a body-biased (BB) differential cascode low-noise amplifier (LNA) with current bias (CR) and capacitor cross-coupling (CCC) technology that meets the bandwidth requirements of 5 GHz wireless applications. In the design, the CCC technology in the differential cascode topology is used to effectively suppress the common mode noise, thereby improving the noise figure. The series resonant network eliminates parasitic capacitance at the input and output ends, thereby improving the power transmission efficiency. The CR technology formed by the intermediate capacitor shares the DC c

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Kushwah, Preeti, Saurabh Khandelwal, and Shyam Akashe. "Multi-Threshold Voltage CMOS Design for Low-Power Half Adder Circuit." International Journal of Nanoscience 14, no. 05n06 (2015): 1550022. http://dx.doi.org/10.1142/s0219581x15500222.

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The new era of portable electronic devices demands lesser power dissipation for longer battery life and design compactability. Leakage current and leakage power are dominating factors which greatly affect the power consumption in low voltage and low power applications. For many numerical representations of binary numbers, combinational circuits like adder, encoder, multiplexer, etc. are useful circuits for arithmetic operation. A novel high speed and low power half adder cell is introduced here which consists of AND gate and OR gate. This cell shows high speed, lower power consumption than con

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Pal, Shishu, and Ashutosh Nandi. "Design of High Power Supply Rejection Ratio Complementary Metal-Oxide-Semiconductor Bandgap Voltage Reference Using Single Node Approach." Sensor Letters 17, no. 10 (2019): 777–83. http://dx.doi.org/10.1166/sl.2019.4136.

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This paper describes a compact, low voltage and high power supply rejection ratio (PSRR) Bandgap voltage reference circuit by using subthreshold MOSFETs. The proposed reference circuit is implemented using 0.18 μm CMOS technology. The circuit simulation is performed using the Cadence Spectre and Synopsys Hspice. The circuit generates the mean output reference voltage of 164 mV and temperature coefficient of 15.5 ppm/°C when temperature is swept from –40 °C to 120 °C at power supply of 1.2 V. For better PSRR, a feed forward mechanism is used. The proposed design has only single transistor for s

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Lee, Changyeop, Gyuseong Cho, Troy Unruh, Seop Hur, and Inyong Kwon. "Integrated Circuit Design for Radiation-Hardened Charge-Sensitive Amplifier Survived up to 2 Mrad." Sensors 20, no. 10 (2020): 2765. http://dx.doi.org/10.3390/s20102765.

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According to the continuous development of metal-oxide semiconductor (MOS) fabrication technology, transistors have naturally become more radiation-tolerant through steadily decreasing gate-oxide thickness, increasing the tunneling probability between gate-oxide and channel. Unfortunately, despite this radiation-hardened property of developed transistors, the field of nuclear power plants (NPPs) requires even higher radiation hardness levels. Particularly, total ionizing dose (TID) of approximately 1 Mrad could be required for readout circuitry under severe accident conditions with 100 Mrad ar

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Zawawi, Ruhaifi Bin Abdullah, Hojong Choi, and Jungsuk Kim. "High PSRR Wide Supply Range Dual-Voltage Reference Circuit for Bio-Implantable Applications." Electronics 10, no. 16 (2021): 2024. http://dx.doi.org/10.3390/electronics10162024.

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On-chip systems are challenging owing to the limited size of the components, such as the capacitor bank in the rectifier. With a small on-chip capacitor, the output voltage of the rectifier might ring if the circuit experiences significant changes in current. The reference circuit is the first block after the rectifier, and the entire system relies on its robustness. A fully integrated dual-voltage reference circuit for bio-implantable applications is presented. The proposed circuit utilizes nonlinear current compensation techniques that significantly decrease supply variations and reject high

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Asghar, Malik Summair, Saad Arslan, and Hyungwon Kim. "A Low-Power Spiking Neural Network Chip Based on a Compact LIF Neuron and Binary Exponential Charge Injector Synapse Circuits." Sensors 21, no. 13 (2021): 4462. http://dx.doi.org/10.3390/s21134462.

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To realize a large-scale Spiking Neural Network (SNN) on hardware for mobile applications, area and power optimized electronic circuit design is critical. In this work, an area and power optimized hardware implementation of a large-scale SNN for real time IoT applications is presented. The analog Complementary Metal Oxide Semiconductor (CMOS) implementation incorporates neuron and synaptic circuits optimized for area and power consumption. The asynchronous neuronal circuits implemented benefit from higher energy efficiency and higher sensitivity. The proposed synapse circuit based on Binary Ex

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Sofeoul-Al-Mamun, Md, Mohammad Badrul Alam Miah, and Fuyad Al Masud. "A Novel Design and Implementation of 8-3 Encoder Using Quantum-dot Cellular Automata (QCA) Technology." European Scientific Journal, ESJ 13, no. 15 (2017): 254. http://dx.doi.org/10.19044/esj.2017.v13n15p254.

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In recent years Quantum-dot Cellular Automata (QCA) has been considered one of the emerging nano-technology for future generation digital circuits and systems. QCA technology is a promising alternative to Complementary Metal Oxide Semiconductor (CMOS) technology. Thus, QCA offers a novel electronics paradigm for information processing and communication system. It has attractive features such as faster speed, higher scale integration, higher switching frequency, smaller size and low power consumption compared to the transistor based technology. It is projected as a promising nanotechnology for

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Padavala, Akhendra Kumar, Narayana Kiran Akondi, and Bheema Rao Nistala. "High quality factor fractal inductor with complementary split-ring array inclusion." Circuit World 46, no. 3 (2020): 215–19. http://dx.doi.org/10.1108/cw-06-2019-0052.

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Purpose This paper aims to present an efficient method to improve quality factor of printed fractal inductors based on electromagnetic band-gap (EBG) surface. Design/methodology/approach Hilbert fractal inductor is designed and simulated using high-frequency structural simulator. To improve the quality factor, an EBG surface underneath the inductor is incorporated without any degradation in inductance value. Findings The proposed inductor and Q factor are measured based on well-known three-dimensional simulator, and the results are compared experimentally. Practical implications The proposed m

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Avci, M., and T. Yildirim. "General design method for complementary pass transistor logic circuits." Electronics Letters 39, no. 1 (2003): 46. http://dx.doi.org/10.1049/el:20030102.

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Huang, Tsung-Ching, Ting Lei, Leilai Shao, et al. "Process Design Kit and Design Automation for Flexible Hybrid Electronics." Journal of Microelectronics and Electronic Packaging 16, no. 3 (2019): 117–23. http://dx.doi.org/10.4071/imaps.925849.

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Abstract High-performance low-cost flexible hybrid electronics (FHE) are desirable for applications such as internet of things and wearable electronics. Carbon nanotube (CNT) thin-film transistor (TFT) is a promising candidate for high-performance FHE because of its high carrier mobility, superior mechanical flexibility, and material compatibility with low-cost printing and solution processes. Flexible sensors and peripheral CNT-TFT circuits, such as decoders, drivers, and sense amplifiers, can be printed and hybrid-integrated with thinned (&lt;50 μm) silicon chips on soft, thin, and flexi

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D., Vaithiyanathan, Megha Singh Kurmi, Alok Kumar Mishra, and Britto Pari J. "Performance analysis of multi-scaling voltage level shifter for low-power applications." World Journal of Engineering 17, no. 6 (2020): 803–9. http://dx.doi.org/10.1108/wje-02-2020-0043.

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Purpose In complementary metal-oxide-semiconductor (CMOS) logic circuits, there is a direct square proportion of supply voltage on dynamic power. If the supply voltage is high, then more amount of energy will be consumed. Therefore, if a low voltage supply is used, then dynamic power will also be reduced. In a mixed signal circuit, there can be a situation when lower voltage circuitry has to drive large voltage circuitry. In such a case, P-type metal-oxide-semiconductor of high-voltage circuitry may not be switched off completely by applying a low voltage as input. Therefore, there is a need f

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Toledo, Pedro, Hamilton Klimach, David Cordova, Sergio Bampi, and Eric Fabris. "MOSFET ZTC Condition Analysis for a Self-biased Current Reference Design." Journal of Integrated Circuits and Systems 10, no. 2 (2015): 103–12. http://dx.doi.org/10.29292/jics.v10i2.411.

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In this paper a self-biased current reference based on Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) Zero Temperature Coefficient (ZTC) condition is proposed. It can be implemented in any Complementary Metal-Oxide-Semiconductor (CMOS) fabrication process and provides another alternative to design current references. In order to support the circuit design, ZTC condition is analyzed using a MOSFET model that is continuous from weak to strong inversion, showing that this condition always occurs from moderate to strong inversion in any CMOS process. The proposed topology was designed

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Wei, Zhaopeng, Gilles Jacquemod, Yves Leduc, Emeric de Foucauld, Jerome Prouvee, and Benjamin Blampey. "Reducing the Short Channel Effect of Transistors and Reducing the Size of Analog Circuits." Active and Passive Electronic Components 2019 (July 4, 2019): 1–9. http://dx.doi.org/10.1155/2019/4578501.

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Analog integrated circuits never follow the Moore’s Law. This is particularly right for passive component. Due to the Short Channel Effect, we have to implement longer transistor, especially for analog cell. In this paper, we propose a new topology using some advantages of the FDSOI (Fully Depleted Silicon on Insulator) technology in order to reduce the size of analog cells. First, a current mirror was chosen to illustrate and validate a new design. Measured currents, with 35nm transistor length, have validated our new cross-coupled back-gate topology. Then, a VCRO (Voltage Controlled Ring Osc

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HUNG, YU-CHERNG. "COMPLEMENTARY AND DOUBLE-EDGE BASED: A 5-BIT CMOS DIGITAL PULSE-WIDTH MODULATION (PWM) DESIGN WITH MULTIPLE OUTPUTS FOR LED DIMMING APPLICATION." Journal of Circuits, Systems and Computers 23, no. 02 (2014): 1450030. http://dx.doi.org/10.1142/s0218126614500303.

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In this paper, a compact high-precision digital pulse-width modulation (DPWM) CMOS circuit is proposed. The circuit, with multiple output capability, allows brightness control of red, green, and blue (RGB) light emitting diode (LED) lighting. The PWM technique is used for LED dimming control to avoid the problem of color shifting. In this design, complementary concepts and hardware sharing are utilized to achieve a compact architecture and small chip area. A double-edge triggered technique is adopted to enhance the capability of high-speed operation. An experimental chip has been realized by u

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Krushna Kanth, Varikuntla, and Singaravelu Raghavan. "Design and optimization of complementary frequency selective surface using equivalent circuit model for wideband EMI shielding." Journal of Electromagnetic Waves and Applications 34, no. 1 (2019): 51–69. http://dx.doi.org/10.1080/09205071.2019.1688691.

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Holmes, Jim, A. Matthew Francis, Ian Getreu, Matthew Barlow, Affan Abbasi, and H. Alan Mantooth. "Extended High-Temperature Operation of Silicon Carbide CMOS Circuits for Venus Surface Application." Journal of Microelectronics and Electronic Packaging 13, no. 4 (2016): 143–54. http://dx.doi.org/10.4071/imaps.527.

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In the last decade, significant effort has been expended toward the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field-effect transistors and metal-oxide-semiconductor (MOS) field-effect transistors have been pursued and demonstrated. More recently, advances in low-power complementary MOS (CMOS) devices have enabled the development of highly integrated digital, analog, and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) of several building block circu

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Sheng, Duo, Wei-Yen Chen, Hao-Ting Huang, and Li Tai. "Digitally Controlled Oscillator with High Timing Resolution and Low Complexity for Clock Generation." Sensors 21, no. 4 (2021): 1377. http://dx.doi.org/10.3390/s21041377.

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This paper presents a digitally controlled oscillator (DCO) with a low-complexity circuit structure that combines multiple delay circuits to achieve a high timing resolution and wide output frequency range simultaneously while also significantly reducing the overall power consumption. A 0.18 µm complementary metal–oxide–semiconductor standard process was used for the design, and measurements showed that the chip had a minimum controllable timing resolution of 4.81 ps and power consumption of 142 µW with an output signal of 364 MHz. When compared with other designs using advanced processes, the

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Li, Zhenghao, Xing Zhao, Shuangxia Niu, and W. N. Fu. "Analysis and Design of a New Relieving-DC-Saturation Transverse-Flux Tubular Motor With Complementary Magnetic Circuit." IEEE Transactions on Magnetics 57, no. 6 (2021): 1–5. http://dx.doi.org/10.1109/tmag.2021.3063773.

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Shen, ShengYu, Ying Qin, KeFei Wang, LiQuan Xiao, JianMin Zhang, and SiKun Li. "Synthesizing Complementary Circuits Automatically." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 29, no. 8 (2010): 1191–202. http://dx.doi.org/10.1109/tcad.2010.2049152.

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Ben Issa, Dalenda, and Mounir Samet. "Design and Optimization of Dual-Band Energy-Efficient OOK UWB Transmitter Via PSO Algorithm." Journal of Circuits, Systems and Computers 29, no. 11 (2020): 2030009. http://dx.doi.org/10.1142/s0218126620300093.

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A CMOS ON–OFF-keying 3–10.6-GHz transmitter with low power consumption and low complexity used to Impulse Radio Ultra-Wide Band (IR-UWB) communication system is presented in this work. This architecture is designed and optimized via particle swarm optimization (PSO) algorithm. The IR-UWB transmitter is adapted to generate a high bandwidth frequency and it has a band switching capability. It consists of a switching inductance–capacitance voltage-controlled oscillator (LC_VCO), a pulse generator circuit, an injection-locked frequency divider (ILFD) circuit, a buffer and an antenna. The VCO is sw

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Singh, Rupali, and Devendra Kumar Sharma. "Design of efficient multilayer RAM cell in QCA framework." Circuit World 47, no. 1 (2020): 31–41. http://dx.doi.org/10.1108/cw-10-2019-0138.

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Purpose Quantum-dot cellular automata (QCA) is a promising technology, which seems to be the prospective substitute for complementary metal-oxide semiconductor (CMOS). It is a high speed, high density and low power paradigm producing efficient circuits. These days, most of the smart devices used for computing, make use of random access memory (RAM). To enhance the performance of a RAM cell, researchers are putting effort to minimize its area and access time. Multilayer structures in QCA framework are area efficient, fast and immune to the random interference. Unlike CMOS, QCA multilayer archit

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John, Vimukth, Shylu Sam, S. Radha, P. Sam Paul, and Joel Samuel. "Design of a power-efficient Kogge–Stone adder by exploring new OR gate in 45nm CMOS process." Circuit World 46, no. 4 (2020): 257–69. http://dx.doi.org/10.1108/cw-12-2018-0104.

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Purpose The purpose of this work is to reduce the power consumption of KSA and to improve the PDP for data path applications. In digital Very Large – Scale Integration systems, the addition of two numbers is one of the essential functions. This arithmetic function is used in the modern digital signal processors and microprocessors. The operating speed of these processors depends on the computation of the arithmetic function. The speed computation block for most of the datapath elements was adders. In this paper, the Kogge–Stone adder (KSA) is designed using XOR, AND and proposed OR gates. The

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Ramanujam, Parthasarathy, P. G. Ramesh Venkatesan, Chandrasekar Arumugam, and Manimaran Ponusamy. "Design of Compact Highpass Filter for 5G mm-wave Applications Using Complementary Split Ring Resonator." Frequenz 74, no. 5-6 (2020): 177–81. http://dx.doi.org/10.1515/freq-2019-0194.

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AbstractThis article presents a design of highpass filter (HPF) for millimeter-wave (mm-wave) applications using a square complementary split-ring resonator (SCSRR). A miniaturized size HPF filter is obtained by overlapping the Right-Hand (RH) and Left-Hand material. The arrangement of inter-digital parallel coupled capacitor and SCSRR offers low insertion loss, high selectivity with a sharp roll-off factor over a wide bandwidth of 15.9 GHz (from 34.1 to 50 GHz). Generally, SCSRR offers narrow passband/stopband however this prototype has a passband over a wide range of frequency. The proposed

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Li, Di, Chunlong Fei, Qidong Zhang, Yani Li, Yintang Yang, and Qifa Zhou. "Ultrahigh Frequency Ultrasonic Transducers Design with Low Noise Amplifier Integrated Circuit." Micromachines 9, no. 10 (2018): 515. http://dx.doi.org/10.3390/mi9100515.

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This paper describes the design of an ultrahigh frequency ultrasound system combined with tightly focused 500 MHz ultrasonic transducers and high frequency wideband low noise amplifier (LNA) integrated circuit (IC) model design. The ultrasonic transducers are designed using Aluminum nitride (AlN) piezoelectric thin film as the piezoelectric element and using silicon lens for focusing. The fabrication and characterization of silicon lens was presented in detail. Finite element simulation was used for transducer design and evaluation. A custom designed LNA circuit is presented for amplifying the

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Sanyal, Rajarshi, Partha Pratim Sarkar, and Santosh Kumar Chowdhury. "Quasi-self-complementary ultra-wideband antenna with band rejection characteristics." International Journal of Microwave and Wireless Technologies 10, no. 3 (2018): 336–44. http://dx.doi.org/10.1017/s1759078717001106.

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This article presents a compact novel quasi-self-complementary semi-octagonal-shaped antenna for ultra-wideband (UWB) application. The proposed novel structure is fed by a microstrip line where different rectangular truncation is etched to the ground plane as an impedance matching element, which results for much wider impedance bandwidth (VSWR<2) from 2.9 to 20 GHz. In order to obtain band-notched characteristics at 5.5 GHz, an open-ended, quarter wavelength, spiral-shaped stub is introduced in the vicinity of the truncated part of the ground plane. An equivalent circuit model is adopted to

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Jérôme, Folla Kamdem, Wembe Tafo Evariste, Essimbi Zobo Bernard, et al. "An 8.72 µW Low-Noise and Wide Bandwidth FEE Design for High-Throughput Pixel-Strip (PS) Sensors." Sensors 21, no. 5 (2021): 1760. http://dx.doi.org/10.3390/s21051760.

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The front-end electronics (FEE) of the Compact Muon Solenoid (CMS) is needed very low power consumption and higher readout bandwidth to match the low power requirement of its Short Strip application-specific integrated circuits (ASIC) (SSA) and to handle a large number of pileup events in the High-Luminosity Large Hadron Collider (LHC). A low-noise, wide bandwidth, and ultra-low power FEE for the pixel-strip sensor of the CMS has been designed and simulated in a 0.35 µm Complementary Metal Oxide Semiconductor (CMOS) process. The design comprises a Charge Sensitive Amplifier (CSA) and a fast Ca

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Reis, Dayane Alfenas, and Frank Sill Torres. "A Defects Simulator for Robustness Analysis of QCA Circuits." Journal of Integrated Circuits and Systems 11, no. 2 (2016): 86–96. http://dx.doi.org/10.29292/jics.v11i2.433.

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Although QCA (Quantum-dot Cellular Automata) is a promising nanotechnology to replace CMOS (Complementary Metal-Oxide-Semiconductor), it has several known reliability problems. Consequently, the design of robust QCA structures is a mandatory step towards the consolidation of this new technology. This paper presents a novel methodology for error analysis of QCA structures based on deterministic and random insertion of possible defects to either the cells and to the phase shifts of the clocking circuit. Further features presented are an evaluation of structures robustness and identification of t

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Rathore, Pradeep Kumar, Brishbhan Singh Panwar, and Jamil Akhtar. "A novel CMOS-MEMS integrated pressure sensing structure based on current mirror sensing technique." Microelectronics International 32, no. 2 (2015): 81–95. http://dx.doi.org/10.1108/mi-11-2014-0048.

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Purpose – The present paper aims to propose a basic current mirror-sensing circuit as an alternative to the traditional Wheatstone bridge circuit for the design and development of high-sensitivity complementary metal oxide semiconductor (CMOS)–microelectromechanical systems (MEMS)-integrated pressure sensors. Design/methodology/approach – This paper investigates a novel current mirror-sensing-based CMOS–MEMS-integrated pressure-sensing structure based on the piezoresistive effect in metal oxide field effect transistor (MOSFET). A resistive loaded n-channel MOSFET-based current mirror pressure-

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Forouhi, Saghi, Rasoul Dehghani, and Ebrahim Ghafar-Zadeh. "Toward High Throughput Core-CBCM CMOS Capacitive Sensors for Life Science Applications: A Novel Current-Mode for High Dynamic Range Circuitry." Sensors 18, no. 10 (2018): 3370. http://dx.doi.org/10.3390/s18103370.

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This paper proposes a novel charge-based Complementary Metal Oxide Semiconductor (CMOS) capacitive sensor for life science applications. Charge-based capacitance measurement (CBCM) has significantly attracted the attention of researchers for the design and implementation of high-precision CMOS capacitive biosensors. A conventional core-CBCM capacitive sensor consists of a capacitance-to-voltage converter (CVC), followed by a voltage-to-digital converter. In spite of their high accuracy and low complexity, their input dynamic range (IDR) limits the advantages of core-CBCM capacitive sensors for

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Xu, Yao, Ashok Srivastava, and Ashwani K. Sharma. "Emerging Carbon Nanotube Electronic Circuits, Modeling, and Performance." VLSI Design 2010 (February 17, 2010): 1–8. http://dx.doi.org/10.1155/2010/864165.

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Current transport and dynamic models of carbon nanotube field-effect transistors are presented. A model of single-walled carbon nanotube as interconnect is also presented and extended in modeling of single-walled carbon nanotube bundles. These models are applied in studying the performances of circuits such as the complementary carbon nanotube inverter pair and carbon nanotube as interconnect. Cadence/Spectre simulations show that carbon nanotube field-effect transistor circuits can operate at upper GHz frequencies. Carbon nanotube interconnects give smaller delay than copper interconnects use

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Rahman, Labonnah Farzana, Mohammad Marufuzzaman, Lubna Alam, and Mazlin Bin Mokhtar. "Design Topologies of a CMOS Charge Pump Circuit for Low Power Applications." Electronics 10, no. 6 (2021): 676. http://dx.doi.org/10.3390/electronics10060676.

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Applications such as non-volatile memories (NVM), radio frequency identification (RFID), high voltage generators, switched capacitor circuits, operational amplifiers, voltage regulators, and DC–DC converters employ charge pump (CP) circuits as they can generate a higher output voltage from the very low supply voltage. Besides, continuous power supply reduction, low implementation cost, and high efficiency can be managed using CP circuits in low-power applications in the complementary metal-oxide-semiconductor (CMOS) process. This study aims to figure out the most widely used CP design topologi

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Li, Chuangze, Benguang Han, Jie He, Zhongjie Guo, and Longsheng Wu. "A Highly Linear CMOS Image Sensor Design Based on an Adaptive Nonlinear Ramp Generator and Fully Differential Pipeline Sampling Quantization with a Double Auto-Zeroing Technique." Sensors 20, no. 4 (2020): 1046. http://dx.doi.org/10.3390/s20041046.

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For a complementary metal-oxide-semiconductor image sensor with highly linear, low noise and high frame rate, the nonlinear correction and frame rate improvement techniques are becoming very important. The in-pixel source follower transistor and the integration capacitor on the floating diffusion node cause linearity degradation. In order to address this problem, this paper proposes an adaptive nonlinear ramp generator circuit based on dummy pixels used in single-slope analog-to-digital converter topology for a complementary metal-oxide-semiconductor (CMOS) image sensor. In the proposed approa

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Shaik, Sadulla. "Device-Circuit Interaction and Performance Benchmarking of Tunnel Transistor-Based Ex-OR Gates for Energy Efficient Computing." Journal of Circuits, Systems and Computers 29, no. 14 (2020): 2050235. http://dx.doi.org/10.1142/s0218126620502357.

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This paper explores the design and analysis of 20[Formula: see text]nm tunnel transistor-based Exclusive-OR (Ex-OR) gates and half-adder cells with circuit interaction (co-design) approach for energy efficient and reliable computing architectures at scaled supply voltages (50–300[Formula: see text]mV). TFETs have attracted much attention recently for energy efficient system designs. The circuit interaction is made possible for designing more consistent functional architectures at the minimum power supply of 50–300[Formula: see text]mV. Using this technique, the core computational blocks of bas

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Choi, Jaihyuk, Sungjae Lee, Youngdoo Son, and Soo Youn Kim. "Design of an Always-On Image Sensor Using an Analog Lightweight Convolutional Neural Network." Sensors 20, no. 11 (2020): 3101. http://dx.doi.org/10.3390/s20113101.

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This paper presents an always-on Complementary Metal Oxide Semiconductor (CMOS) image sensor (CIS) using an analog convolutional neural network for image classification in mobile applications. To reduce the power consumption as well as the overall processing time, we propose analog convolution circuits for computing convolution, max-pooling, and correlated double sampling operations without operational transconductance amplifiers. In addition, we used the voltage-mode MAX circuit for max pooling in the analog domain. After the analog convolution processing, the image data were reduced by 99.58

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Lin, Rong. "A Regularly Structured Parallel Multiplier with Low-power Non-binary-logic Counter Circuits." VLSI Design 12, no. 3 (2001): 377–90. http://dx.doi.org/10.1155/2001/97598.

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A highly regular parallel multiplier architecture along with the novel low-power, high-performance CMOS implementation circuits is presented. The superiority is achieved through utilizing a unique scheme for recursive decomposition of partial product matrices and a recently proposed non-binary arithmetic logic as well as the complementary shift switch logic circuits.The proposed 64×64-b parallel multiplier possesses the following distinct features: (1) generating 64 8×8-b partial product matrices instead of a single large one; (2) comprising only four stages of bit reductions: first, by 8×8-b

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Sandhu, Amanpreet, and Sheifali Gupta. "An Area and Energy Efficient RAM Cell Design in Quantum Dot Cellular Automata." Journal of Computational and Theoretical Nanoscience 16, no. 10 (2019): 4179–87. http://dx.doi.org/10.1166/jctn.2019.8499.

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The Conventional Complementary Metal oxide semiconductor (CMOS) technology has been revolutionized from the past few decades. However, the CMOS circuit faces serious constraints like short channel effects, quantum effects, doping fluctuations at the nanoscale which limits them to further scaling down at nano meter range. Among various existing nanotechnologies, Quantum dot Cellular Automata (QCA) provides new solution at nanocircuit design. The technical advancement of the paper lies in designing a high performance RAM cell with less QCA cells, less occupational area and lower power dissipatio

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Chauhan, Manorama, Ravindra Singh Kushwah, Pavan Shrivastava, and Shyam Akashe. "Analysis and Simulation of a Low-Leakage Analog Single Gate and FinFET Circuits." International Journal of Nanoscience 13, no. 02 (2014): 1450012. http://dx.doi.org/10.1142/s0219581x14500124.

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In the world of Integrated Circuits, complementary metal–oxide–semiconductor (CMOS) has lost its ability during scaling beyond 50 nm. Scaling causes severe short channel effects (SCEs) which are difficult to suppress. FinFET devices undertake to replace usual Metal Oxide Semiconductor Field Effect Transistor (MOSFETs) because of their better ability in controlling leakage and diminishing SCEs while delivering a strong drive current. In this paper, we present a relative examination of FinFET with the double gate MOSFET (DGMOSFET) and conventional bulk Si single gate MOSFET (SGMOSFET) by using C

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Mouhouche, F., A. Azrar, M. Dehmas, and K. Djafri. "Design a Compact UWB Monopole Antenna with Triple Band-Notched Characteristics Using EBG Structures." Frequenz 72, no. 11-12 (2018): 479–87. http://dx.doi.org/10.1515/freq-2018-0069.

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Abstract In this paper, a compact ultra-wideband (UWB) monopole antenna with triple band-notched characteristics is presented. These triple band rejections are produced by inserting the Complementary Co-directional Split-Ring Resonator (CC.SRR) on the radiating element for WiMAX/WLAN (3.4–3.95 GHz/5.35–5.9 GHz) and Electromagnetic Band Gap (EBG) structure in the vicinity of transmission line for X-band satellite communications (6.7–7.7 GHz). The proposed antenna with a total size of 18×20.9×1.63 mm3 has been constructed and tested. An equivalent RLC circuit model is proposed and investigated.

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Dendouga, Abdelghani, Slimane Oussalah, Damien Thienpont, and Abdenour Lounis. "Multiobjective Genetic Algorithms Program for the Optimization of an OTA for Front-End Electronics." Advances in Electrical Engineering 2014 (August 13, 2014): 1–5. http://dx.doi.org/10.1155/2014/374741.

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The design of an interface to a specific sensor induces costs and design time mainly related to the analog part. So to reduce these costs, it should have been standardized like digital electronics. The aim of the present work is the elaboration of a method based on multiobjectives genetic algorithms (MOGAs) to allow automated synthesis of analog and mixed systems. This proposed methodology is used to find the optimal dimensional transistor parameters (length and width) in order to obtain operational amplifier performances for analog and mixed CMOS-(complementary metal oxide semiconductor-) bas

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Kocanda, Piotr, and Andrzej Kos. "Energy losses and DVFS effectiveness vs technology scaling." Microelectronics International 32, no. 3 (2015): 158–63. http://dx.doi.org/10.1108/mi-01-2015-0008.

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Purpose – This article aims to present complete analysis of energy losses in complementary metal-oxide semiconductor (CMOS) circuits and the effectiveness of dynamic voltage and frequency scaling (DVFS) as a method of energy conservation in CMOS circuits in variety of technologies. Energy efficiency in CMOS devices is an issue of highest importance with still continuing technology scaling. There are powerful tools for energy conservation in form of dynamic voltage scaling (DVS) and dynamic frequency scaling (DFS). Design/methodology/approach – Using analytical equations and Spice models of var

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Tankwal, Piyush, Vikas Nehra, Sanjay Prajapati, and Brajesh Kumar Kaushik. "Performance analysis of differential spin hall effect (DSHE)-MRAM-based logic gates." Circuit World 45, no. 4 (2019): 300–310. http://dx.doi.org/10.1108/cw-04-2019-0036.

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Purpose The purpose of this paper is to analyze and compare the characteristics of hybrid conventional complementary metal oxide semiconductor/magnetic tunnel junction (CMOS/MTJ) logic gates based on spin transfer torque (STT) and differential spin Hall effect (DSHE) magnetic random access memory (MRAM). Design/methodology/approach Spintronics technology can be used as an alternative to CMOS technology as it is having comparatively low power dissipation, non-volatility, high density and high endurance. MTJ is the basic spin based device that stores data in form of electron spin instead of char

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Sharma, Anjali, Harsh Sohal, and Harsimran Jit Kaur. "Sleepy CMOS-Sleepy Stack (SC-SS): A Novel High Speed, Area and Power Efficient Technique for VLSI Circuit Design." Journal of Circuits, Systems and Computers 28, no. 12 (2019): 1950197. http://dx.doi.org/10.1142/s0218126619501974.

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This paper presents a novel ultra-low-power Sleepy CMOS-Sleepy Stack (SC-SS) technique for nano scale VLSI technologies. Eight prior techniques are taken for comparison with proposed technique on 65[Formula: see text]nm technology. All the techniques are applied on four benchmark circuits: XOR gate, 1-bit adder, 1-bit comparator and 4-bit up-down counter for measurement of area consumption and total power dissipation. The proposed SC-SS technique achieved very high power efficiency as compared to Complementary CMOS technique (CCT), Dual sleep Technique (DST), Forced stack technique (FST), Slee

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Mladenov, Valeri. "A Unified and Open LTSPICE Memristor Model Library." Electronics 10, no. 13 (2021): 1594. http://dx.doi.org/10.3390/electronics10131594.

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In this paper, a unified and open linear technology simulation program with integrated circuit emphasis (LTSPICE) memristor library is proposed. It is suitable for the analysis, design, and comparison of the basic memristors and memristor-based circuits. The library could be freely used and expanded with new LTSPICE memristor models. The main existing standard memristor models and several enhanced and modified models based on transition metal oxides such as titanium dioxide, hafnium dioxide, and tantalum oxide are included in the library. LTSPICE is one of the best software for analysis and de

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