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1
Sharma, Akshay. "Place and route techniques for FPGA architecture advancement /." Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/6108.
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2
Baweja, Gunjeetsingh. "Gate level coverage of a behavioral test generator." Thesis, This resource online, 1993. http://scholar.lib.vt.edu/theses/available/etd-11102009-020104/.
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3
Tan, Zhou. "Design of a Reconfigurable Pulsed Quad-Cell for Cellular-Automata-Based Conformal Computing." Thesis, North Dakota State University, 2011. https://hdl.handle.net/10365/29176.
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This paper presents the design of a reconfigurable asynchronous unit, called the pulsed quad-cell (PQ-cell), for conformal computing. The conformal computing vision is to create computational materials that can conform to the physical and computational needs of an application. PQ-cells, like cellular automata, are assembled into arrays with nearest neighbor communication and are capable of general computation. They operate asynchronously to minimize power consumption and to allow sealing without the limitations imposed by a global clock. Cell operations are stimulated by pulses which use two wires to encode a data bit. Cells are individually reconfirgurable to perform logic, move and store information, and coordinate parallel activity. The PQ-cell design targets a 0.25 ?m CMOS technology. Simulation results show that a PQ-cell, when pulsed at 1.3 GHz, consumes 16.9 pJ per operation. Examples of self-timed multi-cell structures include a 98 MHz ring oscillator and a 385 MHz pipeline.
4
Hu, Jhy-Fang 1961. "AUTOMATIC HARDWARE COMPILER FOR THE CMOS GATE ARRAY." Thesis, The University of Arizona, 1986. http://hdl.handle.net/10150/276948.
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5
Balog, Michael Rosen Warren A. "The automated compilation of comprehensive hardware design search spaces of algorithmic-based implementations for FPGA design exploration /." Philadelphia, Pa. : Drexel University, 2007. http://hdl.handle.net/1860/1770.
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6
Hall, Tyson Stuart. "Field-Programmable Analog Arrays: A Floating-Gate Approach." Diss., Available online, Georgia Institute of Technology, 2004:, 2004. http://etd.gatech.edu/theses/available/etd-07122004-124607/unrestricted/hall%5Ftyson%5Fs%5F200407%5Fphd.pdf.
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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005. Directed by David Anderson.<br>Prvulovic, Milos, Committee Member ; Citrin, David, Committee Member ; Lanterman, Aaron, Committee Member ; Yalamanchili, Sudhakar, Committee Member ; Hasler, Paul, Committee Member ; Anderson, David, Committee Chair. Includes bibliographical references.
7
Qi, Wen-jie. "Study on high-k dielectrics as alternative gate insulators for 0.1[mu] and beyond ULSI applications /." Digital version accessible at:, 2000. http://wwwlib.umi.com/cr/utexas/main.
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8
Mao, Yu-lung. "Novel high-K gate dielectric engineering and thermal stability of critical interface /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.
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9
Lee, Jian-hung. "Strontium titanate thin films for ULSI memory and gate dielectric applications /." Digital version accessible at:, 2000. http://wwwlib.umi.com/cr/utexas/main.
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10
Kucic, Matthew R. "Analog programmable filters using floating-gate arrays." Thesis, Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/13755.
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11
Lee, Byoung Hun. "Technology development and process integration of alternative gate dielectric material : hafnium oxide /." Full text (PDF) from UMI/Dissertation Abstracts International, 2000. http://wwwlib.umi.com/cr/utexas/fullcit?p3004316.
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12
Luo, Tien-ying. "Electrical and physical analysis of ultra-thin in-situ steam generated (ISSG) SiO₂ and nitride/oxide stacks for ULSI application /." Digital version accessible at:, 2000. http://wwwlib.umi.com/cr/utexas/main.
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13
Yin, Chunshan. "Source/drain and gate design of advanced MOSFET devices /." View abstract or full-text, 2005. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202005%20YIN.
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14
Zhuo, Yue. "Timing and Congestion Driven Algorithms for FPGA Placement." Thesis, University of North Texas, 2006. https://digital.library.unt.edu/ark:/67531/metadc5423/.
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Placement is one of the most important steps in physical design for VLSI circuits. For field programmable gate arrays (FPGAs), the placement step determines the location of each logic block. I present novel timing and congestion driven placement algorithms for FPGAs with minimal runtime overhead. By predicting the post-routing timing-critical edges and estimating congestion accurately, this algorithm is able to simultaneously reduce the critical path delay and the minimum number of routing tracks. The core of the algorithm consists of a criticality-history record of connection edges and a congestion map. This approach is applied to the 20 largest Microelectronics Center of North Carolina (MCNC) benchmark circuits. Experimental results show that compared with the state-of-the-art FPGA place and route package, the Versatile Place and Route (VPR) suite, this algorithm yields an average of 8.1% reduction (maximum 30.5%) in the critical path delay and 5% reduction in channel width. Meanwhile, the average runtime of the algorithm is only 2.3X as of VPR.
15
Gray, Jordan D. "Application of Floating-Gate Transistors in Field Programmable Analog Arrays." Thesis, Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7540.
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Floating-gate transistors similar to those used in FLASH and EEPROM can be used to build reconfigurable analog arrays. The charge on the floating gate can be modified to pass or block a signal in a cross-bar switch matrix, or it can be finely tuned to eliminate a threshold difference across a chip or set a bias. By using such a compact and versatile reconfigurable analog memory element, the number of analog circuit components included on an integrated circuit that is field-programmable is significantly higher. As a result, large-scale FPAAs can be built with the same impact on analog design that FPGAs have had on digital design. In my research, I investigate the areas floating-gate transistors can be used to impact FPAA design and implementation.
An FPAA can be broken up into two basic components, elements of connection and elements of computation. With respect to connection, I show that a floating-gate switch can be used in a cross-bar matrix in place of a transmission gate resulting in less parasitic capacitance and a more linear resistance for the same size transistor. I illuminate the programming issues relating to injecting a floating-gate for use as a switch, including the drain selection circuitry and rogue injection due to gate induced drain leakage. With respect to computation, I explain how a Multiple-Input Translinear Element, or MITE, can be augmented to fit in an FPAA framework. I also discuss two different MITE implementations compatible with CMOS technology, a subthreshold MOS design and a BJT MITE that uses a lateral BJT.
Beyond FPAA components, I present two alternative FPAA systems. The first is a general purpose reconfigurable analog system that uses standard analog design components that have been augmented with floating-gates. The second FPAA is built upon MITE circuits, and is focused on supporting direct system synthesis. I conclude with a discussion of a future large-scale MITE FPAA.
16
Blum, Thomas. "Modular exponentiation on reconfigurable hardware." Digital WPI, 1999. http://www.wpi.edu/Pubs/ETD/Available/etd-090399-090413/unrestricted/thesis.pdf.
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17
Hooper, Mark S. "Submicron CMOS programmable analog floating-gate circuits and arrays using DC-DC converters." Diss., Available online, Georgia Institute of Technology, 2005, 2005. http://etd.gatech.edu/theses/available/etd-12032004-155022/unrestricted/Hooper%5FMark%5FS%5F200505%5Fphd.pdf.
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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005.<br>Kucic, Matthew, Committee Member ; Hasler, Paul, Committee Chair ; Heck, Bonnie, Committee Member ; Cressler, John, Committee Member ; Anderson, David, Committee Member. Vita. Includes bibliographical references.
18
Fourie, Coenrad Johann. "A tool kit for the design of superconducting programmable gate arrays." Thesis, Stellenbosch : University of Stellenbosch, 2004. http://hdl.handle.net/10019.1/16048.
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Thesis (PhD)--University of Stellenbosch, 2003.<br>ENGLISH ABSTRACT: The development of a tool kit for the design of superconducting programmable gate
arrays (SPGAs) is discussed. A circuit optimizer using genetic algorithms is developed
and evaluated. Techniques and a program are also developed for the generation of
segmentized 3D models with which to calculate inductance in circuit structures through
FastHenry. The ability to add random variations to the dimensions of the models is
included. These tools are then used to design novel latching elements that allow the
construction of reprogrammable Rapid Single Flux Quantum (RSFQ) circuits. A circular
process is used, whereby layouts are converted back to circuit diagrams through element
extraction, and reoptimized if necessary. Two programmable frequency dividers are then
designed; one for testing the routing and switch structures and programming architecture
of an SPGA, and another compact one for testing the latching elements and off-chip
interface. The dissertation concludes with an overview of the circuits necessary for the
implementation of a fully functional SPGA.<br>AFRIKAANSE OPSOMMING: Die ontwikkeling van ’n gereedskapstel vir die ontwerp van supergeleier FPGA’s
(SPGA’s) word bespreek. Eerstens word ’n stroombaanoptimeerder, wat met genetiese
algoritmes funksioneer, ontwikkel en geëvalueer. Daarna word tegnieke en ’n program
ontwikkel om driedimensionele segmentmodelle te genereer waaruit FastHenry die
induktansie van stroombaanstrukture kan bepaal. Die vermoë om toevalsveranderinge by
die dimensies van die modelle te voeg, is ook ingesluit. Hierdie gereedskap word dan
gebruik om nuwe grendelelemente te ontwerp waarmee herprogrammeerbare Rapid
Single Flux Quantum (RSFQ) stroombane gebou kan word. ’n Sirkulêre proses word
gevolg, waarvolgens uitlegte na stroombaandiagramme teruggeskakel kan word (deur
elementonttrekkings) en, indien nodig, heroptimeer kan word. Twee programmeerbare
frekwensiedelers word daarna ontwerp; een om die pulsvervoer- en skakelstrukture,
asook programmeringsargitektuur van ’n SPGA te toets, en ’n ander, kompakter een om
die grendelelemente en warmlogika koppelvlakke mee te toets. Die proefskrif sluit af met
’n oorsig oor die stroombane benodig vir die implementering van ’n volledig funksionele
SPGA.
19
Coyne, Jack W. "FPGA-based co-processor for singular value array reconciliation tomography." Worcester, Mass. : Worcester Polytechnic Institute, 2007. http://www.wpi.edu/Pubs/ETD/Available/etd-090507-114502/.
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20
Schafer, Ingo. "Orthogonal and Nonorthogonal Expansions for Multi-Level Logic Synthesis for Nearly Linear Functions and their Application to Field Programmable Gate Array Mapping." PDXScholar, 1992. https://pdxscholar.library.pdx.edu/open_access_etds/1339.
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The growing complexity of integrated circuits and the large variety of architectures of Field Programmable Gate Arrays (FPGAs) require sophisticated logic design tools. In the beginning of the eighties the research in logic design was concentrated on the development of fast two-level AND-OR logic minimizers like the well known ESPRESSO. However, most logic functions have a smaller and often faster circuit realization as a multi-level circuit. Thus, synthesis tools emerged for the minimization of the circuit area in a multi-level realization. Most of these synthesis tools are based on the "unate paradigm". Therefore, the synthesis methods are only advantageous for functions having a minimal circuit realization based on AND-OR gates. However, many common functions have a minmal circuit realization having a mix of AND, OR and EXOR gates like counters, adders, multipliers, and parity generators. Therefore, the design of such functions with synthesis tools based on the "unated paradigm" is very inefficient. Circuits incorporating the EXOR gate have received less attention than AND-OR circuits because the EXOR gate was perceived as slower and larger in terms of its circuit realization than the AND and the OR gate. However, the upcoming of Field Programmable Gate Arrays (FPGAs) like the Xilinx Table-Look-Up (TLU) architecture the Actel ACTâ„¢ series and the CLi 6000 series from Concurrent Logic, which allow the realization of the EXOR gate with the same speed and circuit cost as the AND and OR gate, eliminates the disadvantages of the EXOR gate over the AND and OR gate. Thus, there is a strong need for logic synthesis tools that take advantage of EXOR gates. The mapping to the new FPGAs recently obtained an increased interest. The developed synthesis algorithms for FPGAs are based on the mapping and restructuring of the Directed Acyclic Graph (DAG) representation of the logic function. Even though the new FPGAs allow the realization of the EXOR gate without any speed and circuit size penalty in comparison to the AND and OR gate, the synthesis methods have been based on the "unate paradigm". To overcome the disadvantages of the current logic synthesis tools with respect to (nearly) linear functions and FPGA synthesis, this dissertation introduces an extended theory of spectral methods for multiple-valued input, incompletely specified binary output logic. The spectral methods have not been popular in logic synthesis because of their four major drawbacks: (1) the computational complexity, especially if no Fast Transform exists, (2) the memory requirement to store the function in the necessary minterm representation, (3) they cannot take efficiently advantage of incompletely specified functions, (4) suitable only for few applications in logic synthesis. To overcome the two last stated drawbacks, this dissertation introduces the T spectrum. The T spectrum separates the information obtained for the specified and not specified parts of the underlying function. Thus, it is possible to determine directly the contribution of the specified and the not specified part of the function to a single spectral coefficient. Moreover, the T spectrum is an extension of the known spectra like Walshtype, Adding, Arithmetic, and Reed-Muller spectra to any orthogonal and nonorthogonal transform describing logic functions. Thus, transforms can be constructed that describe certain gate structures, as for example the realizable functions of a FPGA macrocell. This allows the development of special synthesis algorithms for the different types of FPGA architectures. As an exemplification of this method, a complete multi-level synthesis algorithm is introduced for the circuit realization with multiplexer modules, which form the basic macrocell of the Actel ACfâ„¢ FPGA series. Additionally, this dissertation presents the classification of the applications of spectral methods in logic synthesis into three categories: (1) The decomposition of logic functions based on the information obtained by the computation of a single spectrum. As an example the linearization procedure developed by Karpowsky is generalized to incompletely specified multi-output Boolean functions. The linearization procedure is based on the computation of the Rademacher-Walsh spectrum with a following decomposition of the underlying function based on high value spectral coefficients. (2) The circuit realization of a logic function based on the repetitive application of (1). This synthesis method is exemplified by an multi-level synthesis algorithm for multiplexer gates. (3) The realization of a logic function as an AND-EXOR circuit based on a GF 2 (Galois Field (2)) spectrum. The GF 2 transforms exhibit the property that they describe a realization of the underlying function as a two-level AND-EXOR circuit. The Multiple-Valued Input Kronecker Reed-Muller (MIKRM) form is introduced as an application of GF 2 transforms. To overcome the drawbacks of spectral methods concerning the computational complexity and high memory requirements, this dissertation presents a computation method for spectra from disjoint representations. The introduced application of the disjoint cube representation and the Ordered Decision Diagrams for the computation of spectra proves to be an ideal concept. Thus, this dissertation presents general synthesis methods based on new spectral methods that overcome the deficiencies of current logic synthesis methods with respect to the synthesis for FPGAs as well as the computational complexity and memory requirements of spectral methods.
21
Jeon, Yongjoo. "High-k gate dielectric for 100 nm MOSFET application /." Full text (PDF) from UMI/Dissertation Abstracts International, 2000. http://wwwlib.umi.com/cr/utexas/fullcit?p3004296.
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22
Chen, Yuh-yue. "Enhanced hot-hole degradation and negative bias temperature instability (NBTI) in p⁺-poly PMOSFETs with oxynitride gate dielectrics /." Digital version accessible at:, 2000. http://wwwlib.umi.com/cr/utexas/main.
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23
Mulfinger, G. Robert. "Investigation of induced charge damage on self-aligned metal-gate MOS devices /." Online version of thesis, 2006. http://hdl.handle.net/1850/2036.
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Lin, Limin. "A study of gate dielectrics for wide-bandgap semiconductors GaN & SiC /." Click to view the E-thesis via HKUTO, 2007. http://sunzi.lib.hku.hk/hkuto/record/B3932252X.
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Lin, Limin, and 林立旻. "A study of gate dielectrics for wide-bandgap semiconductors: GaN & SiC." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2007. http://hub.hku.hk/bib/B3932252X.
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26
Chawla, Ravi. "Power-efficient analog systems to perform signal-processing using floating-gate MOS device for portable applications." Available online, Georgia Institute of Technology, 2005, 2004. http://etd.gatech.edu/theses/available/etd-01052005-144937/unrestricted/chawla%5Fravi%5F200505%5Fphd.pdf.
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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005.<br>Paul Hasler, Committee Member ; Joy Laskar, Committee Chair ; Phil Allen, Committee Member ; Dave Anderson, Committee Member ; Mark T. Smith, Committee Member. Includes bibliographical references.
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Deng, Linfeng, and 邓林峰. "A study on pentacene organic thin-film transistors with Hf-based oxideas gate dielectric." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2011. http://hub.hku.hk/bib/B47244513.
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Compared with its inorganic counterpart, organic thin-film transistor (OTFT) has advantages such as low-temperature fabrication, adaptability to large-area flexible substrate, and low cost. However, they usually need high operating voltage and thus are not suitable for portable applications. Although reducing their gate–dielectric thickness can lower the operating voltage, it increases their gate leakage. A better way is making use of high-κ gate dielectric, which is the main theme of this research.
Firstly, pentacene OTFTs with HfO2 gate dielectric nitrided in N2O or NH3 at 200 oC were studied. The NH3-annealed OTFT displayed higher carrier mobility, larger on/off current ratio, smaller sub-threshold swing and smaller Hooge?s parameter than the N2O-annealed device. All these advantages were attributed to more nitrogen incorporation at the dielectric surface by the NH3 annealing which provided stronger passivation of surface traps.
The incorporation of lanthanum to hafnium oxide was demonstrated to realize enhanced interface in the pentacene OTFTs. Therefore, pentacene OTFTs with HfLaO gate dielectric annealed in N2, NH3, O2 or NO at 400 oC were investigated. Among the 4 devices, the NH3-annealed OTFT obtained the highest carrier mobility, smallest sub-threshold swing and smallest 1/f noise. All these should be attributed to the improved interface between the gate dielectric and the organic semiconductor associated with the passivation effects of the NH3 annealing on the dielectric surface.
The processing temperature of OTFTs is a big concern because use of flexible or glass substrate is the trend in organic electronics. Therefore, the HfLaO gate dielectric was annealed in N2, NH3, or O2 at two different temperatures, 200 oC and 400 oC. For all the annealing gases, the OTFTs annealed at 400 oC achieved higher carrier mobility, which could be supported by SEM image that pentacene tended to form larger grains (thus less carrier scattering) on HfLaO annealed at 400 oC. Furthermore, the HfLaO film annealed at 400 oC achieved much smaller leakage because more thermal energy at higher annealing temperature could remove oxide defects more effectively.
Fluorination of the HfLaO film (annealed in N2 or NH3 at 400 oC) in a plasma based on CHF3 and O2 was also proposed. For both annealing gases, the OTFT with a 100-s plasma treatment achieved higher carrier mobility and smaller 1/f noise than that without plasma treatment. All these improvements should be due to fluorine incorporation at the dielectric surface which passivated the traps there. By contrast, for longer time (300 s or 900 s) of plasma treatment, the performance of the OTFTs deteriorated due to damage of dielectric surface induced by excessive plasma treatment.
Lastly, a comparative study was done on pentacene OTFTs with HfLaO or La2O3 as gate dielectric. For the same annealing gas (H2, N2, NH3, or O2 at 400 oC), the OTFT with La2O3 gate dielectric obtained lower carrier mobility, smaller on/off current ratio, and larger threshold voltage than that based on HfLaO. The worse performance of the OTFTs with La2O3 gate dielectric was due to the degradation of La2O3 film caused by moisture absorption.<br>published_or_final_version<br>Electrical and Electronic Engineering<br>Doctoral<br>Doctor of Philosophy
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Kang, Laeugu. "Study of HFO₂ as a future gate dielectric and implementation of polysilicon electrodes for HFO₂ films /." Full text (PDF) from UMI/Dissertation Abstracts International, 2000. http://wwwlib.umi.com/cr/utexas/fullcit?p3004301.
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Zaghloul, Yasser A. "Polarization based digital optical representation, gates, and processor." Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/43675.
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A complete all-optical-processing polarization-based binary-logic system, by which any logic gate or processor could be implemented, was proposed. Following the new polarization-based representation, a new Orthoparallel processing technique
that allows for the creation of all-optical-processing gates that produce a unique output once in a truth table, was developed. This representation allows for the implementation of all basic 16 logic gates, including the NAND and NOR gates that can be used independently to represent any Boolean expression or function. In addition, the concept of a generalized gate is presented, which opens the door for reconfigurable optical processors and programmable optical logic gates. The gates can be cascaded, where the information is always on the laser beam. The polarization of the beam, and not its intensity, carries the information.
The new methodology allows for the creation of multiple-input-multiple-output processors that implement, by itself, any Boolean function, such as specialized or non-specialized microprocessors. The Rail Road (RR) architecture for polarization optical processors (POP) is presented. All the control inputs are applied simultaneously, leading to a single time lag, which leads to a very-fast and glitch-immune POP. A simple and easy-to-follow step-by-step design algorithm is provided for the POP, and design reduction methodologies are discussed. The algorithm lends itself systematically to software programming and computer-assisted design.
A completely passive optical switch was also proposed. The switch is used to design completely passive optical gates, including the NAND gate, with their operational speeds only bound by the input beams prorogation delay. The design is used to demonstrate various circuits including the RS latch.
Experimental data is reported for the NAND and the Universal gate operating with different functionality. A minute error is recorded in different cases, which can be easily eliminated by a more dedicated manufacturing process. Finally, some field applications are discussed and a comparison between all proposed systems and the current semiconductor devices is conducted based on multiple factors, including, speed, lag, and heat generation.
30
Wu, Lifei. "Minimization of Permuted Reed-Muller Trees and Reed-Muller Trees for Cellular Logic Programmable Gate Arrays." PDXScholar, 1993. https://pdxscholar.library.pdx.edu/open_access_etds/4745.
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The new family of Field Programmable Gate Arrays, CLI 6000 from Concurrent Logic Inc realizes truly Cellular Logic. It has been mainly designed for the realization of data path architectures. However, the realizable logic functions provided by its macrocells and their limited connectivity call also for new general-purpose logic synthesis methods. The basic cell of CLi 6000 can be programmed to realize a two-input multiplexer ( A*B + C*B ), an AND/EXOR cell ( A*B Ea C ), or the basic 2-input AND, OR and EXOR gate. This suggests to using these cells for tree-like expansions. These "cellular logic" devices require regular connection patterns in the netlists resulting from logic synthesis. This thesis presents a synthesis tree searching program PROMPT, which generates AND/EXOR tree circuits from given Boolean functions. Such circuits have the property that the gate structures are AND/EXOR ( A *B EB C ), AND and EXOR which could be realized by the CLI6000 cells. Also, the connection. way in the circuit is that usually the output of one level gate is the input of the next level gate of the tree. This matches ideally to the architecture of the CLI6000 bussing network where the macrocells have only connections to their neighboring cells. PROMPT is based on the Davio expansions ( an equivalent of the Shannon expansions for the EXOR gates ) as its Boolean decomposition methods. The program includes three versions: exact version, heuristic version and fixed-variable version. The exact version of PROMPT generates the Permuted Reed-Muller Tree circuit which has the minimum number of gates. Such tree circuit is obtained by searching through all possible combinations of the expansion variable orders to get the one which needs the least number of gates. The heuristic version of PROMPT is designed to decrease the time complexity of the search algorithm when dealing with logic functions having many input variables. It generates a Permuted Reed-Muller Tree which may not have the minimum number of gates. However, the tree searching time in this version decreases tremendously compared to the time necessary in the exact version. The fix-variable version is developed to generate Reed-Muller Tree circuits. Such circuits will have the same expansion variables at the same tree level, so they can be easier routed after the placement to the CLI6000 chips. In short, the program PROMPT generates the PRM and RM tree circuits which are particularly well matched to both the realization of logic cell and connection structure of the CLI6000 device. Thus, the PRM and RM circuits can be easily placed and routed on the CLI6000 FPGAs.
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Oberdorf, Michael Craig. "Power losses and thermal modeling of a voltage source inverter." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2006. http://library.nps.navy.mil/uhtbin/hyperion/06Mar%5FOberdorf.pdf.
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Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, March 2006.<br>Thesis Advisor(s): Alexander Julian. "March 2006." Includes bibliographical references (p. 103-104). Also available online.
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Lodaya, Bhaveen. "On-Board Memory Extension on Reconfigurable Integrated Circuits using External DDR3 Memory." Master's thesis, Universitätsbibliothek Chemnitz, 2018. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-qucosa-233196.
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User-programmable, integrated circuits (ICs) e.g. Field Programmable Gate Arrays (FPGAs) are increasingly popular for embedded, high-performance data exploitation. They combine the parallelization capability and processing power of application specific integrated circuits (ASICs) with the exibility, scalability and adaptability of software-based processing solutions. FPGAs provide powerful processing resources due to an optimal adaptation to the target application and a well-balanced ratio of performance, efficiency and parallelization.
One drawback of FPGA-based data exploitation is the limited memory capacity of reconfigurable integrated circuits. Large-scale Digital Signal Processor (DSP) FPGAs provide approximately 4MB on-board random access memory (RAM) which is not sufficient to buffer the broadband sensor and result data. Hence, additional external memory is connected to the FPGA to increase on-board storage capacities.
External memory devices like double data rate three synchronous dynamic random access memories (DDR3-SDRAM) provide very fast and wide bandwidth interfaces that represent a bottleneck when used in highly parallelized processing architectures. Independent processing modules are demanding concurrent read and write access.
Within the master thesis, a concept for the integration of an external DDR3- SDRAM into an FPGA-based parallelized processing architecture is developed and implemented. The solution realizes time division multiple access (TDMA) to the external memory and virtual, low-latency memory extension to the on-board buffer capabilities. The integration of the external RAM does not change the way how on-board buffers are used (control, data-fow).
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Blanchardon, Adrien. "Synthèse d'architectures de circuits FPGA tolérants aux défauts." Thesis, Paris 6, 2015. http://www.theses.fr/2015PA066274/document.
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L'essor considérable de la technologie CMOS a permis l'accroissement de la densité d'intégration selon la loi de Moore. Cependant, la poursuite de cette évolution est en voie de ralentissement dû aux contraintes physiques et économiques. Le défi devient alors de pouvoir utiliser un maximum de circuits tout en tolérant des défauts physiques présents en leur sein. Les circuits reconfigurables de type FPGA (Field Programmable Gate Array) connaissent un succès croissant car leurs performances et leurs capacités d'intégrer des applications très complexes ont directement bénéficié de l'évolution technologique. Le but de cette thèse est de proposer une architecture de FPGA contenant des mécanismes permettant de tolérer plus de 20% d'éléments défectueux après fabrication. La première partie du manuscrit étudie les différentes architectures de FPGA (matricielles et arborescentes) ainsi que les différentes techniques de contournement des défauts. Dans la seconde partie de cette thèse, nous présentons l'architecture cible matricielle (matrice de grappes ou groupes). Cette architecture combine les avantages des architectures matricielles (sa généricité) et arborescentes (réduction du taux d'utilisation de l'interconnexion. La troisième partie de cette thèse présente le développement d'une méthode d'identification des blocs les plus critiques contenus dans le FPGA ainsi que l'impact des différentes techniques de contournement retenues et proposées sur l'architecture et sur la criticité des blocs de base du FPGA. Pour finir, nous définissons les performances des différentes techniques de contournements en termes de tolérance aux défauts, de performances temporelles et de surface<br>The increasing integration density according to Moore’s law is being slowed due to economic and physical limits. However, this technological evolution involves an higher number of physical defects after manufacturing circuit. As yield goes down, one of the future challenges is to find a way to use a maximum of fabricated circuits while tolerating physical defects spread all over the chip. Fiel Programmable Gate Array (FPGA) are integrated circuits that contain logic blocks and reconfigurable interconnect. Their ability to integrate more complex applications, their flexibility and good performance make FPGAs the perfect target architecture. The aim of this thesis is to propose an FPGA architecture containing mechanisms to tolerate more than 20% of defective resources after manufacture. The first part of the manuscript studies the different FPGA architectures (mesh and tree) and different defects bypass techniques. In the second part of this thesis, we present the target architecture called Mesh of Clusters (MoC). This architecture combines the advantages of mesh architectures (genericity) and tree (reduction of the interconnect). The third contribution of this thesis is the development of a method to identify the most critical blocks in the FPGA and the impact of all bypass techniques on the architecture and on the criticality. Finally, we define the performance of all bypass techniques in terms of defect tolerance, timing and area overhead. Finally, thanks to these local redundancy techniques, we are able to tolerate more than 20% of defect on the FPGA architecture. In addition, the designer can fix his own metric in terms of area, timing and defect tolerance
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Zhou, Jing 1959. "LOVERD--a logic design verification and diagnosis system via test generation." Thesis, The University of Arizona, 1989. http://hdl.handle.net/10150/291686.
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The development of cost-effective circuits is primarily a matter of economy. To achieve it, design errors and circuit flaws must be eliminated during the design process. To this end, considerable effort must be put into all phases of the design cycle. Effective CAD tools are essential for the production of high-performance digital systems. This thesis describes a CAD tool called LOVERD, which consists of ATPG, fault simulation, design verification and diagnosis. It uses test patterns, developed to detect single stuck-at faults in the gate-level implementation, to compare the results of the functional level description and its gate-level implementation. Whenever an error is detected, the logic diagnosis tool can be used to provide useful information to designers. It is shown that certain types of design errors in combinational logic circuits can be detected and allocated by LOVERD efficiently.
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Blanchardon, Adrien. "Synthèse d'architectures de circuits FPGA tolérants aux défauts." Electronic Thesis or Diss., Paris 6, 2015. http://www.theses.fr/2015PA066274.
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L'essor considérable de la technologie CMOS a permis l'accroissement de la densité d'intégration selon la loi de Moore. Cependant, la poursuite de cette évolution est en voie de ralentissement dû aux contraintes physiques et économiques. Le défi devient alors de pouvoir utiliser un maximum de circuits tout en tolérant des défauts physiques présents en leur sein. Les circuits reconfigurables de type FPGA (Field Programmable Gate Array) connaissent un succès croissant car leurs performances et leurs capacités d'intégrer des applications très complexes ont directement bénéficié de l'évolution technologique. Le but de cette thèse est de proposer une architecture de FPGA contenant des mécanismes permettant de tolérer plus de 20% d'éléments défectueux après fabrication. La première partie du manuscrit étudie les différentes architectures de FPGA (matricielles et arborescentes) ainsi que les différentes techniques de contournement des défauts. Dans la seconde partie de cette thèse, nous présentons l'architecture cible matricielle (matrice de grappes ou groupes). Cette architecture combine les avantages des architectures matricielles (sa généricité) et arborescentes (réduction du taux d'utilisation de l'interconnexion. La troisième partie de cette thèse présente le développement d'une méthode d'identification des blocs les plus critiques contenus dans le FPGA ainsi que l'impact des différentes techniques de contournement retenues et proposées sur l'architecture et sur la criticité des blocs de base du FPGA. Pour finir, nous définissons les performances des différentes techniques de contournements en termes de tolérance aux défauts, de performances temporelles et de surface<br>The increasing integration density according to Moore’s law is being slowed due to economic and physical limits. However, this technological evolution involves an higher number of physical defects after manufacturing circuit. As yield goes down, one of the future challenges is to find a way to use a maximum of fabricated circuits while tolerating physical defects spread all over the chip. Fiel Programmable Gate Array (FPGA) are integrated circuits that contain logic blocks and reconfigurable interconnect. Their ability to integrate more complex applications, their flexibility and good performance make FPGAs the perfect target architecture. The aim of this thesis is to propose an FPGA architecture containing mechanisms to tolerate more than 20% of defective resources after manufacture. The first part of the manuscript studies the different FPGA architectures (mesh and tree) and different defects bypass techniques. In the second part of this thesis, we present the target architecture called Mesh of Clusters (MoC). This architecture combines the advantages of mesh architectures (genericity) and tree (reduction of the interconnect). The third contribution of this thesis is the development of a method to identify the most critical blocks in the FPGA and the impact of all bypass techniques on the architecture and on the criticality. Finally, we define the performance of all bypass techniques in terms of defect tolerance, timing and area overhead. Finally, thanks to these local redundancy techniques, we are able to tolerate more than 20% of defect on the FPGA architecture. In addition, the designer can fix his own metric in terms of area, timing and defect tolerance
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Pimenta, Valdiney Alves. "Metodologia Brazil-IP : registro do metodo e analise de casos de uso e experiencias ocorridas durante os trabalhos deste consorcio." [s.n.], 2008. http://repositorio.unicamp.br/jspui/handle/REPOSIP/276080.
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Orientador: Rodolfo Jardim de Azevedo<br>Dissertação (mestrado) - Universidade Estadual de Campinas, Instituto de Computação<br>Made available in DSpace on 2018-08-11T08:21:02Z (GMT). No. of bitstreams: 1
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Previous issue date: 2008<br>Resumo: Contrariando as projeções para crescimento da economia mundial, o mercado de semicondutores cresce de forma acelerada, a uma taxa superior a 10% ao ano, movimentando anualmente mais de 270 bilhões de dólares. Acompanhando este crescimento, a importação de componentes eletrônicos pelo Brasil é um dos ítens que mais contribuem negativamente em sua balança comercial, deixando claro que o país não tem atuado de forma econômicamente interessante neste mercado. Um consórcio formado por 8 das principais universidades brasileiras, chamado BrazilIP, foi criado tendo como principal intuito inserir o Brasil no seleto grupo de países produtores de artefatos em semicondutores, em especial, na produção de componentes na forma de propriedade intelectual (IPs). Este grupo tem alcançado considerável sucesso ao longo dos últimos anos e é o foco da presente dissertação. O autor, que participou dos três primeiros anos de vida deste consór.cio, buscou registrar, na forma de método, as propostas, cursos, documentos e experiências ocorridas durante seu envolvimento. São também apresentados casos reais de aplicação da metodologia no desenvolvimento de um decoder de áudio MP3 e um codificador RSA. Uma das intenções deste trabalho é evitar que todo o conhecimento, adquirido e gerado pelo consórcio, se volatilize, além de permitir, através deste registro e exemplos de seu uso, que o método seja facilmente reaplicado em outras instituições de pesquisa. Somando-se a estas contribuições, didáticas e documentais, a dissertação ainda analisa vários pontos, positivos e negativos, sobre sua utilização e pioneirismo, propondo complementações e aprimoramentos<br>Abstract: Contrary to the projections ofthe worldwide economy's growth rate, the semiconductor market, estimated in 270 billions of dollars, grows over 10% each year. The electronic components market in Brazil has been growing at the same rate and poses a huge payout for the country in this area, leading to efforts in semiconductor training. The Brazil-IP consortium, formed by 8 of the major universities in Brazil, was created to try to insert the .country into the select group of countries that design semiconductors, focusing on intellectual property (IP) market. This group has achieved a considerable success over the past years and the systematization of its methodology is the focus of this dissertation. The contributions of this work are divided into three groups: (1) It registers the methodology in a reproducible way since the proposals, courses, documents and experiences that took place during the fist years were not put together. Since the author participated in the first three years, he is one of the recommended persons to do that. (2) It also exemplifies the methodology with real case studies, MP3 decoder and RSA, which is small enough to be used as first case exercise for new designers to be trained. (3) Finally it comments, makes suggestions and analyses the positive and negative points of the methodology as applied in the Institute of Computing, proposing enhancements and complementation<br>Mestrado<br>Sistemas de Computação<br>Mestre em Ciência da Computação
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Srinivasan, Venkatesh. "Programmable Analog Techniques For Precision Analog Circuits, Low-Power Signal Processing and On-Chip Learning." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/11588.
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In this work, programmable analog techniques using floating-gate transistors have been developed to design precision analog circuits, low-power signal processing primitives and adaptive systems that learn on-chip. Traditional analog implementations lack programmability with the result that issues such as mismatch are corrected at the expense of area. Techniques have been proposed that use floating-gate transistors as an integral part of the circuit of interest to provide both programmability and the ability to correct for mismatch. Traditionally, signal processing has been performed in the digital domain with analog circuits handling the interface with the outside world. Such a partitioning of responsibilities is inefficient as signal processing involves repeated multiplication and addition operations that are both very power efficient in the analog domain. Using programmable analog techniques, fundamental signal processing primitives such as multipliers have been developed in a low-power fashion while preserving accuracy. This results in a paradigm shift in signal processing. A co-operative analog/digital signal processing framework is now possible such that the partitioning of tasks between the analog and digital domains is performed in a power efficient manner. Complex signal processing tasks such as adaptive filtering that learn the weight coefficients are implemented by exploiting the non-linearities inherent with floating-gate programming. The resulting floating-gate synapses are compact, low-power and offer the benefits of non-volatile weight storage. In summary, this research involves developing techniques for improving analog circuit performance and in developing power-efficient techniques for signal processing and on-chip learning.
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Doré, Jean-Baptiste. "Optimisation conjointe de codes LDPC (Low Density Parity Check) et de leurs architectures de décodage et mise en oeuvre sur FPGA (Field Programmable Gate Array)." Rennes, INSA, 2007. https://tel.archives-ouvertes.fr/tel-00191155v2.
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La découverte dans les années 90 des Turbo-codes et, plus généralement du principe itératif appliqué au traitement du signal, a révolutionné la manière d'appréhender un système de communications numériques. Cette avancée notable a permis la re-découverte des codes correcteurs d'erreurs inventés par R. Gallager en 1963, appelés codes Low Density Parity Check (LDPC). L'intégration des techniques de codage dites avancées, telles que les Turbo-codes et les codes LDPC, se généralise dans les standards de communications. Dans ce contexte, l'objectif de cette thèse est d'étudier de nouvelles structures de codage de type LDPC associées à des architectures de décodeurs alliant performances et flexibilité. Dans un premier temps, une large présentation des codes LDPC est proposée incluant les notations et les outils algorithmiques indispensables à la compréhension. Cette introduction des codes LDPC souligne l'intérêt qu'il existe à concevoir conjointement le système de codage/décodage et les architectures matérielles. Dans cette optique, une famille de codes LDPC particulièrement intéressante est décrite. En particulier nous proposons des règles de construction de codes pour en contraindre le spectre des distances de Hamming. Ces contraintes sont intégrées dans la définition d'un nouvel algorithme de définition de codes travaillant sur une représentation compressée du code par un graphe. Les propriétés structurelles du code sont ensuite exploitées pour définir l'algorithme de décodage. Cet algorithme, caractérisé par le fait qu'il considère une partie du code comme un code convolutif, converge plus rapidement que les algorithmes habituellement rencontrés tout en permettant une grande flexibilité en termes de rendements de codage. Différentes architectures de décodeurs sont alors décrites et discutées. Des contraintes sur les codes sont ensuite exposées pour exploiter pleinement les propriétés des architectures. Dans un dernier temps, une des architectures proposées est évaluée par l'intégration d'un décodeur sur un composant programmable. Dans différents contextes, des mesures de performances et de complexité montrent l'intérêt de l'architecture proposée<br>The introduction of Turbo-codes in the early 90's and, more generally the iterative principle, has deeply modified the methods for the design of communication systems. This breakthrough has also resurrected the Low Density Parity Check (LDPC) codes invented by R. Gallager in 1963. Advanced channel coding techniques such as Turbo-codes and LDPC, are now increasingly considered for introduction into communication systems and standards. This evolution towards industrialization motivates the definition of new flexible and efficient decoding architecture for LDPC codes. In this thesis, we focus our research on the iterative decoding of LDPC codes and their hardware implementation. We first introduce basic concepts and notations for LDPC codes, which are necessary for a good comprehension. This introduction underlines the interest of jointly designing codes, decoding algorithm and architecture. From this perspective, a family of LDPC codes is described. We define some design rules to constrain the distance spectrum of the code. These constraints are introduced into a new algorithm for the design of the code working on a compact representation of the code graph. A new decoding algorithm is also defined, taking advantage of the intrinsic properties of the code structure. Convergence of the decoding algorithm is increased compared to classical decoding algorithm for LDPC codes. Performance and flexibility of this algorithm is discussed. Different architectures are then described and studied. Some constraints on the codes are derived to target an architecture. The last part of the thesis illustrates the implementation of one of the architectures discussed into a field-programmable gate array (FPGA). Performance and complexity measures are presented for various contexts, showing the interest of the concept for all these cases
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Foote, David W. "The Design, Realization and Testing of the ILU of the CCM2 Using FPGA Technology." PDXScholar, 1994. https://pdxscholar.library.pdx.edu/open_access_etds/4703.
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Most existing computers today are built upon a subset of the arithmetic system which is based upon the foundation of set theory. All formal systems can be expressed in terms of arithmetic and logic on current arithmetic computers through an appropriate model, then work with the model using software manipulation. However, severe speed degradation is the price one must pay for using a software-based approach, making several high-level formal systems impractical. To improve the speed at which computers can implement these high-level systems, one must either design special hardware, implementing specific operations much like math and image processing coprocessors, or execute operations upon multiple processors in a parallel fashion. Due to the increase in developing applications for the manipulation of logic functions, an interest in the logic machine has arisen. Many applications such as logic optimization, simulation, pattern recognition and image processing can be better implemented with a logic machine. This thesis proposes the design, hardware realization, and testing of the iterative logic unit (ILU) of the Cube Calculus Machine II (CCM2). The CCM2 is a general purpose computer with an architecture that emphasizes a data path designed to execute operations of cube calculus, a popular algebraic model used in the minimization of Boolean functions. The ILU is an iterative logic array of cells (ITs) using internal distributed control, enabling the execution of basic cube operations, while the Control Unit (CU) handles global signals from the host computer. The ILU of the CCM2 has been realized in hardware using Xilinx Logic Cell Arrays (LCAs). FPGAs offer the logic density and versatility of gate arrays, with the off-the shelf availability and time-to-market advantages of standard user-programmable devices. These devices can be reconfigured, allowing multiple revisions and future design generations to accommodate the same device, thus saving design and production costs, an ideal solution to the resource and financial problems plaguing the University environment.
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Her, Shyang-Kuen. "Improved I/O pad positions assignment algorithm for sea-of-gates placement." PDXScholar, 1992. https://pdxscholar.library.pdx.edu/open_access_etds/4316.
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A new heuristic method to improve the I/O pad assignment for the sea-of-gates placement algorithm "PROUD" is proposed. In PROUD, the preplaced I/O pads are used as the boundary conditions in solving sparse linear equations to obtain the optimal module placement. Due to the total wire length determined by the module positions is the strong function of the preplaced I/O pad positions, the optimization of the I/O pad circular order and their assignment to the physical locations on the chip are attempted in the thesis. The proposed I/O pad assignment program is used as a predecessor of PROUD. The results have revealed excellent improvement.
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Choudhary, Aarti. "A process variation tolerant self compensation sense amplifier design." Connect to this title, 2008. http://scholarworks.umass.edu/theses/166/.
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Choy, C. S. O. "A bipolar multilevel differential logic gate array." Thesis, University of Manchester, 1986. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.378029.
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43
Mashayekhi, Mohammad. "Inkjet-configurable gate arrays: towards application specific printed electronic circuits." Doctoral thesis, Universitat Autònoma de Barcelona, 2016. http://hdl.handle.net/10803/402272.
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Over the last decades, Organic Electronics has been emerging as a multidisciplinary and
innovative way to generate electronic devices and systems. It is intended to provide a
platform for low-cost, large-area, and low-frequency Printable Electronics on a variety
of substrates, including flexible plastic substrates. Just as the first information
revolution caused by integrated silicon circuits, PE is expected to cause another
revolution characterized by the distribution of information systems in all aspects of life.
Although the integrated circuits, based on Organic Thin Film Transistors (OTFT), are
not meant to compete with the silicon-based high-end industry, their performance have
already reached to a level enabling the use of organic technology to an ever-increasing
number of emerging applications, such as flexible optical displays, sensors, and low-end
microelectronics.
Currently, most of the digital integrated circuits are yet designed by specifying the
layout of each individual transistor and their interconnections. Full-custom design is
extremely labor-intensive, time consuming for complex circuits and it requires
advanced computer software in the design process, and several expensive mask sets in
the fabrication process. Besides, taking the soft and hard faults at transistor level into
account, the yield at system level is expected to be very low, since failure of one
transistor causes the entire circuit to fail. This is more important for technologies based
in non-crystalline materials (such as silicon) in which deposition and layer formation is
more irregular. On the other side, organic electronics is more complex than Printed
Circuit Boards (PCB) in the sense that these do not include active devices and do not
reach high integration level. Furthermore, similar to any new-born technology, the
performance of organic electronic circuits is degraded due to some limitations in
technological and materials sides. That being said, the question arises as to whether
circuit design techniques can be employed to compensate these bottlenecks so as to
meet yield and performance requirements.
The work presented in this thesis contributes to overcome the above-mentioned issues
by proposing the novel concept of Inkjet-configurable Gate Array (IGA) as a designmanufacturing
method for the direct mapping of digital functions on top of new
prefabricated structures. IGA brings together the advantages of semi-custom gate array
methodology, field-configurability, and fault-tolerance, and adopt it to Application
Specific Printed Electronic Circuit (ASPEC), which is the equivalent term to
Application Specific Integrated Circuit (ASIC), but for PE.
This alternative has two main advantages. Firstly, it allows implementing individual
circuit personalization at a very low cost through the best use of additive mask-less
digital printing techniques (e.g. Inkjet, Superfine Jet, and etc.) "in the field", thus
avoiding the need for One Time Programmable ROM-like (or E2PROM) devices.
Secondly, fault tolerance technique allows the adoption of a failure map to use only
working transistors for circuit implementation, thus, it helps to obtain high yield circuits
out of mid-yield foils.
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Honoré, Francis. "Energy-aware architectures, circuits and CAD for field programmable gate arrays." Thesis, Massachusetts Institute of Technology, 2006. http://hdl.handle.net/1721.1/37911.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.<br>Includes bibliographical references (p. 113-117).<br>Field Programmable Gate Arrays (FPGAs) are a class of hardware reconfigurable logic devices based on look-up tables (LUTs) and programmable interconnect that have found broad acceptance for a wide range of applications. However, power consumption is one of the leading obstacles to broader adoption of FPGAs in energy-constrained applications. This thesis addresses active power consumption in FPGAs through the introduction of fine grain configurable power domains. By introducing fine grain power controls, sections of the design that have excess timing margins are able to run at reduced voltage thereby saving power. Delay critical sections can continue to operate at full voltage to maintain the overall performance of the design. A design flow was developed for the analysis and implementation of these configurable power domains. A test chip using dual core voltages fabricated in a 0.18 /m CMOS process features these power reduction techniques. The test chip includes an 8x8 array of logic tiles and a 9x9 switch matrix grid. The chip design flow utilizes a mix of synthesized logic and custom cells. 'The layout required a customized approach to overcome some of the challenges of implementing a fine granularity multiple voltage design.<br>(cont.) A set of benchmark circuits shows a measured average energy-delay improvement of nearly 2X. Additionally, enhancements for the implementation of finite impulse response filters provide a 2.5x improvement in the energy-delay product relative to standard FPGA architectures. This thesis also addresses static: power consumption by reducing sub-threshold leakage through the use of distributed multi-threshold CMOS. A separate test chip using a 0.13 m dual VT process demonstrates the advantages of distributed power gating for sub-threshold leakage reduction by achieving over 10X reduction in static power.<br>by Francis A. Honoré.<br>Ph.D.
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Stamoulis, Iakovos. "Computer graphics hardware using ASICs, FPGAs and embedded logic." Thesis, University of Sussex, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.313943.
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The introduction of new technologies such as Field Programmable Gate Arrays (FPGAs) with high gate counts and embedded memory Applications Specific Integrated Circuits (ASICs) gives greater scope to the design of computer graphics hardware. This thesis investigates the features of the current generation of FPGAs and complex programmable logic devices (CPLD) and assesses their suitability as replacements for ASIC technologies, and as prototyping tools for their verification prior to fabrication. The traditional methodologies and techniques used for digital systems are examined for application to FPGA devices and novel design flow and implementation techniques are proposed. The new methodology and design flow uses a contemporary top down approach using hardware description languages and combines the flexibility of those methods with the efficiency of detailed low level design techniques. As an example of this methodology, a set of floating point arithmetic units consisting of a adder/subtraction, multiplication and division were designed using novel alternative algorithms that significantly outperformed algorithms designed with traditional methods in terms of both size and performance.T hese techniquesu sed were used to form a ToolKit that can accelerateth e design of systems that use floating point units for computer graphics systems. This ToolKit, in combination with a precision investigation methods can be used to generate floating point arithmetic units that have the required precision with minimum required hardware resources. Another emerging technology is that of embedded memory. Recent advancements in semiconductor fabrication processes make it feasible to integrate large amounts of DRAM, SRAM and logic on a single silicon die. This thesis will show the changes in the design flow that are require to take advantage of this new technology. A new embedded logic ToolKit was created that facilitates the exploitation of this technology. Finally, as an example to this methodology, a novel processor oriented towards 3D graphics was designedA. n architecturale xploration driven by novel trace-drivenp erformancea nalysism ethods is detailed that was used to model and tune the processor for the execution of global illumination computer graphics algorithms. The adaptation of these algorithms for execution in our processor is demonstrateda nd the performancea dvantagesth at can be extracteda re shown
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Green, A. D. P. "A percolation model for VLSI routing processes and its application in analysis and design of channelled structures." Thesis, University of Essex, 1988. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.234181.
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Zhang, Chengjin. "An investigation into the realisation and testing of a universal logic primitive gate array." Thesis, University of Bath, 1988. https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.384137.
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Clark, Christopher R. "A Unified Model of Pattern-Matching Circuits for Field-Programmable Gate Arrays." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/14138.
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The objective of this dissertation is to develop a methodology for describing the functionality, analyzing the complexity, and evaluating the performance of a large class of pattern-matching circuit design approaches for field-programmable gate arrays (FPGAs). The developed methodology consists of three elements. The first is a functional model and associated nomenclature that unifies a significant portion of published circuit design approaches while also illuminating many novel approaches. The second is a set of analytical expressions that model the area and time complexity of each circuit design approach based on attributes of a given pattern set. Third, software tools are developed that facilitate architectural design space exploration and circuit implementation. This methodology is used to conduct an extensive evaluation and comparison of design approaches under a wide range of conditions using pattern sets from multiple application domains as well as synthetic pattern sets. The results indicate strong dependences between pattern set properties and circuit performance and provide new insights on the fundamental nature of various design approaches.
A number of techniques have been proposed for designing pattern-matching hardware circuits with reconfigurable FPGA chips. The use of FPGAs enables high performance because the circuits can be customized for a particular application and pattern set. A relatively unstudied consequence of tailoring circuits for specific patterns is that circuit area and performance are affected by various properties of the patterns used. Most previous work in this field only considers a single design approach and a small number of pattern sets. Therefore, it is not clear how each design is affected by pattern set properties. For a given set of patterns, it is difficult to determine which approach would be the most efficient or provide the highest performance. Previous attempts to compare approaches using results from different publications are conflicting and inconclusive due to variations in the FPGA devices, patterns, and circuit optimizations used. There has been no attempt to evaluate a wide range of designs under a common set of conditions. The methodology presented in this dissertation provides a framework for studying multiple aspects of FPGA pattern-matching circuits in a controlled and consistent manner.
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Subramanian, Shyam. "Methods for synthesis of multiple-input translinear element networks." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/22591.
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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2008.<br>Committee Chair: Anderson, David; Committee Member: Habetler, Thomas; Committee Member: Hasler, Paul; Committee Member: McClellan, James; Committee Member: Minch, Bradley.
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MAL, PROSENJIT. "DESIGN AND DEMONSTRATION OF A MULTI-TECHNOLOGY FIELD PROGRAMMABLE GATE ARRAY ARCHITECTURE." University of Cincinnati / OhioLINK, 2004. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1081274672.
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