Zeitschriftenartikel: „Gate array circuits“

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Kunts, A. V., O. V. Dvornikov, and V. A. Tchekhovski. "Design of BJT-JFET Operational Amplifiers on the Master Slice Array." Doklady BGUIR 21, no. 6 (January 4, 2024): 29–36. http://dx.doi.org/10.35596/1729-7648-2023-21-6-29-36.

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The use of dual-gate field-effect transistors located on the base matrix crystal MH2XA031, controlled by a p–n junction needed to reduce the input current of operational amplifiers is studied. Typical circuits of operational amplifiers, containing: source repeaters connected to the inputs of the operational amplifier on complementary bipolar transistors; input differential stage on p-JFET with a “current mirror” load on n–p–n-transistors; input differential in the form of a “folded cascode” on a p-JFET are analyzed. To minimize the input current, it is re commended to use bootstrapped feedback to keep the drain-to-source voltage of the input JFETs low, independent of the input common-mode voltage, and to connect only the top gate of the dual-gate JFET to the op-amp input. The electrical circuits for MH2XA031 elements and the results of circuit simulation of the developed amplifiers, called OAmp10J, OAmp11.1, OAmp11.2, are presented. Accounting the established features of the input stages and operating modes of active elements in circuit design will allow to create an operational amplifier with the required combination of basic parameters.

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Abraitis, Vidas, and Žydrūnas Tamoševičius. "Transition Test Patterns Generation for BIST Implemented in ASIC and FPGA." Solid State Phenomena 144 (September 2008): 214–19. http://dx.doi.org/10.4028/www.scientific.net/ssp.144.214.

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Transition delay testing of sequential circuits in a clocked environment is analyzed. There are presented two test pattern generator methods for built in self testing of the circuit implemented as Application Specific Integrated Circuit (ASIC) and Field Programmable Gate Array (FPGA) of Virtex family. Cellular automaton and Linear Feedback Shift Register (LFSR) structures are used for test sequence generation. The circuits are tested as the black boxes under Transition fault model. Experimental results of the test pattern generation methods are presented and analyzed. Results compared with exhaustive test of transition faults for ASICs and programmable integrated circuits with given configuration.

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Mohammadi, Hossein, and Keivan Navi. "Energy-Efficient Single-Layer QCA Logical Circuits Based on a Novel XOR Gate." Journal of Circuits, Systems and Computers 27, no. 14 (August 23, 2018): 1850216. http://dx.doi.org/10.1142/s021812661850216x.

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Quantum-dot Cellular Automata (QCA) as a nanoscale transistor-less device technology offers distinguishing advantages over the limitations of CMOS circuits. This nanoelectronic is based on the mapping of binary logic in the two excess electrons configuration within a four-dot cell. In this paper, we propose a new ultra-low energy and low-complexity two-input XOR gate which can be employed as a basic component in designing a wide range of QCA logical circuits. For performance evaluation of the presented design in a large array of QCA structures, even parity generator circuit with different lengths up to 32 bits as well as LFSR circuit are designed and analyzed as instances of logical circuits. The simulation results reveal that our proposed designs have significant improvements in contrast to counterparts from hardware implementation requirements and energy consumption aspects. QCADesigner tool is utilized to evaluate functional correctness of the proposed circuits and power dissipation is evaluated using QCAPro simulator as an accurate power estimator tool.

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Mowafy, Aya Nabeel. "Asynchronous Circuits Design Using a Field Programmable Gate Array." International Journal for Research in Applied Science and Engineering Technology 6, no. 4 (April 30, 2018): 2423–32. http://dx.doi.org/10.22214/ijraset.2018.4412.

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5

Sato, Ryoichi, Yuta Kodera, Md Arshad Ali, Takuya Kusaka, Yasuyuki Nogami, and Robert H. Morelos-Zaragoza. "Consideration for Affects of an XOR in a Random Number Generator Using Ring Oscillators." Entropy 23, no. 9 (September 5, 2021): 1168. http://dx.doi.org/10.3390/e23091168.

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A cloud service to offer entropy has been paid much attention to. As one of the entropy sources, a physical random number generator is used as a true random number generator, relying on its irreproducibility. This paper focuses on a physical random number generator using a field-programmable gate array as an entropy source by employing ring oscillator circuits as a representative true random number generator. This paper investigates the effects of an XOR gate in the oscillation circuit by observing the output signal period. It aims to reveal the relationship between inputs and the output through the XOR gate in the target generator. The authors conduct two experiments to consider the relevance. It is confirmed that combining two ring oscillators with an XOR gate increases the complexity of the output cycle. In addition, verification using state transitions showed that the probability of the state transitions was evenly distributed by increasing the number of ring oscillator circuits.

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Kuboki, S., I. Masuda, T. Hayashi, and S. Torii. "A 4K CMOS gate array with automatically generated test circuits." IEEE Journal of Solid-State Circuits 20, no. 5 (October 1985): 1018–24. http://dx.doi.org/10.1109/jssc.1985.1052430.

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7

AKELLA, KAPILAN MAHESWARAN VENKATESH. "PGA-STC: programmable gate array for implementing self-timed circuits." International Journal of Electronics 84, no. 3 (March 1998): 255–67. http://dx.doi.org/10.1080/002072198134823.

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8

Murtaza, Ali Faisal, and Hadeed Ahmed Sher. "A Reconfiguration Circuit to Boost the Output Power of a Partially Shaded PV String." Energies 16, no. 2 (January 4, 2023): 622. http://dx.doi.org/10.3390/en16020622.

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An optical isolator circuit is developed to detect and dynamically relocate the photovoltaic (PV) module under partial shading. The suggested system control structure operates in two modes. Mode 1 governs the system at global maxima (GM) by tracing the power-voltage (PV) curve. Mode 2 detects and separates all the bypassed modules from a PV string/array by means of a decentralized control and stores its power in the battery. Simulations are performed on different shading patterns to verify the efficacy of the suggested system. The results showcase that the averaged harnessed power using the proposed circuit is 25.26% more than the total cross-tied (TCT) and series-parallel (SP) array configurations. The proposed circuit does not require complex gate driver circuits and large switch counts. The circuit is scalable and can be implemented on an “N × N” array.

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Jaafar, Anuar, Norhayati Soin, Sharifah F. Wan Muhamad Hatta, Sani Irwan Salim, and Zahriladha Zakaria. "Multipoint Detection Technique with the Best Clock Signal Closed-Loop Feedback to Prolong FPGA Performance." Applied Sciences 11, no. 14 (July 12, 2021): 6417. http://dx.doi.org/10.3390/app11146417.

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The degradation effect of a field-programmable gate array becomes a significant issue due to the high density of logic circuits inside the field-programmable gate array. The degradation effect occurs because of the rapid technology scaling process of the field-programmable gate array while sustaining its performance. One parameter that causes the degradation effect is the delay occurrence caused by the hot carrier injection and negative bias temperature instability. As such, this research proposed a multipoint detection technique that detects the delay occurrence caused by the hot carrier injection and negative bias temperature instability degradation effects. The multipoint detection technique also assisted in signaling the aging effect on the field-programmable gate array caused by the delay occurrence. The multipoint detection technique was also integrated with a method to optimize the performance of the field-programmable gate array via an automatic clock correction scheme, which could provide the best clock signal for prolonging the field-programmable gate array performance that degraded due to the degradation effect. The delay degradation effect ranged from 0° to 360° phase shifts that happened in the field-programmable gate array as an input feeder into the multipoint detection technique. With the ability to provide closed-loop feedback, the proposed multipoint detection technique offered the best clock signal to prolong the field-programmable gate array performance. The results obtained using the multipoint detection technique could detect the remaining lifetime of the field-programmable gate array and propose the best possible signal to prolong the field-programmable gate array’s performance. The validation showed that the multipoint detection technique could prolong the performance of the degraded field-programmable gate array by 13.89%. With the improvement shown using the multipoint detection technique, it was shown that compensating for the degradation effect of the field-programmable gate array with the best clock signal prolonged the performances.

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Cherepacha, Don, and David Lewis. "DP-FPGA: An FPGA Architecture Optimized for Datapaths." VLSI Design 4, no. 4 (January 1, 1996): 329–43. http://dx.doi.org/10.1155/1996/95942.

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This paper presents a new Field-Programmable Gate Array (FPGA) architecture which reduces the density gap between FPGAs and Mask-Programmed Gate Arrays (MPGAs) for datapath oriented circuits. This is primarily achieved by operating on data as a number of identically programmed four-bit slices. The interconnection network incorporates distinct sets of resources for routing control and data signals. These features reduce circuit area by sharing programming bits among four-bit slices, reducing the total number of storage cells required.This paper discusses the requirements of logic blocks and routing structures that can be used to implement typical circuits containing a number of regularly structured datapaths of various sizes, as well as a small number of irregularities. It proposes a specific set of logic block architectures and analyzes it empirically. Experimental results show that the block with the smallest estimated area contains the following features: a lookup table with four read ports, a dedicated carry chain using a bidirectional four-bit carry skip circuit, a four-bit register with enable and direct input capabilities, and four three-state buffers. Further estimates of implementation area predict that the area of a design's datapath can be reduced by a factor of approximately two compared to a conventional FPGA through the use of programming bit sharing.

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Reaungepattanawiwat, Chalermpol, and Yutthana Kanthaphayao. "Voltage Multiplier Circuits with Coupled-Inductor Applied to a High Step-Up DC-DC Converter." Applied Mechanics and Materials 781 (August 2015): 418–21. http://dx.doi.org/10.4028/www.scientific.net/amm.781.418.

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This paper presents a high voltage gain of a DC-DC converter. The proposed system consists of voltage multiplier circuits and a coupled inductor of a boost DC-DC converter. The input voltage of the voltage multiplier circuit is the induced voltage of inductor at a boost DC-DC converter. The field programmable gate array (FGPA) is used for generating the control signal of the proposed system. To verify the proposed circuit, an experiment was conducted from the prototype circuit. The proposed circuit can step-up the voltage with high voltage gain. Moreover, the voltage across the switch is very low.

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Chen, Yanling, Haozhou Sun, Wei Li, Yanjun Song, and Peng Dub. "65‐4: A Novel GOA Circuit for Large‐size TFT‐LCD Display." SID Symposium Digest of Technical Papers 55, S1 (April 2024): 564. http://dx.doi.org/10.1002/sdtp.17141.

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In recent years, the gate driven on array (GOA) has become increasingly popular in the a‐Si TFT‐LCD industry. In this study, a new GOA circuit was designed by adjusting the ratio of inverter TFT size, and the operation principle of this new GOA circuit was studied in detail. The K/P point voltage in the GOA circuit was effectively optimized, which could avoid the sharp drop of GOA margin during the reliability testing at high temperature and high humidity (60°C/90%, HTHH). The new GOA circuit was used to drive 55” LCD panels that passed a 1500‐hour HTHH test, with only a 6 V loss in GOA margin compared to the original circuit's 13 V loss. This suggests an improvement in the life of GOA circuits in HTHH environments. This study provides a new route to enhance the GOA circuit properties of a‐Si large‐size TFT‐LCDs.

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Harrison, R. R., J. A. Bragg, P. Hasler, B. A. Minch, and S. P. Deweerth. "A CMOS programmable analog memory-cell array using floating-gate circuits." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 48, no. 1 (2001): 4–11. http://dx.doi.org/10.1109/82.913181.

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TANAKA, YU. "EXACT NON-IDENTITY CHECK IS NQP-COMPLETE." International Journal of Quantum Information 08, no. 05 (August 2010): 807–19. http://dx.doi.org/10.1142/s0219749910006599.

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To understand quantum gate array complexity, we define a problem named exact non-identity check, which is a decision problem to determine whether a given classical description of a quantum circuit is strictly equivalent to the identity or not. We show that the computational complexity of this problem is non-deterministic quantum polynomial-time (NQP)-complete. As corollaries, it is derived that exact non-equivalence check of two given classical descriptions of quantum circuits is also NQP-complete and that minimizing the number of quantum gates for a given quantum circuit without changing the implemented unitary operation is NQP-hard.

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M, Thillai Rani, Rajkumar R, Sai Pradeep K.P, Jaishree M, and Rahul S.G. "Integrated extreme gradient boost with c4.5 classifier for high level synthesis in very large scale integration circuits." ITM Web of Conferences 56 (2023): 01005. http://dx.doi.org/10.1051/itmconf/20235601005.

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High-level synthesis (HLS) is utilized for high-performance and energy-efficient heterogeneous systems designing. HLS is assist in field-programmable gate array circuits designing where hardware implementations are refined and replaced in target device. However, the power-process-voltage-temperature-delay (PPVTD) variation in VLSI circuits undergoes many problems and reduced the performance. In order to address these problems, C4.5 with eXtreme Gradient Boosting Classification based High Level Synthesis (C4.5-XGBCHLS) Method is designed for afford better runtime adaptability (RA) with minimal error rate. VLSI circuits are designed using the behavioral input and results are measured at running condition. When VLSI circuit’s results get reduced, the language description of the circuit is considered as an input. Then, compilation process convert high level specification into Intermediate Representation (IR) in control/data flow graph (CDFG). CDFG computes data and control dependencies among operations. eXtreme Gradient Boosting (XGBoost) Classifier is exploited in C4.5-XGBCHLS method to classify the error causing functional unit (FU) with minimal error rate. XGBoost Classifier exploited C4.5 decision tree as base classifier to enhance classification of error causing FU in VLSI circuits. After that, FU gets allocated in place of error causing FU from functional library based on the design objectives and PPVTD variations. Finally, operation scheduling and binding process is executed for register transfer level (RTL) generation to form VLSI circuits with improved RA. The simulation results shows that the C4.5-XGBCHLS method enhances the performance of functional unit selection accuracy (FUSA) with minimal error rate (ER) and circuit adaptability time (CAT).

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Chin, Scott Y. L., Clarence S. P. Lee, and Steven J. E. Wilton. "On the Power Dissipation of Embedded Memory Blocks Used to Implement Logic in Field-Programmable Gate Arrays." International Journal of Reconfigurable Computing 2008 (2008): 1–13. http://dx.doi.org/10.1155/2008/751863.

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We investigate the power and energy implications of using embedded FPGA memory blocks to implement logic. Previous studies have shown that this technique provides extremely dense implementations of some types of logic circuits, however, these previous studies did not evaluate the impact on power. In this paper, we measure the effects on power and energy as a function of three architectural parameters: the number of available memory blocks, the size of the memory blocks, and the flexibility of the memory blocks. We show that although embedded memories provide area efficient implementations of many circuits, this technique results in additional power consumption. We also show that blocks containing smaller-memory arrays are more power efficient than those containing large arrays, but for most array sizes, the memory blocks should be as flexible as possible. Finally, we show that by combining physical arrays into larger logical memories, and mapping logic in such a way that some physical arrays can be disabled on each access, can reduce the power consumption penalty. The results were obtained from place and routed circuits using standard experimental physical design tools and a detailed power model. Several results were also verified through current measurements on a 0.13 μm CMOS FPGA.

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Liu, Lijun, Jie Han, Lin Xu, Jianshuo Zhou, Chenyi Zhao, Sujuan Ding, Huiwen Shi, et al. "Aligned, high-density semiconducting carbon nanotube arrays for high-performance electronics." Science 368, no. 6493 (May 21, 2020): 850–56. http://dx.doi.org/10.1126/science.aba5980.

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Single-walled carbon nanotubes (CNTs) may enable the fabrication of integrated circuits smaller than 10 nanometers, but this would require scalable production of dense and electronically pure semiconducting nanotube arrays on wafers. We developed a multiple dispersion and sorting process that resulted in extremely high semiconducting purity and a dimension-limited self-alignment (DLSA) procedure for preparing well-aligned CNT arrays (within alignment of 9 degrees) with a tunable density of 100 to 200 CNTs per micrometer on a 10-centimeter silicon wafer. Top-gate field-effect transistors (FETs) fabricated on the CNT array show better performance than that of commercial silicon metal oxide–semiconductor FETs with similar gate length, in particular an on-state current of 1.3 milliamperes per micrometer and a recorded transconductance of 0.9 millisiemens per micrometer for a power supply of 1 volt, while maintaining a low room-temperature subthreshold swing of <90 millivolts per decade using an ionic-liquid gate. Batch-fabricated top-gate five-stage ring oscillators exhibited a highest maximum oscillating frequency of >8 gigahertz.

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Sotohebo, Takashi, Minoru Watanabe, and Funtinori Kobayashi. "An FPGA Implementation of Finite Physical Quantity Neural Network." Journal of Robotics and Mechatronics 15, no. 2 (April 20, 2003): 136–42. http://dx.doi.org/10.20965/jrm.2003.p0136.

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We propose installing a finite physical quantity neural network model on a high-density field programmable gate array (FPGA) at high speed by reducing multipliers. We could thereby downsize circuits without loss of precision. We evaluated its installation and experimental results for image recognition.

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Trost, Andrej, Andrej Zemva, and Matjaz Verderber. "Prototyping Hardware and Software Environment for Teaching Digital Circuit Design." International Journal of Electrical Engineering & Education 38, no. 4 (October 2001): 368–78. http://dx.doi.org/10.7227/ijeee.38.4.9.

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In the paper, we present our latest achievements and experience in undergraduate teaching of digital circuits, integrated circuits and embedded systems by exploiting our prototyping hardware and software environment. The hardware environment is based on Field Programmable Gate Array (FPGA) modules that provide sufficient flexibility and support a broad scope of digital design applications. In addition, the designed software environment supports user-friendly hardware verification of the logic circuits implemented on the hardware system. We describe some typical applications and student projects implemented on the programmable prototyping system.

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Lin, Y., Fei Li, and Lei He. "Circuits and architectures for field programmable gate array with configurable supply voltage." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13, no. 9 (September 2005): 1035–47. http://dx.doi.org/10.1109/tvlsi.2005.857180.

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Cabrita, Daniel Mealha, and Carlos Raimundo Erig Lima. "A Fast Simulator in FPGA for LUT-Based Combinational Logic Circuits of Arbitrary Topology for Evolutionary Algorithms." Journal of Circuits, Systems and Computers 25, no. 02 (December 23, 2015): 1650009. http://dx.doi.org/10.1142/s0218126616500092.

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Current works on generation of combinational logic circuits (CLC) using evolutionary algorithms (EA) propose solutions using field-programmable gate array (FPGA) to accelerate the process of combinational circuit simulation, a step needed in order to evaluate the level of correctness of each individual circuit. However, the current works fail to separate the two distinct problems: the EA and the circuit simulator. The insistence of treating both problem as a single one results in works that fail to address either properly, restricting solutions to simple circuits and to topologically restrictive circuit simulators, while providing very limited data on the results. In this work, we address the circuit simulator problem exclusively, where we propose an architecture for fast simulation of n-LUT CLC of arbitrary topology. The proposed architecture is modular and makes no assumptions on the specific EA to be used with. We provide detailed performance results for varying circuit dimensions, and those results show that our architecture is able to surpass other works both in terms of performance and topological flexibility.

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Lee, Ju-Ah, Jongwon Yoon, Seungkwon Hwang, Hyunsang Hwang, Jung-Dae Kwon, Seung-Ki Lee, and Yonghun Kim. "Integrated Logic Circuits Based on Wafer-Scale 2D-MoS2 FETs Using Buried-Gate Structures." Nanomaterials 13, no. 21 (October 30, 2023): 2870. http://dx.doi.org/10.3390/nano13212870.

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Two-dimensional (2D) transition-metal dichalcogenides (TMDs) materials, such as molybdenum disulfide (MoS2), stand out due to their atomically thin layered structure and exceptional electrical properties. Consequently, they could potentially become one of the main materials for future integrated high-performance logic circuits. However, the local back-gate-based MoS2 transistors on a silicon substrate can lead to the degradation of electrical characteristics. This degradation is caused by the abnormal effect of gate sidewalls, leading to non-uniform field controllability. Therefore, the buried-gate-based MoS2 transistors where the gate electrodes are embedded into the silicon substrate are fabricated. The several device parameters such as field-effect mobility, on/off current ratio, and breakdown voltage of gate dielectric are dramatically enhanced by field-effect mobility (from 0.166 to 1.08 cm2/V·s), on/off current ratio (from 4.90 × 105 to 1.52 × 107), and breakdown voltage (from 15.73 to 27.48 V) compared with a local back-gate-based MoS2 transistor, respectively. Integrated logic circuits, including inverters, NAND, NOR, AND, and OR gates, were successfully fabricated by 2-inch wafer-scale through the integration of a buried-gate MoS2 transistor array.

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Zheng, Fang Yan, Zi Ran Chen, and Zhi Cheng Yu. "Signal Processing Circuit Design Based on SOPC Technology for the Electric Field Type Time Grating Sensors." Applied Mechanics and Materials 635-637 (September 2014): 755–59. http://dx.doi.org/10.4028/www.scientific.net/amm.635-637.755.

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Signal processing circuits are proposed for the electric field type time grating sensors. The proposed design scheme integrates sampling function and processing function into a signal field programmable gate array (FPGA) based on system on programmable chip (SOPC) technology. Employing NiosII technology and adding self-defined instructions improve data processing speed for time grating sensors. The proposed signal processing circuits are simple and stabile. The proposed signal processing circuits are applied to electric field type linear time grating sensors, the experiments results that the peak-to peak measuring error is 0.3um within 200mm without any corrections.

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Rayudu, Kurada Verra Bhoga Vasantha, Dhananjay Ramachandra Jahagirdar, and Patri Srihari Rao. "Design and testing of systolic array multiplier using fault injecting schemes." Computer Science and Information Technologies 3, no. 1 (March 1, 2022): 1–9. http://dx.doi.org/10.11591/csit.v3i1.p1-9.

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Nowadays low power design circuits are major important for data transmission and processing the information among various system designs. One of the major multipliers used for synchronizing the data transmission is the systolic array multiplier, low power designs are mostly used for increasing the performance and reducing the hardware complexity. Among all the mathematical operations, multiplier plays a major role where it processes more information and with the high complexity of circuit in the existing irreversible design. We develop a systolic array multiplier using reversible gates for low power appliances, faults and coverage of the reversible logic are calculated in this paper. To improvise more, we introduced a reversible logic gate and tested the reversible systolic array multiplier using the fault injection method of built-in self-test block observer (BILBO) in which all corner cases are covered which shows 97% coverage compared with existing designs. Finally, Xilinx ISE 14.7 was used for synthesis and simulation results and compared parameters with existing designs which prove more efficiency.

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Kurada Verra Bhoga Vasantha Rayudu, Dhananjay Ramachandra Jahagirdar, and Patri Srihari Rao. "Design and testing of systolic array multiplier using fault injecting schemes." Computer Science and Information Technologies 3, no. 1 (March 1, 2022): 1–9. http://dx.doi.org/10.11591/csit.v3i1.pp1-9.

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Nowadays low power design circuits are major important for data transmission and processing the information among various system designs. One of the major multipliers used for synchronizing the data transmission is the systolic array multiplier, low power designs are mostly used for increasing the performance and reducing the hardware complexity. Among all the mathematical operations, multiplier plays a major role where it processes more information and with the high complexity of circuit in the existing irreversible design. We develop a systolic array multiplier using reversible gates for low power appliances, faults and coverage of the reversible logic are calculated in this paper. To improvise more, we introduced a reversible logic gate and tested the reversible systolic array multiplier using the fault injection method of built-in self-test block observer (BILBO) in which all corner cases are covered which shows 97% coverage compared with existing designs. Finally, Xilinx ISE 14.7 was used for synthesis and simulation results and compared parameters with existing designs which prove more efficiency.

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Fehr, E. Scott, Stephen A. Szygenda, and Granville E. Ott. "An Integrated Hardware Array for Very High Speed Logic Simulation." VLSI Design 4, no. 2 (January 1, 1996): 107–18. http://dx.doi.org/10.1155/1996/13931.

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A hardware architecture is proposed which allows direct mapping of design simulation topology onto an acceleration platform. In order to clarify architectural principles, the simulation is confined to functional verification of unit delay, binary valued gate level logic designs. Under this approach, a rank ordered design description is executed on a massively parallel processor grid which implements an efficient and direct model of the design, similar to prototyping. Architectural innovation reduces logic complexity and execution time of boolean evaluation and fanout switching circuits, while large scale parallelism is integrated at die level to reduce cost and communication delays. The results of this research form the basis for a multiple order of magnitude improvement in reported state-of-the-art cost-performance merit for hardware gate level simulation accelerators.

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Fan, Shiquan, Peihao Liu, Yongqiang Shi, Shujing Zhao, Chuanyu Han, Junyi Xu, and Guohe Zhang. "Multi-Channel Sensing System Utilizing Mott Memristors for Single-Wire Data Fusion and Back-End Greedy Strategy Data Recovery." Electronics 13, no. 2 (January 13, 2024): 345. http://dx.doi.org/10.3390/electronics13020345.

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This paper presents a novel Mott memristor-based multi-channel sensing system designed for the simultaneous processing of multiple sensing channels, employing single-wire data fusion and a greedy search strategy for back-end data recovery. Multiple channels of external stimulus information are simultaneously encoded into analog signals with varying frequencies, utilizing a Mott memristor array. Auxiliary circuits then convert the analog sensing signals into square wave signals which are further transformed into narrow (100 ns) pulse signals through pulse generation circuitry. Subsequently, these narrow pulse signals are fused into a single-wire signal by using an OR gate. At the back-end of the system, a greedy searching strategy is applied to accurately identify all frequencies within the fused pulse signal, enabling seamless analog-to-frequency conversion across multiple channels. The system is suitable for a wide range of sensors and can be directly connected to FPGAs for data processing, eliminating the need for traditional analogue front-end and ADC circuits and greatly reducing circuit complexity and power consumption. By leveraging the innovative capabilities of Mott memristors, the proposed system achieves precise analog-to-frequency conversion with significantly reduced power consumption.

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Tung, Dam Minh, Nguyen Van Toan, and Jeong-Gun Lee. "A One-Cycle Correction Error-Resilient Flip-Flop for Variation-Tolerant Designs on an FPGA." Electronics 9, no. 4 (April 10, 2020): 633. http://dx.doi.org/10.3390/electronics9040633.

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Timing error resilience (TER) is one of the most promising approaches for eliminating design margins that are required due to process, voltage, and temperature (PVT) variations. However, traditional TER circuits have been designed typically on an application-specific integrated circuits (ASIC) where customized circuits and metastability detector designs at a transistor level are possible. On the other hand, it is difficult to implement those designs on a field-programmable gate array (FPGA) due to its predefined LUT structure and irregular wiring. In this paper, we propose an error detection and correction flip-flop (EDACFF) on an FPGA chip, where the metastability issue can be resolved by imposing proper timing constraints on the circuit structures. The proposed EDACFF exploits a transition detector for detecting a timing error along with a data correction latch for correcting the error with one-cycle performance penalty. Our proposed EDACFF is implemented in a 3-bit counter circuit employing a 5-stage pipeline on a Spartan-6 FPGA device (the XFC6SLX45) to verify the functional and timing behavior. The measurement results show that the proposed design obtains 32% less power consumption and 42% higher performance compared to a traditional worst-case design.

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Pfänder, O. A., R. Nopper, H. J. Pfleiderer, S. Zhou, and A. Bermak. "Comparison of reconfigurable structures for flexible word-length multiplication." Advances in Radio Science 6 (May 26, 2008): 113–18. http://dx.doi.org/10.5194/ars-6-113-2008.

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Abstract. Binary multiplication continues to be one of the essential arithmetic operations in digital circuits. Even though field-programmable gate arrays (FPGAs) are becoming more and more powerful these days, the vendors cannot avoid implementing multiplications with high word-lengths using embedded blocks instead of configurable logic. But on the other hand, the circuit's efficiency decreases if the provided word-length of the hard-wired multipliers exceeds the precision requirements of the algorithm mapped into the FPGA. Thus it is beneficial to use multiplier blocks with configurable word-length, optimized for area, speed and power dissipation, e.g. regarding digital signal processing (DSP) applications. In this contribution, we present different approaches and structures for the realization of a multiplication with variable precision and perform an objective comparison. This includes one approach based on a modified Baugh and Wooley algorithm and three structures using Booth's arithmetic operand recoding with different array structures. All modules have the option to compute signed two's complement fix-point numbers either as an individual computing unit or interconnected to a superior array. Therefore, a high throughput at low precision through parallelism, or a high precision through concatenation can be achieved.

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Okuno, Hirotsugu, and Tetsuya Yagi. "Bio-Inspired Real-Time Robot Vision for Collision Avoidance." Journal of Robotics and Mechatronics 20, no. 1 (February 20, 2008): 68–74. http://dx.doi.org/10.20965/jrm.2008.p0068.

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A mixed analog-digital integrated vision sensor was designed to detect an approaching object in real-time. To respond selectively to approaching stimuli, the sensor employed an algorithm inspired by the visual nervous system of a locust, which can avoid collisions robustly by using visual information. An electronic circuit model was designed to mimic the architecture of the locust nervous system. Computer simulations showed that the model provided appropriate responses for collision avoidance. We implemented the model with a compact hardware system consisting of a silicon retina and field-programmable gate array (FPGA) circuits; the system was confirmed to respond selectively to approaching stimuli that constituted a collision threat.

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Takahashi, T., M. Uchida, T. Takahashi, R. Yoshino, M. Yamamoto, and N. Kitamura. "A CMOS gate array with 600 Mb/s simultaneous bidirectional I/O circuits." IEEE Journal of Solid-State Circuits 30, no. 12 (1995): 1544–46. http://dx.doi.org/10.1109/4.482204.

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Saleh, Adham Hadi, Hayder Khaleel AL-Qaysi, Khalid Awaad Humood, and Tahreer Mahmood. "Design of CRC circuit for 5G system using VHDL." Bulletin of Electrical Engineering and Informatics 12, no. 4 (August 1, 2023): 2125–35. http://dx.doi.org/10.11591/beei.v12i4.4598.

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In this document, we focus on how to design cyclic redundancy check (CRC) circuits with different 5G polynomial divisor using very high-speed integrated circuit (VHSIC) hardware description language (VHDL) to integrate in field-programmable gate array (FPGA) suitable kit using a suitable design code. The different between designed circuits came from the different of data size according to polynomials requirements conditions since there are huge data size in 5G system that required divide it with suitable method and then implemented the required circuit. CRC code as a polar code and short low density parity check (LDPC) is proposed in 5G new radio (NR) systems, CRC properties to divided data and CRC cod make it particularly very useful for codes with higher data rate and longer lengths, and for codes with low data rates and small length as an error detection method. The CRC encoder circuit (transmitter side) and CRC decoder circuit (receiver side) with different polynomial and data size have been designed using VHDL. Xilinx ISE 14.3 simulator, where the test bench simulation results give the expected simulator results of proposed decoding circuit scheme so to integrated using ZYNQ FPGA kit.

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Saleh, Adham Hadi, Hayder Khaleel AL-Qaysi, Khalid Awaad Humood, and Tahreer Mahmood. "Design of CRC circuit for 5G system using VHDL." Bulletin of Electrical Engineering and Informatics 12, no. 4 (August 1, 2023): 2125–35. http://dx.doi.org/10.11591/eei.v12i4.4598.

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In this document, we focus on how to design cyclic redundancy check (CRC) circuits with different 5G polynomial divisor using very high-speed integrated circuit (VHSIC) hardware description language (VHDL) to integrate in field-programmable gate array (FPGA) suitable kit using a suitable design code. The different between designed circuits came from the different of data size according to polynomials requirements conditions since there are huge data size in 5G system that required divide it with suitable method and then implemented the required circuit. CRC code as a polar code and short low density parity check (LDPC) is proposed in 5G new radio (NR) systems, CRC properties to divided data and CRC cod make it particularly very useful for codes with higher data rate and longer lengths, and for codes with low data rates and small length as an error detection method. The CRC encoder circuit (transmitter side) and CRC decoder circuit (receiver side) with different polynomial and data size have been designed using VHDL. Xilinx ISE 14.3 simulator, where the test bench simulation results give the expected simulator results of proposed decoding circuit scheme so to integrated using ZYNQ FPGA kit.

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Bibilo, P. N. "Synthesis of Modular Multipliers." Programmnaya Ingeneria 14, no. 8 (August 14, 2023): 377–87. http://dx.doi.org/10.17587/prin.14.377-387.

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The results of experiments on the circuit implementation of modular multipliers in the design library of ASIC (Application-Specific Integrated Circuits) and FPGA (Field-Programmable Gate Array) are presented. The initial descriptions of modular multiplier projects were given by systems of not fully defined (partial) Boolean functions and algorithmic VHDL descriptions. Logical optimization was carried out in the class of disjunctive normal forms (DNF) and representations of Boolean function systems by BDD (Binary Decision Diagrams). The synthesized circuits were evaluated by area and time delay. It is established that the use of partial Boolean function models and preliminary logical BDD optimization allows one to improve the parameters of synthesized ASIC and FPGA blocks for small module values, however, the best solutions for large module values can be obtained using algorithmic VHDL descriptions of modular multipliers. In the synthesis of modular multiplier circuits as part of an FPGA and the use of ISE and Vivado design systems it is advisable to use synthesized VHDL operations (a*b) mod p.

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Sheng, Duo, Hsin-Ting Lee, and Fu-Chi Huang. "All-digital transmit beamformer for portable high-frequency ultrasound imaging systems." Review of Scientific Instruments 94, no. 3 (March 1, 2023): 034707. http://dx.doi.org/10.1063/5.0128410.

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To meet the requirements of high-frequency ultrasound imaging systems, a transmit-beamforming integrated circuit with higher delay resolution than conventional transmit-beamforming circuits, which are typically implemented using field-programmable gate array chips, is presented. It also requires smaller volumes, allowing for portable applications. Its proposed design includes two all-digital delay-locked loops providing a specified digital control code for a counter-based beamforming delay chain (CBDC) to generate stable and suitable delays for exciting the array transducer elements without variations in process, voltage, and temperature. Moreover, to maintain the duty cycle of long propagation signals, this novel CBDC requires only a few delay cells, significantly reducing hardware costs and power consumption. Simulations were conducted, revealing a maximum time delay of 451.9 ns with a time resolution of 652 ps and a maximum lateral resolution error of 0.04 mm at 6.8 mm.

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Hidalgo-López, José A., Óscar Oballe-Peinado, Julián Castellanos-Ramos, and José A. Sánchez-Durán. "Two-Capacitor Direct Interface Circuit for Resistive Sensor Measurements." Sensors 21, no. 4 (February 22, 2021): 1524. http://dx.doi.org/10.3390/s21041524.

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Direct interface circuits (DICs) avoid the need for signal conditioning circuits and analog-to-digital converters (ADCs) to obtain digital measurements of resistive sensors using only a few passive elements. However, such simple hardware can lead to quantization errors when measuring small resistance values as well as high measurement times and uncertainties for high resistances. Different solutions to some of these problems have been presented in the literature over recent years, although the increased uncertainty in measurements at higher resistance values is a problem that has remained unaddressed. This article presents an economical hardware solution that only requires an extra capacitor to reduce this problem. The circuit is implemented with a field-programmable gate array (FPGA) as a programmable digital device. The new proposal significantly reduces the uncertainty in the time measurements. As a result, the high resistance errors decreased by up to 90%. The circuit requires three capacitor discharge cycles, as is needed in a classic DIC. Therefore, the time to estimate resistance increases slightly, between 2.7% and 4.6%.

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Yoshikawa, Masaya, Yusuke Mori, and Takeshi Kumaki. "Implementation Aware Hardware Trojan Trigger." Advanced Materials Research 933 (May 2014): 482–86. http://dx.doi.org/10.4028/www.scientific.net/amr.933.482.

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Recently, the threat of hardware Trojans has garnered attention. Hardware Trojans are malicious circuits that are incorporated into large-scale integrations (LSIs) during the manufacturing process. When predetermined conditions specified by an attacker are satisfied, the hardware Trojan is triggered and performs subversive activities without the LSI users even being aware of these activities. In previous studies, a hardware Trojan was incorporated into a cryptographic circuit to estimate confidential information. However, Trojan triggers have seldom been studied. The present study develops several new Trojan triggers and each of them is embedded in a field-programmable gate array (FPGA). Subsequently, the ease of detection of each trigger is verified from the standpoint of area.

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Liu, Yixuan, Qiao Hu, Qiqiao Wu, Xuanzhi Liu, Yulin Zhao, Donglin Zhang, Zhongze Han, et al. "Probabilistic Circuit Implementation Based on P-Bits Using the Intrinsic Random Property of RRAM and P-Bit Multiplexing Strategy." Micromachines 13, no. 6 (June 10, 2022): 924. http://dx.doi.org/10.3390/mi13060924.

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Probabilistic computing is an emerging computational paradigm that uses probabilistic circuits to efficiently solve optimization problems such as invertible logic, where traditional digital computations are difficult to solve. This paper proposes a true random number generator (TRNG) based on resistive random-access memory (RRAM), which is combined with an activation function implemented by a piecewise linear function to form a standard p-bit cell, one of the most important parts of a p-circuit. A p-bit multiplexing strategy is also applied to reduce the number of p-bits and improve resource utilization. To verify the superiority of the proposed probabilistic circuit, we implement the invertible p-circuit on a field-programmable gate array (FPGA), including AND gates, full adders, multi-bit adders, and multipliers. The results of the FPGA implementation show that our approach can significantly save the consumption of hardware resources.

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Sun, Jun-Wei, Xing-Tong Zhao, and Yan-Feng Wang. "Multi-Input Look-Up-Table Design Based on Nanometer Memristor." Journal of Nanoelectronics and Optoelectronics 15, no. 1 (January 1, 2020): 113–21. http://dx.doi.org/10.1166/jno.2020.2721.

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The logic blocks of Field Programmable Gate Array (FPGA) basic unit are mainly composed of Look-Up-Tables (LUTs). The traditional LUTs use the static random access memory (SRAM), which causes FPGA reach the limitation in term of the density, speed, and configuration overhead. In this paper, a novel nanometer memristor-based LUT (NMLUT) is composed of memristors, MOS field effect transistors, decoders, resistors. A three-input NMLUT and a four-input NMLUT circuits are investigated. Moreover, an adder is used to verify the practicality of NMLUT circuit. The proposed NMLUT circuit can implement some combinational logic functions through specific configuration and it is better in data transmission and data storage than the traditional LUT. Since NMLUT circuit is compatible with the mainstream circuit in the FPGA, it can effectively solve the limitations of the field FPGA. The correctness of the results is verified in PSPICE software.

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Cheng, Shi, JinBao Zhang, Zhan Gao, and Jiehua Wang. "Circuit Implementation of Respiratory Information Extracted from Electrocardiograms." Journal of Database Management 33, no. 2 (April 1, 2022): 1–12. http://dx.doi.org/10.4018/jdm.314211.

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Breathing is an important physiological process in the human body. The wavelet transform method can extract respiratory information from electrocardiogram (ECG) data; thus, the authors designed an integrated circuit of ECG-derived respiration (EDR). They propose a discrete wavelet transform (DWT) EDR algorithm based on an analysis of the heartbeat frequency and respiration. They verified the algorithm in both the time domain and the frequency domain using Matlab. Next, the DWT EDR digital circuit was designed using the QUARTUS program. Finally, they used a field programmable gate array (FPGA) for downloading and simulation, and they verified the designed circuits using a logic analyzer, where they compared the waveform of the data obtained from the EDR circuit with the waveform obtained after processing the wavelet transform EDR in Matlab. The experimental results showed that the circuit can allow the extraction of respiratory information from ECG data.

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Liu, Meng, Yunfei Wang, and Shuai Li. "A Field Programmable Gate Array Placement Methodology for Netlist-Level Circuits with GPU Acceleration." Electronics 13, no. 1 (December 20, 2023): 37. http://dx.doi.org/10.3390/electronics13010037.

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Field Programmable Gate Arrays (FPGAs), renowned for their reconfigurable nature, offer unmatched flexibility and cost-effectiveness in engineering experimentation. They stand as the quintessential platform for hardware acceleration and prototype validation. With the increasing ubiquity of FPGA chips and the escalating scale of system designs, the significance of their accompanying Electronic Design Automation (EDA) tools has never been more pronounced. The placement process, serving as the linchpin in FPGA EDA, directly influences FPGA development and operational efficiency. This paper introduces an FPGA placement methodology hinging on the Verilog-to-Routing (VTR) framework. We introduce a novel packing approach grounded in the weighted Edmonds’ Blossom algorithm, ensuring that the CLB generation strategy aligns more closely with load-balanced distribution. Furthermore, we enhanced the electric field-driven resolver placement process for CLB locations and leverage GPU-accelerated design. Experimental results demonstrate substantial improvements over the traditional VTR algorithm, with an average optimization of 28.42% in the packing process runtime, an average acceleration ratio of 2.85 times in the placement phase, and a 39.97% reduction in total packing and placement runtime consumption.

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Poghossian, Arshak, Rene Welden, Vahe V. Buniatyan, and Michael J. Schöning. "An Array of On-Chip Integrated, Individually Addressable Capacitive Field-Effect Sensors with Control Gate: Design and Modelling." Sensors 21, no. 18 (September 14, 2021): 6161. http://dx.doi.org/10.3390/s21186161.

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The on-chip integration of multiple biochemical sensors based on field-effect electrolyte-insulator-semiconductor capacitors (EISCAP) is challenging due to technological difficulties in realization of electrically isolated EISCAPs on the same Si chip. In this work, we present a new simple design for an array of on-chip integrated, individually electrically addressable EISCAPs with an additional control gate (CG-EISCAP). The existence of the CG enables an addressable activation or deactivation of on-chip integrated individual CG-EISCAPs by simple electrical switching the CG of each sensor in various setups, and makes the new design capable for multianalyte detection without cross-talk effects between the sensors in the array. The new designed CG-EISCAP chip was modelled in so-called floating/short-circuited and floating/capacitively-coupled setups, and the corresponding electrical equivalent circuits were developed. In addition, the capacitance-voltage curves of the CG-EISCAP chip in different setups were simulated and compared with that of a single EISCAP sensor. Moreover, the sensitivity of the CG-EISCAP chip to surface potential changes induced by biochemical reactions was simulated and an impact of different parameters, such as gate voltage, insulator thickness and doping concentration in Si, on the sensitivity has been discussed.

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Xu, Peilong, Dan Lan, Fengyun Wang, and Incheol Shin. "In-Memory Computing Integrated Structure Circuit Based on Nonvolatile Flash Memory Unit." Electronics 12, no. 14 (July 20, 2023): 3155. http://dx.doi.org/10.3390/electronics12143155.

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Artificial intelligence has made people’s demands for computer computing efficiency increasingly high. The traditional hardware circuit simulation method for neural morphology computation has problems of unstable performance and excessive power consumption. This research will use non-volatile flash memory cells that are easy to read and write to build a convolutional neural network structure to improve the performance of neural morphological computing. In the experiment, floating-gate transistors were used to simulate neural network synapses to design core cross-array circuits. A voltage subtractor, voltage follower and ReLU activation function are designed based on a differential amplifier. An Iris dataset was introduced in this experiment to conduct simulation experiments on the research circuit. The IMC circuit designed for this experiment has high performance, with an accuracy rate of 96.2% and a recall rate of 60.2%. The overall current power consumption of the hardware circuit is small, and the current power consumption of the subtractor circuit and ReLU circuit does not exceed 100 µA, while the power consumption of the negative feedback circuit is about 440 mA. The accuracy of analog circuits under the IMC architecture is above 93%, the energy consumption is only about 360 nJ, and the recognition rate is about 12 μs. Compared with the classic von Neumann architecture, it reduces the circuit recognition rate and power consumption while meeting accuracy requirements.

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Shi, Runxiao, Tengteng Lei, Zhihe Xia, and Man Wong. "Low-temperature metal–oxide thin-film transistor technologies for implementing flexible electronic circuits and systems." Journal of Semiconductors 44, no. 9 (September 1, 2023): 091601. http://dx.doi.org/10.1088/1674-4926/44/9/091601.

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Abstract Here we review two 300 °C metal–oxide (MO) thin-film transistor (TFT) technologies for the implementation of flexible electronic circuits and systems. Fluorination-enhanced TFTs for suppressing the variation and shift of turn-on voltage (V ON), and dual-gate TFTs for acquiring sensor signals and modulating V ON have been deployed to improve the robustness and performance of the systems in which they are deployed. Digital circuit building blocks based on fluorinated TFTs have been designed, fabricated, and characterized, which demonstrate the utility of the proposed low-temperature TFT technologies for implementing flexible electronic systems. The construction and characterization of an analog front-end system for the acquisition of bio-potential signals and an active-matrix sensor array for the acquisition of tactile images have been reported recently.

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Salauyou, Valery, and Witali Bułatow. "Optimized Sequential State Encoding Methods for Finite-State Machines in Field-Programmable Gate Array Implementations." Applied Sciences 14, no. 13 (June 27, 2024): 5594. http://dx.doi.org/10.3390/app14135594.

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A Finite-State Machine (FSM) model is frequently employed to represent the behavior of sequential circuits. In the optimal design of these circuits, it is crucial to enhance FSM characteristics such as area (implementation cost), performance (operating frequency), and power consumption. This paper proposes sequential state encoding methods that aim to reduce the area and enhance the performance of FSMs. The methods involve sequentially selecting FSM states for encoding and determining the most appropriate code for each selected state. Several state and code selection modes are introduced, allowing for consideration of the relationships between states, the number of incoming and outgoing transitions, and the number of input variables initiating transitions to each state. The code selection process takes into account the architectural features of the electronic device in which the FSM is implemented, while some code selection modes are introduced to optimize both the area and performance of the FSM. The experimental results demonstrate that the proposed approach yields, on average, a reduction in the FSM area by 19.7% (in some instances, up to twofold reduction), along with an average performance increase of 21.2% (in certain cases, up to 69.3%), compared to the Sequential mode of the Quartus system.

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Mayacela, Margarita, Leonardo Rentería, Luis Contreras, and Santiago Medina. "Comparative Analysis of Reconfigurable Platforms for Memristor Emulation." Materials 15, no. 13 (June 25, 2022): 4487. http://dx.doi.org/10.3390/ma15134487.

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The memristor is the fourth fundamental element in the electronic circuit field, whose memory and resistance properties make it unique. Although there are no electronic solutions based on the memristor, interest in application development has increased significantly. Nevertheless, there are only numerical Matlab or Spice models that can be used for simulating memristor systems, and designing is limited to using memristor emulators only. A memristor emulator is an electronic circuit that mimics a memristor. In this way, a research approach is to build discrete-component emulators of memristors for its study without using the actual models. In this work, two reconfigurable hardware architectures have been proposed for use in the prototyping of a non-linearity memristor emulator: the FPAA (Field Programing Analog Arrays) and the FPGA (Field Programming Gate Array). The easy programming and reprogramming of the first architecture and the performance, high area density, and parallelism of the second one allow the implementation of this type of system. In addition, a detailed comparison is shown to underline the main differences between the two approaches. These platforms could be used in more complex analog and/or digital systems, such as neural networks, CNN, digital circuits, etc.

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Qin, Xing, Chaojie Li, Haitao He, Zejun Pan, and Chenxiao Lai. "Python-Based Circuit Design for Fundamental Building Blocks of Spiking Neural Network." Electronics 12, no. 11 (May 23, 2023): 2351. http://dx.doi.org/10.3390/electronics12112351.

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Spiking neural networks (SNNs) are considered a crucial research direction to address the “storage wall” and “power wall” challenges faced by traditional artificial intelligence computing. However, developing SNN chips based on CMOS (complementary metal oxide semiconductor) circuits remains a challenge. Although memristor process technology is the best alternative to synapses, it is still undergoing refinement. In this study, a novel approach is proposed that employs tools to automatically generate HDL (hardware description language) code for constructing neuron and memristor circuits after using Python to describe the neuron and memristor models. Based on this approach, HR (Hindmash–Rose), LIF (leaky integrate-and-fire), and IZ (Izhikevich) neuron circuits, as well as HP, EG (enhanced generalized), and TB (the behavioral threshold bipolar) memristor circuits are designed to construct the most basic connection of a SNN: the neuron–memristor–neuron circuit that satisfies the STDP (spike-timing-dependent-plasticity) learning rule. Through simulation experiments and FPGA (field programmable gate array) prototype verification, it is confirmed that the IZ and LIF circuits are suitable as neurons in SNNs, while the X variables of the EG memristor model serve as characteristic synaptic weights. The EG memristor circuits best satisfy the STDP learning rule and are suitable as synapses in SNNs. In comparison to previous works on hardware spiking neurons, the proposed method needed fewer area resources for creating spiking neurons models on FPGA. The proposed SNN basic components design method, and the resulting circuits, are beneficial for architectural exploration and hardware–software co-design of SNN chips.

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Miura, Yuto, Hiroki Nishikawa, Xiangbo Kong, and Hiroyuki Tomiyama. "Timing issues on power side-channel leakage of advanced encryption standard circuits designed by high-level synthesis." International Journal of Reconfigurable and Embedded Systems (IJRES) 13, no. 3 (November 1, 2024): 616. http://dx.doi.org/10.11591/ijres.v13.i3.pp616-624.

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In recent years, field programmable gate array (FPGA) have been used in many internet of things (IoT) devices and are equipped with cryptographic circuits to ensure security. However, they are exposed to the risk of cryptographic keys being stolen by side-channel attacks. Countermeasures against side-channel attacks have been developed, but they are becoming more of a threat to IoT devices due to the diversity of attacks. Therefore, it is necessary to understand the basic characteristics of side-channel attacks. Therefore, this study clarifies the relationship between two timing issues, the clock period of the circuit and the power sampling interval, and the amount of side-channel leakage. We design seven advanced encryption standard (AES) circuits with different clock periods and conduct empirical experiments using logic simulations to clarify the correlation between the two timings and the amount of side-channel leakage. T-test is used to evaluate the leakage amount, which is evaluated based on four metrics. From the results, we argue that the clock period and sampling interval do not interfere with each other in the side-channel leakage amount.

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Bravaix, A., G. Hamparsoumian, J. Sonzogni, H. Pitard, T. Garba-Seybou, E. Kussener, X. Federspiel, and F. Cacho. "CMOS Scaling Challenges for High Performance and Low Power applications facing Reliability Criteria towards the Decananometer range." Journal of Physics: Conference Series 2548, no. 1 (July 1, 2023): 012003. http://dx.doi.org/10.1088/1742-6596/2548/1/012003.

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Abstract The huge improvements in integrated circuits manufacturing has faced great challenges between process optimization, performance requirements and the trade-off between low power operation and reliability for long term use. Both the variability at time zero and the time variability due to external constraints and aging phenomena make mandatory the validation of the CMOS technology nodes from device to circuits and products under operation. While High-K Metal-Gate (HKMG) offered good compromises down to 28nm gate-length, the move to Fully Depleted Silicon on Insulator (FDSOI) allows to further scale the dimension down to 14nm effective gate-length with ultra-thin equivalent gate-oxide thickness (EOT) of 1.35 nm. This has been obtained guarantying a small subthreshold slope for switching, small drain-induced barrier lowering (DIBL) for limited short-channel effect (SCE) and excellent current drivability thanks to a proper gate-stack with HfO2/SiON optimization and adapted rapid thermal processing and annealing. We give new insights to determine first the performance with temperature, the process variability impact at time zero and the robustness of CMOS nodes submitted to interface traps, oxide charge and recoverable traps. Their role is analysed using accelerated DC and AC experiments in devices to SRAM cell and array, focusing on the balance between hot-carrier and bias temperature damage. This allows to guaranty the technology robustness, speed performance and limited power consumption for product qualification.

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Żbik, Mateusz, and Piotr Wieczorek. "Charge-Line Dual-FET High-Repetition-Rate Pulsed Laser Driver." Applied Sciences 9, no. 7 (March 27, 2019): 1289. http://dx.doi.org/10.3390/app9071289.

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Most modern pulsed laser systems require versatile laser diode drivers. A state-of-the-art pulsed laser driver should provide precise peak power regulation, high repetition rate, and pulse duration control. A new, charge line dual-FET transistor circuit structure was developed to provide all these features. The pulsed modulation current is adjustable up to Imax = 1.2 A, with the laser diode forward voltage acceptable up to UF max = 20 V. The maximum repetition rate is limited by a charge line circuit to frep max = 20 MHz. Compared to the conventional single transistor drivers, the solution proposed in this paper allows a precise, high resolution width regulation to be obtained, whereas a low pulse jitter is ensured. In the solution, two separate, out-of-phase signals are used to trigger the individual Field Effect Transistors (FET). The resultant pulsed modulation current full-width-at-half-maxima (FWHM) is regulated from ~200 ps up to 2 ns. All control and timing signals are generated with a popular Field-Programmable Gate Array (FPGA) digital circuitry. The use of standard FPGA devices ensures the low cost and high reliability of the circuit, which are not available in laser drivers consisting of sophisticated analogue adjustable delay circuits.

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