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Auswahl der wissenschaftlichen Literatur zum Thema „Hardware Construction Languages (HCLs)“
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Zeitschriftenartikel zum Thema "Hardware Construction Languages (HCLs)"
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Kamkin, Alexander Sergeevich, Mikhail Mikhaylovich Chupilko, Mikhail Sergeevich Lebedev, Sergey Aleksandrovich Smolov, and Georgi Gaydadjiev. "Comparison of High-Level Synthesis and Hardware Construction Tools." Proceedings of the Institute for System Programming of the RAS 34, no. 5 (2022): 7–22. http://dx.doi.org/10.15514/ispras-2022-34(5)-1.
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Application-specific systems with FPGA accelerators are often designed using high-level synthesis or hardware construction tools. Nowadays, there are many frameworks available, both open-source and commercial. In this work, we attempt to fairly compare several existing solutions (languages and tools), including Verilog (our baseline), Chisel, Bluespec SystemVerilog (Bluespec Compiler), DSLX (XLS), MaxJ (MaxCompiler), and C (Bambu and Vivado HLS). Our analysis has been carried out using a representative example of 8×8 inverse discrete cosine transform (IDCT), a widely used algorithm engaged in, among others, JPEG and MPEG decoders. The metrics under consideration include: (a) the degree of automation (how much less code is required compared to Verilog), (b) the controllability (possibility to achieve given design characteristics, namely a given ratio of the performance and area), and (c) the flexibility (ease of design modification to achieve certain characteristics). Rather than focusing on computational kernels only, we have developed AXI-Stream wrappers for the synthesized implementations, which allows adequately evaluating characteristics of the designs when they are used as parts of real computer systems. Our study shows clear examples of what impact specific optimizations (tool settings and source code modifications) have on the overall system performance and area. It emphasizes how important is to be able to control the balance between the communication interface utilization and the computational kernel performance and delivers clear guidelines for the next generation tools for designing FPGA accelerator based systems.
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Заризенко, Инна Николаевна, та Артём Евгеньевич Перепелицын. "АНАЛИЗ СРЕДСТВ И ТЕХНОЛОГИЙ РАЗРАБОТКИ FPGA КАК СЕРВИС". RADIOELECTRONIC AND COMPUTER SYSTEMS, № 4 (25 грудня 2019): 88–93. http://dx.doi.org/10.32620/reks.2019.4.10.
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This article has analyzed the most effective integrated development environments from leading programmable logical device (PLD) manufacturers. Heterogeneous calculations and the applicability of a general approach to the description of hardware accelerator designs are considered. An analytical review of the use of the OpenCL language in the construction of high-performance FPGA-based solutions is performed. The features of OpenCL language usage for heterogeneous computing for FPGA-based accelerators are discussed. The experience of a unified description of projects for solutions based on CPU, GPU, signal processors and FPGA is analyzed. The advantages of using such a description for tasks that perform parallel processing are shown. Differences in productivity and labor costs for developing FPHA systems with parallel data processing for hardware description languages and OpenCL language are shown. The results of comparing commercially available solutions for building services with FPGA accelerators are presented. The advantages of the Xilinx platform and tools for building an FPGA service are discussed. The stages of creating solutions based on FaaS are proposed. Some FaaS related tasks are listed and development trends are discussed. The SDAccel platform of the Xilinx SDx family is considered, as well as the possible role of these tools in creating the FPGA computing platform as a service. An example of using SDAccel to develop parallel processing based on FPGA is given. The advantages and disadvantages of the use of hardware description languages with such design automation tools are discussed. The results of comparing the performance of the simulation speed of the system described with the use of programming languages and hardware description languages are presented. The advantages of modeling complex systems are discussed, especially for testing solutions involving the processing of tens of gigabytes of data and the impossibility of creating truncated test sets. Based on practical experience, the characteristics of development environments, including undocumented ones, are formulated.
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Kohen, Hanan, and Dov Dori. "Improving Conceptual Modeling with Object-Process Methodology Stereotypes." Applied Sciences 11, no. 5 (2021): 2301. http://dx.doi.org/10.3390/app11052301.
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As system complexity is on the rise, there is a growing need for standardized building blocks to increase the likelihood of systems’ success. Conceptual modeling is the primary activity required for engineering systems to be understood, designed, and managed. Modern modeling languages enable describing the requirements and design of systems in a formal yet understandable way. These languages use stereotypes to standardize, clarify the model semantics, and extend the meaning of model elements. An Internet of things (IoT) system serves as an example to show the significant contributions of stereotypes to model construction, comprehension, error reduction, and increased productivity during design, simulation, and combined hardware–software system execution. This research emphasizes stereotype features that are unique to Object-Process Methodology (OPM) ISO 19450, differentiating it from stereotypes in other conceptual modeling languages. We present the implementation of stereotypes in OPCloud, an OPM modeling software environment, explore stereotype-related problems, propose solutions, and discuss future enhancements.
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Keller, Damián, Aman Jagwani, and Victor Lazzarini. "The Ubimus Plugging Framework: Deploying FPGA-Based Prototypes for Ubiquitous Music Hardware Design." Computers 14, no. 4 (2025): 155. https://doi.org/10.3390/computers14040155.
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The emergent field of embedded computing presents a challenging scenario for ubiquitous music (ubimus) design. Available tools demand specific technical knowledge—as exemplified in the techniques involved in programming integrated circuits of configurable logic units, known as field-programmable gate arrays (FPGAs). Low-level hardware description languages used for handling FPGAs involve a steep learning curve. Hence, FPGA programming offers a unique challenge to probe the boundaries of ubimus frameworks as enablers of fast and versatile prototyping. State-of-the-art hardware-oriented approaches point to the use of high-level synthesis as a promising programming technique. Furthermore, current FPGA system-on-chip (SoC) hardware with an associated onboard general-purpose processor may foster the development of flexible platforms for musical signal processing. Taking into account the emergence of an FPGA-based ecology of tools, we introduce the ubimus plugging framework. The procedures employed in the construction of a modular- synthesis library based on field-programmable gate array hardware, ModFPGA, are documented, and examples of musical projects applying key design principles are discussed.
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Giraldo, Carlos Alberto, Beatriz Florian-Gaviria, Eval Bladimir Bacca-Cortés, Felipe Gómez, and Francisco Muñoz. "A programming environment having three levels of complexity for mobile robotics." Ingeniería e Investigación 32, no. 3 (2012): 76–82. http://dx.doi.org/10.15446/ing.investig.v32n3.35947.
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This paper presents a programming environment for supporting learning in STEM, particularly mobile robotic learning. It was designed to maintain progressive learning for people with and without previous knowledge of programming and/or robotics. The environment was multi-platform and built with open source tools. Perception, mobility, communication, navigation and collaborative behaviour functionalities can be programmed for different mobile robots. A learner is able to programme robots using different programming languages and editor interfaces: graphic programming interface (basic level), XML-based meta-language (intermediate level) or ANSI C language (advanced level). The environment supports programme translation transparently into different languages for learners or explicitly on learners' demand. Learners can access proposed challenges and learning interfaces by examples. The environment was designed to allow characteristics such as extensibility, adaptive interfaces, persistence and low software/hardware coupling. Functionality tests were performed to prove programming environment specifications. UV-BOT mobile robots were used in these tests.
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Zielenkiewicz, Maciej, and Aleksy Schubert. "Automata theory approach to predicate intuitionistic logic." Journal of Logic and Computation 32, no. 3 (2021): 554–80. http://dx.doi.org/10.1093/logcom/exab069.
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Abstract Predicate intuitionistic logic is a well-established fragment of dependent types. Proof construction in this logic, as the Curry–Howard isomorphism states, is the process of program synthesis. We present automata that can handle proof construction and program synthesis in full intuitionistic first-order logic. Given a formula, we can construct an automaton such that the formula is provable if and only if the automaton has an accepting run. As further research, this construction makes it possible to discuss formal languages of proofs or programs, the closure properties of the automata and their connections with the traditional logical connectives.
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Akay, Abdullah E., and John Sessions. "Applying the Decision Support System, TRACER, to Forest Road Design." Western Journal of Applied Forestry 20, no. 3 (2005): 184–91. http://dx.doi.org/10.1093/wjaf/20.3.184.
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Abstract A three-dimensional forest road alignment model, TRACER, was developed to assist a forest road designer with rapid evaluation of alternative road paths. The objective is to design a route with the lowest total cost considering construction, maintenance, and transportation costs, while conforming to design specifications, environmental requirements, and driver safety. The model integrates two optimization techniques: a linear programming for earthwork allocation and a heuristic approach for vertical alignment selection. The model enhances user efficiency through automated horizontal and vertical curve fitting routines, cross-section generation, and cost routines for construction, maintenance, and vehicle use. The average sediment delivered to a stream from the road section is estimated using the method of a GIS-based road erosion/delivery model. It is anticipated that the development of a design procedure incorporating modern graphics capability, hardware, software languages, modern optimization techniques, and environmental considerations will improve the design process for forest roads. West. J. Appl. For. 20(3):184–191.
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Popescu, Natalie, Ziyang Xu, Sotiris Apostolakis, David I. August, and Amit Levy. "Safer at any speed: automatic context-aware safety enhancement for Rust." Proceedings of the ACM on Programming Languages 5, OOPSLA (2021): 1–23. http://dx.doi.org/10.1145/3485480.
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Type-safe languages improve application safety by eliminating whole classes of vulnerabilities–such as buffer overflows–by construction. However, this safety sometimes comes with a performance cost. As a result, many modern type-safe languages provide escape hatches that allow developers to manually bypass them. The relative value of performance to safety and the degree of performance obtained depends upon the application context, including user goals and the hardware upon which the application is to be executed. Since libraries may be used in many different contexts, library developers cannot make safety-performance trade-off decisions appropriate for all cases. Application developers can tune libraries themselves to increase safety or performance, but this requires extra effort and makes libraries less reusable. To address this problem, we present NADER, a Rust development tool that makes applications safer by automatically transforming unsafe code into equivalent safe code according to developer preferences and application context. In end-to-end system evaluations in a given context, NADER automatically reintroduces numerous library bounds checks, in many cases making application code that uses popular Rust libraries safer with no corresponding loss in performance.
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Izatri, Dini Idzni, Nofita Idaroka Rohmah, and Renny Sari Dewi. "Identifikasi Risiko pada Perpustakaan Daerah Gresik dengan NIST SP 800-30." JURIKOM (Jurnal Riset Komputer) 7, no. 1 (2020): 50. http://dx.doi.org/10.30865/jurikom.v7i1.1756.
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With the rapid development of technology in Indonesia, several companies and government institutions have begun to implement IT in their systems, as well as the Gresik Regency Regional Library. Information Technology is a field of technology management and covers various fields including but not limited to things such as processes, computer software, information systems, computer hardware, programming languages, and data construction. In short, what makes data, information or knowledge felt in any visual format, through any mechanism of multimedia distribution, is considered part of Information Technology. Regional Library of Gresik Regency is one of the institutions from the government that has implemented Information Technology in their system. Gresik district library has about thirty thousand books consisting of novels, magazines, school textbooks, literature, and others. The Regional Library of Gresik Regency is now using the INLIS LITE application, this application is used by the library, from the collection of books to the list of library members
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BANYASAD, OMID, and PHILIP T. COX. "Integrating design synthesis and assembly of structured objects in a visual design language." Theory and Practice of Logic Programming 5, no. 6 (2005): 601–21. http://dx.doi.org/10.1017/s1471068404002285.
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Computer Aided Design systems provide tools for building and manipulating models of solid objects. Some also provide access to programming languages so that parametrised designs can be expressed. There is a sharp distinction, therefore, between building models, a concrete graphical editing activity, and programming, an abstract, textual, algorithm-construction activity. The recently proposed Language for Structured Design (LSD) was motivated by a desire to combine the design and programming activities in one language. LSD achieves this by extending a visual logic programming language to incorporate the notions of solids and operations on solids. Here we investigate another aspect of the LSD approach, namely, that by using visual logic programming as the engine to drive the parametrised assembly of objects, we also gain the powerful symbolic problem-solving capability that is the forté of logic programming languages. This allows the designer/programmer to work at a higher level, giving declarative specifications of a design in order to obtain the design descriptions. Hence LSD integrates problem solving, design synthesis, and prototype assembly in a single homogeneous programming/design environment. We demonstrate this specification-to-final-assembly capability using the masterkeying problem for designing systems of locks and keys.
Dissertationen zum Thema "Hardware Construction Languages (HCLs)"
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Ait, Bensaid Samira. "Formal Semantics of Hardware Compilation Framework." Electronic Thesis or Diss., université Paris-Saclay, 2023. http://www.theses.fr/2023UPASG085.
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Les analyses statiques de pire temps d’exécution sont utilisées pour garantir les délais requis pour les systèmes critiques. Afin d’estimer des bornes précises sur ces temps d’exécution, ces analyses temporelles nécessitent des considérations sur la (micro)- architecture. Habituellement, ces modèles de micro-architecture sont construits à la main à partir des manuels des processeurs. Cependant, les initiatives du matériel libre et les langages de description de matériel de haut niveau (HCLs), permettent de réaborder la problématique de la génération automatique de ces modèles de micro-architecture, et plus spécifiquement des modèles de pipeline. Nous proposons un workflow qui vise à construire automatiquement des modèles de chemin de données de pipeline à partir de conceptions de processeurs décrites dans des langages de contruction de matériel (HCLs). Notre workflow est basé sur la chaine de compilation matériel Chisel/FIRRTL. Nous construisons au niveau de la représentation intermédiaire les modèles de pipeline du chemin de données. Notre travail vise à appliquer ces modèles pour prouver des propriétés liées à la prédictibilité temporelle. Notre méthode repose sur la vérification formelle. Les modèles générés sont ensuite traduits en modèles formels et intégrés dans une procédure existante basée sur la vérification de modèles pour détecter les anomalies de temps. Nous utilisons le langage de modélisation et de vérification TLA+ et expérimentons notre analyse avec plusieurs processeurs RISC-V open-source. Enfin, nous faisons progresser les études en évaluant l’impact de la génération automatique à l’aide d’une série de critères synthétiques<br>Static worst-case timing analyses are used to ensure the timing deadlines required for safety-critical systems. In order to derive accurate bounds, these timing analyses require precise (micro-)architecture considerations. Usually, such micro-architecture models are constructed by hand from processor manuals.However, with the open-source hardware initiatives and high-level Hardware Description Languages (HCLs), the automatic generation of these micro-architecture models and, more specifically, the pipeline models are promoted. We propose a workflow that aims to automatically construct pipeline datapath models from processor designs described in HCLs. Our workflow is based on the Chisel/FIRRTL Hardware Compiler Framework. We build at the intermediate representation level the datapath pipeline models. Our work intends to prove the timing properties, such as the timing predictability-related properties. We rely on the formal verification as our method. The generated models are then translated into formal models and integrated into an existing model checking-based procedure for detecting timing anomalies. We use TLA+ modeling and verification language and experiment with our analysis with several open-source RISC-V processors. Finally, we advance the studies by evaluating the impact of automatic generation through a series of synthetic benchmarks
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Slipp, Walter Whitfield 1964. "Display of arbitrary subgraphs for HPCOM-generated networks." Thesis, The University of Arizona, 1989. http://hdl.handle.net/10150/277016.
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Hardware description languages provide digital system designers with a convenient, compact method for describing complex circuits. A Hardware Programming Language (AHPL) is a powerful description language based on the APL programming language. AHPL circuit descriptions can be unambiguously translated into a logic gate network using the HPCOM hardware compiler. The initial discussion section covers the conversion of the VAX version of HPCOM into a version which will run on MS-DOS microcomputers. The major portion of the research focuses on the development, use, and application of a graphics display tool for HPCOM-generated networks. The display package, SUBGRAPH, allows selected subgraphs of a network to be viewed and/or printed. The discussion of this research concludes with an extensive example of the complete circuit generation and graphics display sequence. The printed graphics examples feature cases of particular interest for test generation.
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Nzekwa, Russel. "Construction flexible des boucles de contrôles autonomes pour les applications à large échelle." Phd thesis, Université des Sciences et Technologie de Lille - Lille I, 2013. http://tel.archives-ouvertes.fr/tel-00843874.
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Les logiciels modernes sont de plus en plus complexes. Ceci est dû en partie à l'hétérogénéité des solutions misent en oeuvre, au caractère distribué des architectures de déploiement et à la dynamicité requise pour de tels logiciels qui devraient être capable de s'adapter en fonction des variations de leur contexte d'évolution. D'un autre coté, l'importance grandissante des contraintes de productivité dans le but de réduire les coûts de maintenance et de production des systèmes informatiques a favorisé l'émergence de nouveaux paradigmes pour répondre à la complexité des logiciels modernes. L'informatique des systèmes autonomes (Autonomic computing) s'inscrit dans cette perspective. Elle se propose entre autres de réduire le coût de maintenance des systèmes informatiques en développant des logiciels dits autonomes, c'est à dire dotés de la capacité de s'auto-gérer moyennant une intervention limité d'un opérateur humain. Toutefois, le développement de logiciels autonomes soulèvent de nombreux défis scientifiques et technologiques. Par exemple, l'absence de visibilité de la couche de contrôle dans les applications autonomes rend difficile leur maintenabilité, l'absence d'outils de vérification pour les architectures autonomes est un frein pour l'implémentation d'applications fiables, enfin, la gestion transparente des propriétés non-fonctionnelles et la traçabilité entre le design et l'implémentation sont autant de défis que pose la construction de logiciels autonomes flexibles. La principale contribution de cette thèse est CORONA. CORONA est un canevas logiciel qui vise à faciliter le développement de logiciels autonomes flexibles. Dans cet objectif, CORONA s'appuie sur un langage de description architecturale qui réifie les éléments qui forment la couche de contrôle dans les systèmes autonomes. CORONA permet l'intégration transparente des propriétés non-fonctionnelles dans la description architecturale des systèmes autonomes. il fournit aussi dans sa chaîne de compilation un ensemble d'outils qui permet d'effectuer des vérifications sur l'architecture des systèmes autonomes. Enfin, la traçabilité entre le design et l'implémentation est assurée par un mécanisme de génération des skeletons d'implémentation à partir d'une description architecturale. Les différentes propriétés de CORONA sont illustrées par trois cas d'utilisation.
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Zimmerman, Nicole P. "Time-Variant Load Models of Electric Vehicle Chargers." PDXScholar, 2015. https://pdxscholar.library.pdx.edu/open_access_etds/2297.
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In power distribution system planning, it is essential to understand the impacts that electric vehicles (EVs), and the non-linear, time-variant loading profiles associated with their charging units, may have on power distribution networks. This research presents a design methodology for the creation of both analytical and behavioral models for EV charging units within a VHDL-AMS simulation environment.
Voltage and current data collected from Electric Avenue, located on the Portland State University campus, were used to create harmonic profiles of the EV charging units at the site. From these profiles, generalized models for both single-phase (Level 2) and three-phase (Level 3) EV chargers were created. Further, these models were validated within a larger system context utilizing the IEEE 13-bus distribution test feeder system.
Results from the model's validation are presented for various charger and power system configurations. Finally, an online tool that was created for use by distribution system designers is presented. This tool can aid designers in assessing the impacts that EV chargers have on electrical assets, and assist with the appropriate selection of transformers, conductor ampacities, and protection equipment & settings.
Bücher zum Thema "Hardware Construction Languages (HCLs)"
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Alain, Vachoux, ed. Analog and mixed-signal hardware description languages. Kluwer Academic Publishers, 1997.
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IFIP WG10.2 International Symposium on Computer Hardware Description Languages and their Applications (9th 1989 Washington, D. C.). Computer hardware description languages and their applications: Proceedings of theIFIP WG 10.2 Ninth International Symposium on Computer Hardware Description Languages and their Applications : Washington, D. C., U.S.A., 19-21 June, 1989. North-Holland, 1990.
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Carlos, Delgado Kloos, and Damm Werner, eds. Practical formal methods for hardware design. Springer, 1997.
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1947-, Koomen C. J., Motooka To ru 1929-, IFIP TC-10, and IFIP WG 10 2, eds. Computer hardware description languages and their applications: Proceedings of the IFIP WG 10.2 Seventh International Conference on Computer Hardware Description Languages and Their Applications, Tokyo, Japan, 29-31 August 1985. North-Holland, 1985.
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IFIP WG 10.2 International Conference on Computer Hardware Description Languages and their Applications (7th 1985 Tokyo). Computer hardware description languages and their applications: Proceedings of the IFIP WG 10.2 Seventh International Conference on Computer Hardware Description Languages and their Applications : Tokyo, Japan, 29-31 August, 1985. North-Holland, 1985.
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(2003), FDL'03. Languages for system specification: Selected contributions on UML, SystemC, System Verilig, mixed-signal systems, and property specification from FDL'03. Kluwer Academic Publishers, 2004.
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Anne, Mignotte, Villar Eugenio, and Horobin Lynn, eds. System on chip design languages: Extended papers : best of FDL'01 and HDLCon'01. Kluwer Academic Publishers, 2002.
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Hoffmann, Andreas. Architecture exploration for embedded processors with LISA. Kluwer Academic Publishers, 2002.
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1956-, Foster Harry, ed. Principles of verifiable RTL design: A functional coding style supporting verification processes in Verilog. Kluwer Academic Publishers, 2000.
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Bening, Lionel. Principles of verifiable RTL design: A functional coding style supporting verification processes in Verilog. 2nd ed. Kluwer Academic Publishers, 2001.
Den vollen Inhalt der Quelle findenBuchteile zum Thema "Hardware Construction Languages (HCLs)"
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Mycroft, Alan, and Richard Sharp. "Hardware/Software Co-design Using Functional Languages." In Tools and Algorithms for the Construction and Analysis of Systems. Springer Berlin Heidelberg, 2001. http://dx.doi.org/10.1007/3-540-45319-9_17.
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Hartmanns, Arnd. "Correct Probabilistic Model Checking with Floating-Point Arithmetic." In Tools and Algorithms for the Construction and Analysis of Systems. Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-030-99527-0_3.
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AbstractProbabilistic model checking computes probabilities and expected values related to designated behaviours of interest in Markov models. As a formal verification approach, it is applied to critical systems; thus we trust that probabilistic model checkers deliver correct results. To achieve scalability and performance, however, these tools use finite-precision floating-point numbers to represent and calculate probabilities and other values. As a consequence, their results are affected by rounding errors that may accumulate and interact in hard-to-predict ways. In this paper, we show how to implement fast and correct probabilistic model checking by exploiting the ability of current hardware to control the direction of rounding in floating-point calculations. We outline the complications in achieving correct rounding from higher-level programming languages, describe our implementation as part of the Modest Toolset’s model checker, and exemplify the tradeoffs between performance and correctness in an extensive experimental evaluation across different operating systems and CPU architectures.
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de Niz, Dionisio, Gaurav Bhatia, and Raj Rajkumar. "Separation of Concerns in Model-Based Development of Distributed Real-Time Systems." In Behavioral Modeling for Embedded Systems and Technologies. IGI Global, 2010. http://dx.doi.org/10.4018/978-1-60566-750-8.ch006.
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Software is increasingly being used to enable new features in systems in multiple domains. These domains include automotive, avionics, telecomunication, and industrial automation. Because the user of these systems is not aware of the presence of the software, this type of software is known as embedded software. More importantly, such a software, and the whole system in general, must satisfy not only logical functional requirements but also parafunctional (a.k.a. nonfunctional) properties such as timeliness, security, and reliability. Traditional development languages and tools provide powerful abstractions such as functions, classes, and objects to build a functional structure that reduces complexity and enables software reuse. However, the software elements responsible for the parafunctional behaviors are frequently scattered across the functional structure. This scattering prevents the easy identification of these elements and their independent manipulation/reuse to achieve a specific parafunctional behavior. As a result, the complexity of parafunctional behaviors cannot be reduced and even worse, the construction of those behaviors can corrupt the functional structure of the software. In this chapter, we propose a model-based framework for designing embedded real-time systems to enable a decomposition structure that reduces the complexity of both functional and parafunctional aspects of the software. This decomposition enables the separation of the functional and parafunctional aspects of the system into semantic dimensions (e.g., event-flow, timing, deployment, fault-tolerant) that can be represented, manipulated, and modified independent of one another from an end-user point of view. The realizations of these dimensions, however, do interact on the target platform since they consume common resources and impose constraints. These interactions can be captured during model construction and resource demands mediated during platform deployment. The use of semantic dimensions results in three significant benefits. First of all, it preserves the independence of the functional structure from parafunctional behaviors. Secondly, it enables the user to manipulate different parafunctional concerns (e.g., timeliness, reliability) independent of one another. Lastly, it enables the reuse of compositions along any dimension from other systems. The second core abstraction in our modeling approach is an entity called a coupler. A coupler expresses a particular relationship between two or more components, and can also be used recursively. Couplers enable the hierarchical decomposition of functional as well as parafunctional aspects. Aided by semantic dimensions and multiple coupler types, our framework enables the auto-generation of glue code to produce a fully deployable system. Our framework can also construct a detailed timing and resource model. This model in turn is used to optimize the usage of a given hardware configuration, or synthesize a configuration to suit a given software model. Our framework is implemented in a tool (de Niz, Bhatia & Rajkumar 2006) called SysWeaver that had been used to generate glue code and analyze the timing behavior of avionics, automotive, and software-radio pilot systems.
Konferenzberichte zum Thema "Hardware Construction Languages (HCLs)"
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Lukashov, Ivan, and Alexander Antonov. "TRANSACTION-LEVEL DESIGNING OF NEUROMORPHIC PROCESSORS MICROARCHITECTURE." In 24th SGEM International Multidisciplinary Scientific GeoConference 2024. STEF92 Technology, 2024. https://doi.org/10.5593/sgem2024/2.1/s07.11.
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Spiking neural networks (SNNs) is a promising research direction to their ability to imitate certain functions of brain. Hardware acceleration of SNN can offer orders of magnitude increase in performance and power efficiency. However, traditional hardware description languages have a barrier for rapid development and prototyping of custom internal hardware mechanisms that affect hardware construction throughout the entire processor structure. Mainstream high-level design methods also have disadvantages, e.g. poor focus on transaction streams management description in dynamically scheduled pipelined structures. To accelerate development of custom neuromorphic processors, we propose Neuromorphix software library, which implements a flexible, reconfigurable microarchitectural template enabling selection of a set of transactions specific to neuromorphic processors. Neuromorphix is based on the previously developed ActiveCore open-source framework, which provides a hardware-oriented intermediate representation for generation of hardware data types, operations and behavioral logic. Development process is accelerated by automatic generation of hardware structures typical for neuromorphic processors using transaction-level approach. At the same time, Neuromorphix supports the option to integrate user-defined hardware blocks and also enables reuse of high-level hardware mechanisms which allows to achieve fold decrease of entry barrier for a wide range of neuromorphic processors developers.
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Izraelevitz, Adam, Jack Koenig, Patrick Li, et al. "Reusability is FIRRTL ground: Hardware construction languages, compiler frameworks, and transformations." In 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). IEEE, 2017. http://dx.doi.org/10.1109/iccad.2017.8203780.
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Rebello Januário, Leonardo, Gustavo Henrique Müller, Alex Luciano Roesler Rese, Rudimar Luís Scaranto Dazzi, and Thiago Felski Pereira. "Máquina de Turing Analógica para Ensino de Linguagens Formais e Autômatos." In Computer on the Beach. Universidade do Vale do Itajaí, 2021. http://dx.doi.org/10.14210/cotb.v12.p531-533.
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The article describes the development of a practical device for teachingin the area of Computer Theory. In the study, an adaptationof the Turing Machine is presented, using hardware and softwareintegration to interpret Formal Languages. Simulating an Automaton,sensors and motors are used to move the device head to the leftand right and to read and write the input tape. The developmentof the mechanism is described in two parts, the first includes thehardware that consists of the construction and adaptation of theTuring Machine, the second the implementation of the software andcommunication part between both. The developed device, allowsthe interpretation of a binary alphabet (0, 1), where an input word isaccepted, and as an output result, such device rejected or acceptedthe word.
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Guida, Francesco Ermanno, and Ernesto Voltaggio. "Programming Visual Representations. Evolutions of Visual Identities between Tangible and Intangible." In Systems & Design: Beyond Processes and Thinking. Universitat Politècnica València, 2016. http://dx.doi.org/10.4995/ifdp.2016.3334.
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The communication design field it's considerably changed in the last 20 years and more as well as the role of the designer. Technology has modified the daily work tools and new possible relations between the designer, the commitment and the final user can be underlined. Observing some of the most experimental practices, new visual languages have draw the attention, affected by innovative approaches and mixed competencies. The area of visual identities is especially of interest, not excluding other areas of experimentations.The phenomenon of the so-called dynamic or post-logo identities underlined the possibilities of using more fluid and expressive, variable, context related, processual, performative, non-linear, consistent visual languages instead of the usual and static repetition of a logo or an imposed series of rules (Felsing, 2010). But also their contradictions in making recognizable an organization and in the visual identity daily management.An interesting evolution to be underlined is in the use of the digital tools, not anymore in a passive way but in an active way. Visual designers can build their digital tools basing them on design and esthetic needs. Innovation is in the creative process, instead of in the final result, is in the “way to live our own creativeness” as affirmed precisely by Soddu (1998).The designer is not anymore just the user of ready-made digital tools, becoming himself programmer of customized digital toolboxes by using open source codes like Processing or VVVV or hardware like Arduino. This allows to affirm that visual designers are are becoming designer-producers (Bianchini &amp; Maffei, 2012) too, as its happening for the colleagues of the product design field. Not just a DIY attitude but something that it's changing the control knobs of a design system in all its process and development. As far as technology support is relevant, technical matters are relegated in the background on behalf of abstraction and data parametrization that means on behalf of a meta-design level. The use of programming in creative and visual communication design processes “empowers the designer, freeing he from the constraints of predefined computational tools, and promoting creative freedom in the construction of visual metaphors” (Duro, Machado, Rebelo, 2012). The aim of this paper is to argue this recent evolution in the field of visual identities and in the wider area of communication design practices.DOI: http://dx.doi.org/10.4995/IFDP.2016.3334