Thematische Bibliographien / Logic optimizations

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Auswahl der wissenschaftlichen Literatur zum Thema „Logic optimizations“

Autor: Grafiati

Veröffentlicht am 28. Juni 2021

Zuletzt aktualisiert am 1. Februar 2022

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Zeitschriftenartikel zum Thema "Logic optimizations"

Rus, Teodor, and Eric van Wyk. "Using Model Checking in a Parallelizing Compiler." Parallel Processing Letters 08, no. 04 (1998): 459–71. http://dx.doi.org/10.1142/s0129626498000468.

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In this paper we describe the usage of temporal logic model checking in a parallelizing compiler to analyze the structure of a source program and locate opportunities for optimization and parallelization. The source program is represented as a process graph in which the nodes are sequential processes and the edges are control and data dependence relationships between the computations at the nodes. By labeling the nodes and edges with descriptive atomic propositions and by specifying the conditions necessary for optimizations and parallelizations as temporal logic formulas, we can use a model checker to locate nodes of the process graph where particular optimizations can be made. To discover opportunities for new optimizations or modify existing ones in this parallelizing compiler, we need only specify their conditions as temporal logic formulas; we do not need to add to or modify the code of the compiler. This greatly simplifies the process of locating optimization and parallelization opportunities in the source program and makes it easier to experiment with complex optimizations. Hence, this methodology provides a convenient, concise, and formal framework in which to carry out program optimizations by compilers.

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Kudva, P., Associate, A. Sullivan, and W. Dougherty. "Measurements for structural logic synthesis optimizations." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 22, no. 6 (2003): 665–74. http://dx.doi.org/10.1109/tcad.2003.811456.

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Khurshid, Burhan, and Roohie Naaz. "Technology - Dependent Optimization of FIR Filters based on Carry - Save Multiplier and 4:2 Compressor unit." Electronics ETF 20, no. 2 (2017): 43. http://dx.doi.org/10.7251/els1620043k.

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This work presents an FPGA implementation of FIR filter based on 4:2 compressor and CSA multiplier unit. The hardware realizations presented in this pa per are based on the technology-dependent optimization of these individual units. The aim is to achieve an efficient mapping of these isolated units on Xilinx FPGAs. Conventional filter implementations consider only technology-independent optimizations and rely on Xilinx CAD tools to map the logic onto FPGA fabric. Very often this results in inefficient mapping. In this paper, we consider the traditional CSA-4:2 compressor based FIR filte rs and restructure these units to achieve improved integration levels. The technology optimized Boolean networks are then coded using instantiation based coding strategies. The Xilinx tool then uses its own optimization strategies to further optimize the networks and generate circuits with high logic densities and reduced depths. Experimental results indicate a significant improvement in performance over traditional realizations. An important property of technology-dependent optimizations is the simultaneous improvement in all the performance parameters. This is in contrast to the technology-independent optimizations where there is always an application driven trade-off between different performance parameters.

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Lacey, David, Neil D. Jones, Eric Van Wyk, and Carl Christian Frederiksen. "Proving correctness of compiler optimizations by temporal logic." ACM SIGPLAN Notices 37, no. 1 (2002): 283–94. http://dx.doi.org/10.1145/565816.503299.

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Zhou, Neng-Fa. "Global Optimizations in a Prolog Compiler for the Toam." Journal of Logic Programming 15, no. 4 (1993): 275–94. http://dx.doi.org/10.1016/s0743-1066(14)80001-0.

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ZHOU, NENG-FA, TAISUKE SATO, and YI-DONG SHEN. "Linear tabling strategies and optimizations." Theory and Practice of Logic Programming 8, no. 01 (2007): 81–109. http://dx.doi.org/10.1017/s147106840700316x.

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AbstractRecently there has been a growing interest in research in tabling in the logic programming community because of its usefulness in a variety of application domains including program analysis, parsing, deductive databases, theorem proving, model checking, and logic-based probabilistic learning. The main idea of tabling is to memorize the answers to some subgoals and use the answers to resolve subsequent variant subgoals. Early resolution mechanisms proposed for tabling such as OLDT and SLG rely on suspension and resumption of subgoals to compute fixpoints. Recently, the iterative approach named linear tabling has received considerable attention because of its simplicity, ease of implementation, and good space efficiency. Linear tabling is a framework from which different methods can be derived on the basis of the strategies used in handling looping subgoals. One decision concerns when answers are consumed and returned. This article describes two strategies, namely,lazyandeagerstrategies, and compares them both qualitatively and quantitatively. The results indicate that, while the lazy strategy has good locality and is well suited for finding all solutions, the eager strategy is comparable in speed with the lazy strategy and is well suited for programs with cuts. Linear tabling relies on depth-first iterative deepening rather than suspension to compute fixpoints. Each cluster of interdependent subgoals as represented by a topmost looping subgoal is iteratively evaluated until no subgoal in it can produce any new answers. Naive re-evaluation of all looping subgoals, albeit simple, may be computationally unacceptable. In this article, we also introduce semi-naive optimization, an effective technique employed in bottom-up evaluation of logic programs to avoid redundant joins of answers, into linear tabling. We give the conditions for the technique to be safe (i.e., sound and complete) and propose an optimization technique calledearly answer promotionto enhance its effectiveness. Benchmarking in B-Prolog demonstrates that with this optimization linear tabling compares favorably well in speed with the state-of-the-art implementation of SLG.

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BÁRÁNY, VINCE, MICHAEL BENEDIKT, and BALDER TEN CATE. "SOME MODEL THEORY OF GUARDED NEGATION." Journal of Symbolic Logic 83, no. 04 (2018): 1307–44. http://dx.doi.org/10.1017/jsl.2018.64.

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AbstractThe Guarded Negation Fragment (GNFO) is a fragment of first-order logic that contains all positive existential formulas, can express the first-order translations of basic modal logic and of many description logics, along with many sentences that arise in databases. It has been shown that the syntax of GNFO is restrictive enough so that computational problems such as validity and satisfiability are still decidable. This suggests that, in spite of its expressive power, GNFO formulas are amenable to novel optimizations. In this article we study the model theory of GNFO formulas. Our results include effective preservation theorems for GNFO, effective Craig Interpolation and Beth Definability results, and the ability to express the certain answers of queries with respect to a large class of GNFO sentences within very restricted logics.

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Hernández-Ramos, José L., Antonio J. Jara, Leandro Marín, and Antonio F. Skarmeta Gómez. "DCapBAC: embedding authorization logic into smart things through ECC optimizations." International Journal of Computer Mathematics 93, no. 2 (2014): 345–66. http://dx.doi.org/10.1080/00207160.2014.915316.

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Hsiao, K. S., and C. H. Chen. "Wake-Up Logic Optimizations Through Selective Match and Wakeup Range Limitation." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 14, no. 10 (2006): 1089–102. http://dx.doi.org/10.1109/tvlsi.2006.884150.

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Sheriff, Bonnie A., Dunwei Wang, James R. Heath, and Juanita N. Kurtin. "Complementary Symmetry Nanowire Logic Circuits: Experimental Demonstrations and in Silico Optimizations." ACS Nano 2, no. 9 (2008): 1789–98. http://dx.doi.org/10.1021/nn800025q.

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Dissertationen zum Thema "Logic optimizations"

Crha, Adam. "Syntéza a optimalizace polymorfních obvodů." Doctoral thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2021. http://www.nusl.cz/ntk/nusl-444886.

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Tato práce se zabývá metodami logické syntézy a optimalizací pro polymorfní obvody. V práci jsou jak diskutovány existující metody pro konvenční obvody, tak i představeny nové metody, aplikovatelné na polymorfní elektroniku. Hlavním přínosem práce je představení nových metod optimalizace a logické syntézy pro polymorfní obvody. Přesto, že v minulých letech byly představeny metody pro návrh polymorfních obvodů, jsou tyto metody založené na evolučních technikách nebo nejsou dobře škálovatelné. Z toho vyplývá, že stále neexistuje stabilní metodika pro návrh složitějších polymorfních obvodů. Tato práce představuje zejména reprezentaci polymorgních obvodů a metodiku pro jejich návrh založenou na And-Inverter grafech. Na polymorfní obvody reprezentované pomocí AIG je možné aplikovat známé techniky jako například přepisování [rewriting]. Nasazením techniky přepisování na polymorfní AIG získáme obvod, obsahující polymorfní prvky uvnitř obvodu, a je možné dosáhnout značných úspor prostředků, které mohou být sdíleny mezi dvěma funkcemi současně. Ověření návrhové metodiky pro polymorfní obvody bylo provedeno nad sadou veřejně dostupných obvodů, čímž je demonstrována efektivita metodiky.

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Xu, Qing. "Optimization techniques for distributed logic simulation." Thesis, McGill University, 2011. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=96665.

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Gate level simulation is a necessary step to verify the correctness of a circuitdesign before fabrication. It is a very time-consuming application, especially in lightof current circuit sizes. Since circuits are continually growing in size and complexity,there is a need for more efficient simulation techniques to keep the circuit verificationtime acceptably small. The use of parallel or distributed simulation is such a technique.When executed on a network of workstations, distributed simulation is alsoa very cost-effective technique. This research focuses on optimization techniques forTime Warp based gate-level logic simulations. The techniques which are described inthis thesis are oriented towards distributed platforms. The first major contributionof this thesis was the creation of an object oriented distributed simulator, XTW. Ituses an optimistic synchronization algorithm and incorporates a number of knownoptimization techniques targeting different aspects of distributed logic simulation.XEQ, an O(1) event scheduling algorithm for this simulator was developed for usein XTW. XEQ enabled us to execute gate level simulations up to 9.4 times fasterthan the same simulator using a skip-list (O(lg n)) event queue. rb-messagea mechanism which reduces the cost of rollback in Time Warp was also developedfor use in XTW. Our experiments revealed that the rb-message mechanism reducedthe number of anti-messages sent in a Time Warp based logic simulation by 76%on average. Moreover, based on the observations that (1)not all circuits should besimulated in parallel and (2) different circuits achieve their best parallel simulationperformance with a different number of compute nodes, an algorithm that uses theK-NN machine learning algorithm was devised to determine the most effective softwareand hardware combination for a logic simulation. After an extensive trainingregime, it was shown to make a correct prediction 99% of the time on whether touse a parallel or sequential simulator. The predicted number of nodes to use on aparallel platform was shown to produce an average execution time which was notmore than 12% of the smallest execution time. The configuration which resulted inthe minimal execution time was picked 61% of the time. A final contribution of thisthesis is an effort to link together commercial single processor simulators making useof Verilog PLI. La simulation "gate-level" est une tape ncessaire pour vrifier la conformit dela conception d'un circuit avant sa fabrication. C'est un programme qui prendbeaucoup de temps, compte tenu particulirement de la taille actuelle des circuits.Ceux-ci ne cessant de se dvelopper en taille et en complexit, il y a un rel besoin detechniques de simulation plus efficaces afin de maintenir la dure de vrification ducircuit raisonnablement courte. Une de ces techniques consiste utiliser la simulationparallle ou distribue. Quand excute sur un rseau de postes de travail, la simulationdistribue se rvle galement tre une technique trs rentable. Cette recherche se concentresur l'optimisation des techniques de simulations "gate-level" logiques bases surTime Warp. Les techniques qui sont dcrites dans cet expos sont orientes vers lesplateformes distribues. La premire contribution majeure de cet expos a t la crationd'un simulateur distribu orient sur l'objet, XTW. Il utilise un algorithme de synchronisationoptimiste et incorpore un certain nombre de techniques d'optimisationconnues visant diffrents aspects de la simulation distribue logique. XEQ, un algorithmeprogrammateur d'vnements O(1) pour ce simulateur a t dvelopp pour treutilis dans XTW. XEQ nous permet d'excuter des simulations "gate-level" jusqu'9,4 fois plus rapides qu'avec le mme simulateur utilisant une suite d'vnement en"skip-list" (O(lg n)). "rb-message" – un mcanisme qui diminue le co?t de rductiondans Time Warp a galement t mis au point pour tre utilis dans XTW. Nos essaisont rvl que le mcanisme de "rb-message" permettait de diminuer le nombre des antimessagesenvoys au cours d'une simulation logique base sur Time Warp de 76 % enmoyenne. Il a t en outre con?u, en se basant sur les observations que (1) certainscircuits ne devraient pas tre simuls en parallle et (2) que diffrents circuits atteignentleur meilleure performance de simulation parallle avec un nombre diffrent de noeudsde calculs, un algorithme utilisant l'algorithme d'apprentissage de la machine K-NNafin de dterminer quelle tait l'association de logiciel et de matriel la plus efficacedans le cadre d'une simulation logique. l'issue d'un entra?nement approfondi, ilest apparu qu'il pouvait faire un pronostic juste 99 % tablissant quand utiliser unsimulateur parallle ou squentiel. Le nombre annonc de noeuds utiliser sur une plateformeparallle s'est avr permettre une dure d'excution moyenne gale 12 % de la pluscourte dure d'excution. La configuration ayant abouti la dure d'excution minimalea t reprise dans 61 % des cas. Dernire contribution apporte par cet expos, relier lessimulateurs commerciaux processeur unique utilisant Verilog PLI.

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Dadone, Paolo. "Design Optimization of Fuzzy Logic Systems." Diss., Virginia Tech, 2001. http://hdl.handle.net/10919/27893.

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Fuzzy logic systems are widely used for control, system identification, and pattern recognition problems. In order to maximize their performance, it is often necessary to undertake a design optimization process in which the adjustable parameters defining a particular fuzzy system are tuned to maximize a given performance criterion. Some data to approximate are commonly available and yield what is called the supervised learning problem. In this problem we typically wish to minimize the sum of the squares of errors in approximating the data. We first introduce fuzzy logic systems and the supervised learning problem that, in effect, is a nonlinear optimization problem that at times can be non-differentiable. We review the existing approaches and discuss their weaknesses and the issues involved. We then focus on one of these problems, i.e., non-differentiability of the objective function, and show how current approaches that do not account for non-differentiability can diverge. Moreover, we also show that non-differentiability may also have an adverse practical impact on algorithmic performances. We reformulate both the supervised learning problem and piecewise linear membership functions in order to obtain a polynomial or factorable optimization problem. We propose the application of a global nonconvex optimization approach, namely, a reformulation and linearization technique. The expanded problem dimensionality does not make this approach feasible at this time, even though this reformulation along with the proposed technique still bears a theoretical interest. Moreover, some future research directions are identified. We propose a novel approach to step-size selection in batch training. This approach uses a limited memory quadratic fit on past convergence data. Thus, it is similar to response surface methodologies, but it differs from them in the type of data that are used to fit the model, that is, already available data from the history of the algorithm are used instead of data obtained according to an experimental design. The step-size along the update direction (e.g., negative gradient or deflected negative gradient) is chosen according to a criterion of minimum distance from the vertex of the quadratic model. This approach rescales the complexity in the step-size selection from the order of the (large) number of training data, as in the case of exact line searches, to the order of the number of parameters (generally lower than the number of training data). The quadratic fit approach and a reduced variant are tested on some function approximation examples yielding distributions of the final mean square errors that are improved (i.e., skewed toward lower errors) with respect to the ones in the commonly used pattern-by-pattern approach. Moreover, the quadratic fit is also competitive and sometimes better than the batch training with optimal step-sizes, thus showing an improved performance of this approach. The quadratic fit approach is also tested in conjunction with gradient deflection strategies and memoryless variable metric methods, showing errors smaller by 1 to 7 orders of magnitude. Moreover, the convergence speed by using either the negative gradient direction or a deflected direction is higher than that of the pattern-by-pattern approach, although the computational cost of the algorithm per iteration is moderately higher than the one of the pattern-by-pattern method. Finally, some directions for future research are identified. Ph. D.

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Lehar, Matthew A. 1977. "A branching fuzzy-logic classifier for building optimization." Thesis, Massachusetts Institute of Technology, 2005. http://hdl.handle.net/1721.1/32512.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Mechanical Engineering, 2005. Includes bibliographical references (p. 109-110). We present an input-output model that learns to emulate a complex building simulation of high dimensionality. Many multi-dimensional systems are dominated by the behavior of a small number of inputs over a limited range of input variation. Some also exhibit a tendency to respond relatively strongly to certain inputs over small ranges, and to other inputs over very large ranges of input variation. A branching linear discriminant can be used to isolate regions of local linearity in the input space, while also capturing the effects of scale. The quality of the classification may be improved by using a fuzzy preference relation to classify input configurations that are not well handled by the linear discriminant. by Matthew A. Lehar. Ph.D.

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Alidina, Mazhar Murtaza. "Precomputation-based sequential logic optimization for low power." Thesis, Massachusetts Institute of Technology, 1994. http://hdl.handle.net/1721.1/36454.

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Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994. Includes bibliographical references (leaves 69-71). by Mazhar Murtaza Alidina. M.S.

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Wang, Lingli. "Automated synthesis and optimization of multilevel logic circuits." Thesis, Edinburgh Napier University, 2000. http://researchrepository.napier.ac.uk/Output/4342.

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With the increased complexity of Very Large Scaled Integrated (VLSI) circuits, multilevel logic synthesis plays an even more important role due to its flexibility and compactness. The history of symbolic logic and some typical techniques for multilevel logic synthesis are reviewed. These methods include algorithmic approach; Rule-Based approach; Binary Decision Diagram (BDD) approach; Field Programmable Gate Array(FPGA) approach and several perturbation applications. One new kind of don't cares (DCs), called functional DCs has been proposed for multilevel logic synthesis. The conventional two-level cubes are generalized to multilevel cubes. Then functional DCs are generated based on the properties of containment. The concept of containment is more general than unateness which leads to the generation of new DCs. A separate C program has been developed to utilize the functional DCs generated as a Boolean function is decomposed for both single output and multiple output functions. The program can produce better results than script.rugged of SIS, developed by UC Berkeley, both in area and speed in less CPU time for a number of testcases from MCNC and IWLS'93 benchmarks. In certain applications ANDjXOR (Reed-Muller) logic has shown some attractive advantages over the standard Boolean logic based on AND JOR operations. A bidirectional conversion algorithm between these two paradigms is presented based on the concept of polarity for sum-of-products (SOP) Boolean functions, multiple segment and multiple pointer facilities. Experimental results show that the algorithm is much faster than the previously published programs for any fixed polarity. Based on this algorithm, a new technique called redundancy-removal is applied to generalize the idea to very large multiple output Boolean functions. Results for benchmarks with up to 199 inputs and 99 outputs are presented. Applying the preceding conversion program, any Boolean functions can be expressed by fixed polarity Reed-Muller forms. There are 2n polarities for an n-variable function and the number of product terms depends on these polarities. The problem of exact polarity minimization is computationally extensive and current programs are only suitable when n :::; 15. Based on the comparison of the concepts of polarity in the standard Boolean logic and Reed-Muller logic, a fast algorithm is developed and implemented in C language which can find the best polarity for multiple output functions. Benchmark examples of up to 25 inputs and 29 outputs run on a personal computer are given. After the best polarity for a Boolean function is calculated, this function can be further simplified using mixed polarity methods by combining the adjacent product terms. Hence, an efficient program is developed based on decomposition strategy to implement mixed polarity minimization for both single output and very large multiple output Boolean functions. Experimental results show that the numbers of product terms are much less than the results produced by ESPRESSO for some categories of functions.

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Sapiña, Sanchis Julia. "Rewriting Logic Techniques for Program Analysis and Optimization." Doctoral thesis, Universitat Politècnica de València, 2018. http://hdl.handle.net/10251/94044.

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Esta tesis propone una metodología de análisis dinámico que mejora el diagnóstico de programas erróneos escritos en el lenguaje Maude. La idea clave es combinar técnicas de verificación de aserciones en tiempo de ejecución con la fragmentación dinámica de trazas de ejecución para detectar automáticamente errores en tiempo de ejecución, al tiempo que se reduce el tamaño y la complejidad de las trazas a analizar. En el caso de violarse una aserción, se infiere automáticamente el criterio de fragmentación, lo que facilita al usuario identificar rápidamente la fuente del error. En primer lugar, la tesis formaliza una técnica destinada a detectar automáticamente eventuales desviaciones del comportamiento deseado del programa (síntomas de error). Esta técnica soporta dos tipos de aserciones definidas por el usuario: aserciones funcionales (que restringen llamadas a funciones deterministas) y aserciones de sistema (que especifican los invariantes de estado del sistema). La técnica de verificación dinámica propuesta es demostrablemente correcta en el sentido de que todos los errores señalados definitivamente delatan la violación de las aserciones. Tras eventuales violaciones de aserciones, se generan automáticamente trazas fragmentadas (es decir, trazas simplificadas pero igualmente precisas) que ayudan a identificar la causa del error. Además, la técnica también sugiere una posible reparación para las reglas implicadas en la generación de los estados erróneos. La metodología propuesta se basa en (i) una notación lógica para especificar las aserciones que se imponen a la ejecución; (ii) una técnica de verificación aplicable en tiempo de ejecución que comprueba dinámicamente las aserciones; y (iii) un mecanismo basado en la generalización (ecuacional) menos general que automáticamente obtiene criterios precisos para fragmentar trazas de ejecución a partir de aserciones falsificadas. Por último, se presenta una implementación de la técnica propuesta en la herramienta de análisis dinámico basado en aserciones ABETS, que muestra cómo es posible combinar el trazado de las propiedades asertadas del programa para obtener un algoritmo preciso de análisis de trazas que resulta útil para el diagnóstico y la depuración de programas. This thesis proposes a dynamic analysis methodology for improving the diagnosis of erroneous Maude programs. The key idea is to combine runtime assertion checking and dynamic trace slicing for automatically catching errors at runtime while reducing the size and complexity of the erroneous traces to be analyzed (i.e., those leading to states that fail to satisfy the assertions). In the event of an assertion violation, the slicing criterion is automatically inferred, which facilitates the user to rapidly pinpoint the source of the error. First, a technique is formalized that aims at automatically detecting anomalous deviations of the intended program behavior (error symptoms) by using assertions that are checked at runtime. This technique supports two types of user-defined assertions: functional assertions (which constrain deterministic function calls) and system assertions (which specify system state invariants). The proposed dynamic checking is provably sound in the sense that all errors flagged definitely signal a violation of the specifications. Then, upon eventual assertion violations, accurate trace slices (i.e., simplified yet precise execution traces) are generated automatically, which help identify the cause of the error. Moreover, the technique also suggests a possible repair for the rules involved in the generation of the erroneous states. The proposed methodology is based on (i) a logical notation for specifying assertions that are imposed on execution runs; (ii) a runtime checking technique that dynamically tests the assertions; and (iii) a mechanism based on (equational) least general generalization that automatically derives accurate criteria for slicing from falsified assertions. Finally, an implementation of the proposed technique is presented in the assertion-based, dynamic analyzer ABETS, which shows how the forward and backward tracking of asserted program properties leads to a thorough trace analysis algorithm that can be used for program diagnosis and debugging. Esta tesi proposa una metodologia d'anàlisi dinàmica que millora el diagnòstic de programes erronis escrits en el llenguatge Maude. La idea clau és combinar tècniques de verificació d'assercions en temps d'execució amb la fragmentació dinàmica de traces d'execució per a detectar automàticament errors en temps d'execució, alhora que es reduïx la grandària i la complexitat de les traces a analitzar. En el cas de violar-se una asserció, s'inferix automàticament el criteri de fragmentació, la qual cosa facilita a l'usuari identificar ràpidament la font de l'error. En primer lloc, la tesi formalitza una tècnica destinada a detectar automàticament eventuals desviacions del comportament desitjat del programa (símptomes d'error). Esta tècnica suporta dos tipus d'assercions definides per l'usuari: assercions funcionals (que restringixen crides a funcions deterministes) i assercions de sistema (que especifiquen els invariants d'estat del sistema). La tècnica de verificació dinàmica proposta és demostrablement correcta en el sentit que tots els errors assenyalats definitivament delaten la violació de les assercions. Davant eventuals violacions d'assercions, es generen automàticament traces fragmentades (és a dir, traces simplificades però igualment precises) que ajuden a identificar la causa de l'error. A més, la tècnica també suggerix una possible reparació de les regles implicades en la generació dels estats erronis. La metodologia proposada es basa en (i) una notació lògica per a especificar les assercions que s'imposen a l'execució; (ii) una tècnica de verificació aplicable en temps d'execució que comprova dinàmicament les assercions; i (iii) un mecanisme basat en la generalització (ecuacional) menys general que automàticament obté criteris precisos per a fragmentar traces d'execució a partir d'assercions falsificades. Finalment, es presenta una implementació de la tècnica proposta en la ferramenta d'anàlisi dinàmica basat en assercions ABETS, que mostra com és possible combinar el traçat cap avant i cap arrere de les propietats assertades del programa per a obtindre un algoritme precís d'anàlisi de traces que resulta útil per al diagnòstic i la depuració de programes. Sapiña Sanchis, J. (2017). Rewriting Logic Techniques for Program Analysis and Optimization [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/94044 TESIS

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Dosi, Shubham. "Optimization and Further Development of an Algorithm for Driver Intention Detection with Fuzzy Logic and Edit Distance." Master's thesis, Universitätsbibliothek Chemnitz, 2016. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-qucosa-202567.

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Inspired by the idea of vision zero, there is a lot of work that needs to be done in the field of advance driver assistance systems to develop more safer systems. Driver intention detection with a prediction of upcoming behavior of the driver is one possible solution to reduce the fatalities in road traffic. Driver intention detection provides an early warning of the driver's behavior to an Advanced Driver Assistance Systems (ADAS) and at the same time reduces the risk of non-essential warnings. This will significantly reduce the problem of warning dilemma and the system will become more safer. A driving maneuver prediction can be regarded as an implementation of driver's behavior. So the aim of this thesis is to determine the driver's intention by early prediction of a driving maneuver using Controller Area Network (CAN) bus data. The focus of this thesis is to optimize and further develop an algorithm for driver intention detection with fuzzy logic and edit distance method. At first the basics concerning driver's intention detection are described as there exists different ways to determine it. This work basically uses CAN bus data to determine a driver's intention. The algorithm overview with the design parameters are described next to have an idea about the functioning of the algorithm. Then different implementation tasks are explained for optimization and further development of the algorithm. The main aim to execute these implementation tasks is to improve the overall performance of the algorithm concerning True Positive Rate (TPR), False Positive Rate (FPR) and earliness values. At the end, the results are validated to check the algorithm performance with different possibilities and a test drive is performed to evaluate the real time capability of the algorithm. Lastly the use of driver intention detection algorithm for an ADAS to make it more safer is described in details. The early warning information can be feed to an ADAS, for example, an automatic collision avoidance or a lane change assistance ADAS to further improve safety for these systems.

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Feng, Yi. "Dynamic Fuzzy Logic Control of GeneticAlgorithm Probabilities." Thesis, Högskolan Dalarna, Datateknik, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:du-3286.

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Genetic algorithms are commonly used to solve combinatorial optimizationproblems. The implementation evolves using genetic operators (crossover, mutation,selection, etc.). Anyway, genetic algorithms like some other methods have parameters(population size, probabilities of crossover and mutation) which need to be tune orchosen.In this paper, our project is based on an existing hybrid genetic algorithmworking on the multiprocessor scheduling problem. We propose a hybrid Fuzzy-Genetic Algorithm (FLGA) approach to solve the multiprocessor scheduling problem.The algorithm consists in adding a fuzzy logic controller to control and tunedynamically different parameters (probabilities of crossover and mutation), in anattempt to improve the algorithm performance. For this purpose, we will design afuzzy logic controller based on fuzzy rules to control the probabilities of crossoverand mutation. Compared with the Standard Genetic Algorithm (SGA), the resultsclearly demonstrate that the FLGA method performs significantly better.

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Bengtsson, Tomas. "Testing and Logic Optimization Techniques for Systems on Chip." Doctoral thesis, Linköpings universitet, Programvara och system, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-84806.

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Today it is possible to integrate more than one billion transistors onto a single chip. This has enabled implementation of complex functionality in hand held gadgets, but handling such complexity is far from trivial. The challenges of handling this complexity are mostly related to the design and testing of the digital components of these chips. A number of well-researched disciplines must be employed in the efficient design of large and complex chips. These include utilization of several abstraction levels, design of appropriate architectures, several different classes of optimization methods, and development of testing techniques. This thesis contributes mainly to the areas of design optimization and testing methods. In the area of testing this thesis contributes methods for testing of on-chip links connecting different clock domains. This includes testing for defects that introduce unacceptable delay, lead to excessive crosstalk and cause glitches, which can produce errors. We show how pure digital components can be used to detect such defects and how the tests can be scheduled efficiently. To manage increasing test complexity, another contribution proposes to raise theabstraction level of fault models from logic level to system level. A set of system level faultmodels for a NoC-switch is proposed and evaluated to demonstrate their potential. In the area of design optimization, this thesis focuses primarily on logic optimization. Two contributions for Boolean decomposition are presented. The first one is a fast heuristic algorithm that finds non-disjoint decompositions for Boolean functions. This algorithm operates on a Binary Decision Diagram. The other contribution is a fast algorithm for detecting whether a function is likely to benefit from optimization for architectures with a gate depth of three with an XOR-gate as the third gate.

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Bücher zum Thema "Logic optimizations"

Khatri, Sunil P. Advanced techniques in logic synthesis, optimizations and applications. Springer, 2011.

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Gulati, Kanupriya, ed. Advanced Techniques in Logic Synthesis, Optimizations and Applications. Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4419-7518-8.

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Adam, Kaplan, and Sarrafzadeh Majid, eds. Synthesis techniques and optimizations for reconfigurable systems. Kluwer Academic Publishers, 2004.

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Kastner, Ryan. Synthesis techniques and optimizations for reconfigurable systems. Kluwer Academic Publishers, 2004.

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Sasao, Tsutomu. Logic Synthesis and Optimization. Springer US, 1993.

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Sasao, Tsutomu, ed. Logic Synthesis and Optimization. Springer US, 1993. http://dx.doi.org/10.1007/978-1-4615-3154-8.

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McAloon, Kenneth. Optimization and computational logic. Wiley, 1996.

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Hooker, John. Logic-Based Methods for Optimization. John Wiley & Sons, Inc., 2000. http://dx.doi.org/10.1002/9781118033036.

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Villa, Tiziano. Synthesis of Finite State Machines: Logic Optimization. Springer US, 1997.

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Chandru, Vijay. Optimization methods for logical inference. Wiley, 1999.

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Buchteile zum Thema "Logic optimizations"

Schrijvers, Tom. "Analyses, Optimizations and Extensions of Constraint Handling Rules: Ph.D. Summary." In Logic Programming. Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/11562931_44.

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Kozen, Dexter, and Maria-Cristina Patron. "Certification of Compiler Optimizations Using Kleene Algebra with Tests." In Computational Logic — CL 2000. Springer Berlin Heidelberg, 2000. http://dx.doi.org/10.1007/3-540-44957-4_38.

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Yang, Yu-Shen, Subarna Sinha, Andreas Veneris, Robert Brayton, and Duncan Smith. "Automated Logic Restructuring with aSPFDs." In Advanced Techniques in Logic Synthesis, Optimizations and Applications. Springer New York, 2010. http://dx.doi.org/10.1007/978-1-4419-7518-8_15.

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Krishnaswamy, Smita, Haoxing Ren, Nilesh Modi, and Ruchir Puri. "Logic Difference Optimization for Incremental Synthesis." In Advanced Techniques in Logic Synthesis, Optimizations and Applications. Springer New York, 2010. http://dx.doi.org/10.1007/978-1-4419-7518-8_12.

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Bernasconi, Anna, Valentina Ciriani, Gabriella Trucco, and Tiziano Villa. "Logic Synthesis by Signal-Driven Decomposition." In Advanced Techniques in Logic Synthesis, Optimizations and Applications. Springer New York, 2010. http://dx.doi.org/10.1007/978-1-4419-7518-8_2.

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Bollapalli, Kalyana C., Sunil P. Khatri, and Laszlo B. Kish. "Digital Logic Using Non-DC Signals." In Advanced Techniques in Logic Synthesis, Optimizations and Applications. Springer New York, 2010. http://dx.doi.org/10.1007/978-1-4419-7518-8_20.

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Kravets, Victor N., and Alan Mishchenko. "Sequential Logic Synthesis Using Symbolic Bi-decomposition." In Advanced Techniques in Logic Synthesis, Optimizations and Applications. Springer New York, 2010. http://dx.doi.org/10.1007/978-1-4419-7518-8_3.

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Brayton, Robert, Alan Mishchenko, and Satrajit Chatterjee. "Boolean Factoring and Decomposition of Logic Networks." In Advanced Techniques in Logic Synthesis, Optimizations and Applications. Springer New York, 2010. http://dx.doi.org/10.1007/978-1-4419-7518-8_4.

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Debray, Saumya K. "Compiler optimizations for low-level redundancy elimination: An application of meta-level prolog primitives." In Meta-Programming in Logic. Springer Berlin Heidelberg, 1992. http://dx.doi.org/10.1007/3-540-56282-6_8.

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Qian, Weikang, Marc D. Riedel, Kia Bazargan, and David J. Lilja. "Synthesizing Combinational Logic to Generate Probabilities: Theories and Algorithms." In Advanced Techniques in Logic Synthesis, Optimizations and Applications. Springer New York, 2010. http://dx.doi.org/10.1007/978-1-4419-7518-8_18.

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Konferenzberichte zum Thema "Logic optimizations"

Ehliar, Andreas, and Dake Liu. "An ASIC perspective on FPGA optimizations." In 2009 International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2009. http://dx.doi.org/10.1109/fpl.2009.5272311.

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Lacey, David, Neil D. Jones, Eric Van Wyk, and Carl Christian Frederiksen. "Proving correctness of compiler optimizations by temporal logic." In the 29th ACM SIGPLAN-SIGACT symposium. ACM Press, 2002. http://dx.doi.org/10.1145/503272.503299.

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Nguyen, Hong Diep, Bogdan Pasca, and Thomas B. Preußer. "FPGA-Specific Arithmetic Optimizations of Short-Latency Adders." In 2011 International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2011. http://dx.doi.org/10.1109/fpl.2011.49.

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Veenstra, Kerry, Bruce Pedersen, Jay Schleicher, and Chiakang Sung. "Optimizations for a highly cost-efficient programmable logic architecture." In the 1998 ACM/SIGDA sixth international symposium. ACM Press, 1998. http://dx.doi.org/10.1145/275107.275115.

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Nobre, Ricardo. "Identifying sequences of optimizations for HW/SW compilation." In 2013 23rd International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2013. http://dx.doi.org/10.1109/fpl.2013.6645615.

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Sulieman, Mawahib Hussein, Valeriu Beiu, and Walid Ibrahim. "Low-power and highly reliable logic gates transistor-level optimizations." In 2010 IEEE 10th Conference on Nanotechnology (IEEE-NANO). IEEE, 2010. http://dx.doi.org/10.1109/nano.2010.5697892.

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Zhu, Keren, Mingjie Liu, Hao Chen, Zheng Zhao, and David Z. Pan. "Exploring Logic Optimizations with Reinforcement Learning and Graph Convolutional Network." In MLCAD '20: 2020 ACM/IEEE Workshop on Machine Learning for CAD. ACM, 2020. http://dx.doi.org/10.1145/3380446.3430622.

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Hires, Matej, and Hashim Habiballa. "Fuzzy logic analysis optimizations for pattern recognition - Implementation and experimental results." In INTERNATIONAL CONFERENCE OF NUMERICAL ANALYSIS AND APPLIED MATHEMATICS (ICNAAM 2016). Author(s), 2017. http://dx.doi.org/10.1063/1.4992230.

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Goparaju, Manoj Kumar, and Spyros Tragoudas. "A Fault Tolerant Design Methodology for Threshold Logic Gates and Its Optimizations." In 8th International Symposium on Quality Electronic Design (ISQED'07). IEEE, 2007. http://dx.doi.org/10.1109/isqed.2007.12.

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Gondhalekar, Atharva, and Wu-Chun Feng. "Exploring FPGA Optimizations in OpenCL for Breadth-First Search on Sparse Graph Datasets." In 2020 30th International Conference on Field-Programmable Logic and Applications (FPL). IEEE, 2020. http://dx.doi.org/10.1109/fpl50879.2020.00032.

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Berichte der Organisationen zum Thema "Logic optimizations"

Smith, James F., Rhyne III, and II Robert D. Fuzzy Logic Resource Management and Coevolutionary Game-based Optimization. Defense Technical Information Center, 2001. http://dx.doi.org/10.21236/ada390559.

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