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Thematische Bibliographien / Memory transistor

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Zeitschriftenartikel

Auswahl der wissenschaftlichen Literatur zum Thema „Memory transistor“

Autor: Grafiati

Veröffentlicht am 25. Mai 2024

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Zeitschriftenartikel zum Thema "Memory transistor"

1

Xie, Fangqing, Maryna N. Kavalenka, Moritz Röger, et al. "Copper atomic-scale transistors." Beilstein Journal of Nanotechnology 8 (March 1, 2017): 530–38. http://dx.doi.org/10.3762/bjnano.8.57.

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We investigated copper as a working material for metallic atomic-scale transistors and confirmed that copper atomic-scale transistors can be fabricated and operated electrochemically in a copper electrolyte (CuSO4 + H2SO4) in bi-distilled water under ambient conditions with three microelectrodes (source, drain and gate). The electrochemical switching-on potential of the atomic-scale transistor is below 350 mV, and the switching-off potential is between 0 and −170 mV. The switching-on current is above 1 μA, which is compatible with semiconductor transistor devices. Both sign and amplitude of th

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2

Choi, Young Jin, Jihyun Kim, Min Je Kim, et al. "Hysteresis Behavior of the Donor–Acceptor-Type Ambipolar Semiconductor for Non-Volatile Memory Applications." Micromachines 12, no. 3 (2021): 301. http://dx.doi.org/10.3390/mi12030301.

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Donor–acceptor-type organic semiconductor molecules are of great interest for potential organic field-effect transistor applications with ambipolar characteristics and non-volatile memory applications. Here, we synthesized an organic semiconductor, PDPPT-TT, and directly utilized it in both field-effect transistor and non-volatile memory applications. As-synthesized PDPPT-TT was simply spin-coated on a substrate for the device fabrications. The PDPPT-TT based field-effect transistor showed ambipolar electrical transfer characteristics. Furthermore, a gold nanoparticle-embedded dielectric layer

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3

Kim, Woojo, Jimin Kwon, and Sungjune Jung. "3D Integration of Flexible and Printed Electronics: Integrated Circuits, Memories, and Sensors." Journal of Flexible and Printed Electronics 2, no. 2 (2023): 199–210. http://dx.doi.org/10.56767/jfpe.2023.2.2.199.

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Printing technologies have received a lot of attention and expectations for producing flexible and wearable electronics. However, the low transistor density of the printed devices has been a major obstacle to commercialization. In this review, a three-dimensional (3D) integration of organic flexible and printed electronics is described. First, layout-to-bitmap conversion and design rules for printed transistors, arrays, and integrated circuits are introduced. Then, printed 3D transistors, digital integrated circuits, and memories are described. Finally, 3D integration of printed active-matrix

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4

Kim, Ji-Hun, Hyeon-Jun Kim, Ki-Jun Kim, Tae-Hun Shim, Jin-Pyo Hong, and Jea-gun Park. "3-Terminal Igzo FET Based 2T0C DRAM Combined Bit-Line Structure." ECS Meeting Abstracts MA2023-02, no. 30 (2023): 1561. http://dx.doi.org/10.1149/ma2023-02301561mtgabs.

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The IGZO (InGaZnO)-based two-transistor zero-capacitor(2T0C) DRAM has attracted much attention as an alternative memory to overcome the scale-down limit of current 1T1C DRAM due to its low power consumption and monolithic 3D stacking capability. In particular, its low power consumption and the feasibility of low temperature process make it highly implementable for 3D DRAM. For operating the 2T0C DRAM, four metal lines are necessary, i.e., write word line and write bit line (WBL) for operating write transistor (WTR), and read word line and read bit line (RBL) for operating read transistor (RTR)

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5

Al-shawi, Amjad, Maysoon Alias, Paul Sayers, and Mohammed Fadhil Mabrook. "Improved Memory Properties of Graphene Oxide-Based Organic Memory Transistors." Micromachines 10, no. 10 (2019): 643. http://dx.doi.org/10.3390/mi10100643.

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To investigate the behaviour of the organic memory transistors, graphene oxide (GO) was utilized as the floating gate in 6,13-Bis(triisopropylsilylethynyl)pentacene (TIPS-pentacene)-based organic memory transistors. A cross-linked, off-centre spin-coated and ozone-treated poly(methyl methacrylate) (cPMMA) was used as the insulating layer. High mobility and negligible hysteresis with very clear transistor behaviour were observed for the control transistors. On the other hand, memory transistors exhibited clear large hysteresis which is increased with increasing programming voltage. The shifts i

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6

Brtník, Bohumil. "Assembling a Formula for Current Transferring by Using a Summary Graph and Transformation Graphs." Journal of Electrical Engineering 64, no. 5 (2013): 334–36. http://dx.doi.org/10.2478/jee-2013-0050.

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Abstract This paper deals with the symbolic solution of the switched current circuits. As is described, the full graph method of the solution can be used for finding relationships expressing current transfer, too. The summa MC-graph is constructed using two-graphs method in two-phase switching. By comparing the matrix form with results of the Mason’s formula are derived relations for current transfers in all phases. There are discussed various options described transistor memory cells - with loss and lossless transistors and normal transistor current mirror. Evaluation of the graph is simplifi

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7

Grudanov, Oleksandr. "Stability Parameters of Register File Bit Cell with Low Power Consumption Priority." Electronics and Control Systems 3, no. 77 (2023): 40–46. http://dx.doi.org/10.18372/1990-5548.77.17963.

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This research is dedicated to a transistor sizing method of an 8-transistor register file static random access memory bit cell aiming to create two-port register files and two-port static random access memory with reduced supply voltage to reduce power consumption. This method can also be applied to 6-transistor single-port static random access memory bit cells. The method is based on the analysis of butterfly curves and the search for such values of the sizes of transistors and margin of their threshold voltages, in which, for a given critical minimal supply voltage, the condition for the exi

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8

Fuller, Elliot J., Scott T. Keene, Armantas Melianas, et al. "Parallel programming of an ionic floating-gate memory array for scalable neuromorphic computing." Science 364, no. 6440 (2019): 570–74. http://dx.doi.org/10.1126/science.aaw5581.

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Neuromorphic computers could overcome efficiency bottlenecks inherent to conventional computing through parallel programming and readout of artificial neural network weights in a crossbar memory array. However, selective and linear weight updates and <10-nanoampere read currents are required for learning that surpasses conventional computing efficiency. We introduce an ionic floating-gate memory array based on a polymer redox transistor connected to a conductive-bridge memory (CBM). Selective and linear programming of a redox transistor array is executed in parallel by overcoming the bridgi

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9

Srinivasarao, B. N., and K. Chandrabhushana Rao. "Design and Analysis of Area Efficient 128 Bytes SRAM Architecture." Journal of VLSI Design and Signal Processing 8, no. 1 (2022): 19–26. http://dx.doi.org/10.46610/jovdsp.2022.v08i01.004.

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SRAM Memory architecture design and implementation is a challenging task for memory applications. Practical architecture was developed and used successfully using various double ended SRAM cells like 6 and 4 transistors. But for single ended SRAM cell like 5 transistors or any other number of transistors there is no specific architecture for practical applications. Conventional SRAM architecture has SRAM cell, write driver circuit along with bit inverter, Pre-charge circuit and sense amplifier which consists more, number of transistors required to handle single bit storage. In this paper SRAM

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10

Seo, Yeongkyo, and Kon-Woo Kwon. "Ultra High-Density SOT-MRAM Design for Last-Level On-Chip Cache Application." Electronics 12, no. 20 (2023): 4223. http://dx.doi.org/10.3390/electronics12204223.

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This paper presents ultra high-density spin-orbit torque magnetic random-access memory (SOT-MRAM) for last-level data cache application. Although SOT-MRAM has many appealing attributes of low write energy, nonvolatility, and high reliability, it poses challenges to ultra-high-density memory implementation. Due to using two access transistors per cell, the vertical dimension of SOT-MRAM is >40% longer than that of the spin-transfer torque magnetic random-access memory (STT-MRAM), a single transistor-based design. Moreover, the horizontal dimension cannot be reduced below two metal pitches du

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