Einloggen

Thematische Bibliographien / Output chips / Dissertationen

Um die anderen Arten von Veröffentlichungen zu diesem Thema anzuzeigen, folgen Sie diesem Link: Output chips.

Dissertationen zum Thema „Output chips“

Autor: Grafiati

Veröffentlicht am 4. Juni 2021

Zuletzt aktualisiert am 29. Juli 2025

Geben Sie eine Quelle nach APA, MLA, Chicago, Harvard und anderen Zitierweisen an

Wählen Sie eine Art der Quelle aus:

Machen Sie sich mit Top-30 Dissertationen für die Forschung zum Thema "Output chips" bekannt.

Neben jedem Werk im Literaturverzeichnis ist die Option "Zur Bibliographie hinzufügen" verfügbar. Nutzen Sie sie, wird Ihre bibliographische Angabe des gewählten Werkes nach der nötigen Zitierweise (APA, MLA, Harvard, Chicago, Vancouver usw.) automatisch gestaltet.

Sie können auch den vollen Text der wissenschaftlichen Publikation im PDF-Format herunterladen und eine Online-Annotation der Arbeit lesen, wenn die relevanten Parameter in den Metadaten verfügbar sind.

Sehen Sie die Dissertationen für verschiedene Spezialgebieten durch und erstellen Sie Ihre Bibliographie auf korrekte Weise.

1

Burrow, Ryan David. "Enhancing Input/Output Correctness, Protection, Performance, and Scalability for Process Control Platforms." Thesis, Virginia Tech, 2019. http://hdl.handle.net/10919/89903.

Der volle Inhalt der Quelle

Annotation:

Most modern control systems use digital controllers to ensure safe operation. We modify the traditional digital control system architecture to integrate a new component known as a trusted input/output processor (TIOP). TIOP interface to the inputs (sensors) and outputs (actuators) of the system through existing communication protocols. The TIOP also interface to the application processor (AP) through a simple message passing protocol. This removes any direct input/output (I/O) interaction from taking place in the AP. By isolating this interaction from the AP, system resilience against malware

APA, Harvard, Vancouver, ISO und andere Zitierweisen

2

Wang, Mingzhen. "High-speed Low-voltage CMOS Flash Analog-to-Digital Converter for Wideband Communication System-on-a-Chip." Wright State University / OhioLINK, 2007. http://rave.ohiolink.edu/etdc/view?acc_num=wright1189815482.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

3

Gupta, Vishal. "An accurate, trimless, high PSRR, low-voltage, CMOS bandgap reference IC." Diss., Available online, Georgia Institute of Technology, 2007, 2007. http://etd.gatech.edu/theses/available/etd-07052007-073154/.

Der volle Inhalt der Quelle

Annotation:

Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2008.<br>Ayazi, Farrokh, Committee Member ; Rincon-Mora, Gabriel, Committee Chair ; Bhatti, Pamela, Committee Member ; Leach, W. Marshall, Committee Member ; Morley, Thomas, Committee Member.

APA, Harvard, Vancouver, ISO und andere Zitierweisen

4

Chiu, Yan-Lian, and 邱彥璉. "On-Chip ESD Protection Design for Output Driver Applications." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/71703819228828214352.

Der volle Inhalt der Quelle

Annotation:

碩士<br>國立臺灣師範大學<br>電機工程學系<br>104<br>With the continuous evolution of semiconductor integrated circuits (ICs) process, electrostatic discharge (ESD) events are likely to cause internal electronic components of the wafer suffered irreversible damage. All microelectronic products must meet the reliability specifications. Therefore, ESD must be taken into consideration. In the application of integrated circuit, several novel ESD protection devices are designed in this work. By designing the structure, this work has been fabricated in 0.18-μm 1.8V/3.3V CMOS process. In the experimental results, t

APA, Harvard, Vancouver, ISO und andere Zitierweisen

5

Fang, Chein-Wei, and 方建偉. "Output Reduction and Data Compression for System-on-a-Chip." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/43898895869830469288.

Der volle Inhalt der Quelle

Annotation:

碩士<br>國立成功大學<br>電機工程學系碩博士班<br>92<br>With the popularization in SOC designs, it is highly demanded to increase the SOC reliability. The conventional scan architecture is one of the most popular methods for this purpose. However, One of the bottlenecks of testing a system-on-a-chip (SoC) is the long test times arisen from the limited test data bandwidth between the tester and the SOC. Hence, the data compression techniques that reduce the test data volume have received much attention recently. 　　In this thesis, we present a test response compression approach which can greatly reduce the volum

APA, Harvard, Vancouver, ISO und andere Zitierweisen

6

Shen, Wei-Chieh, and 沈瑋傑. "Chip Design of Low Latency Parallel Turbo Decoder with Synchronous Output." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/5y8xbk.

Der volle Inhalt der Quelle

Annotation:

碩士<br>國立臺北科技大學<br>電腦與通訊研究所<br>100<br>Turbo code has excellent decoding performance which is one of close to the Shannon-limit error correction codes. In order to achieve requirement of the modern communication, turbo codes employ multiple SISO decoders by intuition. However, parallel decoders will degrade the correcting performance dramatically as a result of shortening the interleaver length. Thus in this thesis, we proposed a low latency parallel decoding with synchronous output turbo decoder. It can improve both latency and error correction ability in comparison with general parallel turbo

APA, Harvard, Vancouver, ISO und andere Zitierweisen

7

Wang, Tzu-Hao, and 王子豪. "An Integrated Humidity and Temperature Sensor Readout Chip with Digital Output." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/26986627523151876879.

Der volle Inhalt der Quelle

Annotation:

碩士<br>國立暨南國際大學<br>電機工程學系<br>98<br>This work presents a sensor chip which consists of a humidity sensor and a temperature sensor, and a readout circuit with digital output. We use the polyimide as a sensing material. The readout circuit is designed to detect the capacitance and current changes for sensing the humidity and temperature changes, respectively. The chip is implemented using 0.35μm CMOS-MEMS process provided by CIC. The simulation result of digital output for humidity sensor is 685-863 when the capacitance changes from 2.928pF to 3.697pF, and temperature sensor is 50-393 when the tem

APA, Harvard, Vancouver, ISO und andere Zitierweisen

8

Chao, Wen-Chang. "Performance-Driven Block and Input/Output Buffer Placement in Flip-Chip Design." 2004. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-2907200414064000.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

9

Chao, Wen-Chang, and 趙文璋. "Performance-Driven Block and Input/Output Buffer Placement in Flip-Chip Design." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/6565c8.

Der volle Inhalt der Quelle

Annotation:

碩士<br>國立臺灣大學<br>電子工程學研究所<br>92<br>The flip-chip package gives the highest chip density of any packaging methods to support the pad-limited ASIC design. One of the most important characteristics of flip chip designs is that the input/output buffers could be placed anywhere inside a chip. For most practical designs, we have to control the timing of the input/output signals. This can be achieved through controlling the positions of bump balls, input/output buffers, and first-stage/last-stage cells in a flip chip. Specifically, we intend to minimize the path length between blocks and bump balls as

APA, Harvard, Vancouver, ISO und andere Zitierweisen

10

Lin, Cheng Chen, and 林正晨. "Enhancement of Heat Dissipation and Output Efficiency for Power Flip-Chip LEDs." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/44659073715026467929.

Der volle Inhalt der Quelle

Annotation:

碩士<br>長庚大學<br>電子工程學系<br>98<br>Light emitting diode (LED) has the most potential to be mainstream device in the next solid-state lighting illustration. Nowadays, all the LED related researches focus on the topic of high power 1×1 mm2 LED. However, how to dissipate heat generated from LED’s junction is a very important issue for high power LED. In this thesis, goal stub bump which has high thermal conductivity (291 W/m-K) and silicon substrate as sub-mount had been used to achieve Flip-Chip LED fabrication by thermosonic bonding method. Since Flip-Chip LED can quick dissipate heat through goal s

APA, Harvard, Vancouver, ISO und andere Zitierweisen

11

Huang, Po-Shan, and 黃柏舜. "Detour Output Buffer of High-Performance RoCo Decoupled Router for Network-on-Chip." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/96705213767866780491.

Der volle Inhalt der Quelle

Annotation:

碩士<br>國立臺灣大學<br>資訊工程學研究所<br>96<br>The scaling of microchip technologies has enabled large scale systems-on-chip(SoC). With ever increasing complexity of design and IP cores, the inter-communication between IP cores becomes the noteworthy challenge. In order to solve the problem of the data communication, the Network-on-Chip is proposed to deal with the difficulties of inter-communication between IP cores.Network-on-chip (NoC) research addresses global communication in SoC. The low latency design is one of the most important issues to on-chip network design and the implementation of scalable co

APA, Harvard, Vancouver, ISO und andere Zitierweisen

12

Huang, Po-Shan. "Detour Output Buffer of High-Performance RoCo Decoupled Router for Network-on-Chip." 2008. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-2707200808212000.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

13

Lai, Hsin-Chi, and 賴信吉. "Chip Design of Source and Gate Output Buffers for TFT-LCD Driver Applications." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/49245657243399395949.

Der volle Inhalt der Quelle

Annotation:

碩士<br>國立彰化師範大學<br>積體電路設計研究所<br>95<br>In this thesis, we focus on the design of driver circuits for TFT-LCD display. The driver circuits of TFT-LCD are composed of two parts, the source driver and the gate driver. First, we propose a CMOS voltage reference circuit, which is designed for CMOS output buffer or DAC of TFT-LCD source drivers. The temperature-stable voltage reference is based on the same magnitude of gate-source voltage of NMOS and PMOS transistors that provides the temperature-compensation mechanism for the variations of threshold voltage and mobility. It gives a temperature coeffi

APA, Harvard, Vancouver, ISO und andere Zitierweisen

14

Su, Chien-Kuo, and 蘇建國. "A Full On-Chip 1-V Output 50-mV Ultra-Low-Dropout Voltage Regulator." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/47309995389592059200.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

15

Chang, Kuo-Te, and 張國德. "Design of Capacitive Micro Tilt Sensor Chip with Digital Output Using CMOS-MEMS Process." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/05575940836560606290.

Der volle Inhalt der Quelle

Annotation:

碩士<br>國立暨南國際大學<br>電機工程學系<br>100<br>In this thesis, the design of a micro tilt sensor chip is presented. The micro tilt sensor is composed of a micro fluidic channel with two sensing capacitors located at oppositive end of the channel, and readout circuit with a 10-bit successive approximation analog to digital converter (SAR ADC). The inclination of the micro channel filled will fluid cause with changes of the sensing capacitance, and the changes can be readout and converted to 10-bit digital output. The micro tilt sensor chip is implemented using TSMC 0.18μm 1P6M CMOS-MEMS process provided by

APA, Harvard, Vancouver, ISO und andere Zitierweisen

16

Chan, Kuei-Cheng, and 詹貴丞. "Enhancement of Light Output in Flip-Chip Light-Emitting Diodes by Patterned Sapphire Surface." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/24916124757818650642.

Der volle Inhalt der Quelle

Annotation:

碩士<br>崑山科技大學<br>光電工程研究所<br>100<br>Nitride-based high-power flip-chip light emitting diode （FC LED） with patterned sapphire surface （PSS） was proposed and realized. The generated light in the active layer is mostly absorbed by the gradually disappears due to total internal reflection . It is therefore very important that the photons generated from LEDs experience multiple opportunities of escaping to improve the light extraction efficiency. We use the of 0, 30, 60, 120 minutes different dry etching time, compare the optical and electrical properties and observe the graphic changes. Under 350 mA

APA, Harvard, Vancouver, ISO und andere Zitierweisen

17

Chen, Yu-Ting, and 陳育廷. "Design Hardware of A Pseudo Virtual Output Queue CICQ Switching Router for Network on Chip." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/90531754530776656047.

Der volle Inhalt der Quelle

Annotation:

碩士<br>雲林科技大學<br>資訊工程研究所<br>96<br>In accordance with the development of chip, the functional component that can hold at single chip increases day by day. Therefore, the development of system on chip (SoC) in embedded system has already occupied significant position. In the past, the designs of systems always need very kind of functional chip to carry out the structure. The more functions are held, the more components are needed. Consequently, not only increase the volume of products, but also raise the complexity of the design. The designs of the chip originally focus on promoting the efficienc

APA, Harvard, Vancouver, ISO und andere Zitierweisen

18

"Development of Area-Efficient Wide-Bandwidth Output-Capacitorless Low-Dropout Regulators for System-on-Chip Applications." 2016. http://repository.lib.cuhk.edu.hk/en/item/cuhk-1292443.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

19

Hun-Hsien, Chang, and 張恆祥. "DESIGN OF CMOS ON-CHIP ELECTROSTATIC DISCHARGE PROTECTION CIRCUITS AND LOW SIMULTANEOUSLY SWITCHING NOISE OUTPUT BUFFER." Thesis, 1998. http://ndltd.ncl.edu.tw/handle/36511042291952628222.

Der volle Inhalt der Quelle

Annotation:

博士<br>國立交通大學<br>電子工程研究所<br>87<br>The thesis includes two parts: the first is the design on "CMOS on-chip ESDprotection circuits", and the second is the design on "low simultaneousswitching noise output buffer". In the first part of this thesis, there are four robust CMOS on-chip ESDprotection circuits proposed: (1) The first is the compleme ntary-LVTSCR ESDprotection circuit. One LVTSCR device merged with short-channel NMOS and anotherLVTSCR device merged with short-channel PMOS in a complementary style isdesigned to provide effective and direct ESD discharging paths from the input

APA, Harvard, Vancouver, ISO und andere Zitierweisen

20

Yen, Chia Yi, and 顏嘉逸. "Enhancement of the Output Efficiency, Heat Dissipation Capability and ESD Protection for Flip-Chip Power LED Fabrication." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/22007994233903224457.

Der volle Inhalt der Quelle

Annotation:

碩士<br>長庚大學<br>光電工程研究所<br>97<br>At present, all the light emitting diodes (LED) related researches focus on the topic of improving their output efficiency for white light applications. In this work we used ultrasonic flip-chip method to achieve the goals of high efficiency flip-chip power LED fabrication. In this thesis, three important aspects of flip-chip LED fabrication, such as the output efficiency, heat dissipation characteristics and anti electrostatic discharge capability are studied and detailed. First of all, we use silicon and AlN as submouts. For they both have good thermal cond

APA, Harvard, Vancouver, ISO und andere Zitierweisen

21

Peng, Fu-Long, and 彭福龍. "Automatic Substrate Switching Circuit for On-Chip Single-Inductor Dual-Output Switching Converter with Low-Voltage Operation." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/33266685548807569133.

Der volle Inhalt der Quelle

Annotation:

碩士<br>國立交通大學<br>電機學院碩士在職專班電機與控制組<br>96<br>For battery powered portable applications, such as personal digital assistants (PDAs), mobile phones, digital cameras, etc, extending the battery life time and increasing the power conversion efficiency become the two important design issues. Besides, the compact size is also a design requirement in today’s market. Thus, a single inductor is needed to provide multiple outputs for reducing the footprint area of the power module. How to design a compact size, high conversion efficiency and low input supply voltage become a challenge for the power managem

APA, Harvard, Vancouver, ISO und andere Zitierweisen

22

YEH, CHENG-SHIN, and 葉承鑫. "A Study of the Material Model of Complementary inputs for an Insufficient Output of the LED Chip Manufacturing Plant." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/20183578462155545487.

Der volle Inhalt der Quelle

Annotation:

碩士<br>中華大學<br>工業管理學系碩士班<br>102<br>The LED industry involves four kinds of production processes which includeraw material side, upstream, midstream, and downstream. The LED Chip Manufacturers (LED-CM) is a part of the midstream and is a key role of the LED industry. In order to satisfy the various requirements of the downstream, the LED Chip Manufacturers (LED-CMs) are always the type ofMTO production. Their productionprocessesare not only complicated but also uncertain which makes low Hit Target Ratio (HT) and with a lot of variation. Therefore the critical issue of LED manufacturersusually co

APA, Harvard, Vancouver, ISO und andere Zitierweisen

23

Tseng-HsingLin and 林增興. "Improving the Light Output Power of Vertically-Structured and Thin-Film Flip-Chip GaN-Based High Power Light-Emitting Diodes." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/se4d85.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

24

Su, Yi-Ching, and 蘇宜清. "Effect of the Plated Copper Thickness on the Output Power and Reliability for High Efficient Flip-Chip Light-Emitting Diodes." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/37553817067308591176.

Der volle Inhalt der Quelle

Annotation:

碩士<br>明新科技大學<br>電子工程研究所<br>102<br>In this study, the output power and reliability of the different LED chips such as CREE TR5050 and CREE DA1000 with different plate copper thickness are proposed. With the optical characteristic measurements, the flip chip structure of CREE DA1000 emits more output power than the conventional structure of CREE TR5050. With the T3 Ster system measurements, the thermal resistance of CREE DA1000 is lower than the CREE TR5050. On the other hand, the CREE DA1000 chip with 30 μm copper thickness with good thermal characteristic emits more output power than the CREE

APA, Harvard, Vancouver, ISO und andere Zitierweisen

25

Chen, Ssu-Yu, and 陳思妤. "The Design of Wireless Smart Power Outlet System Using System on a Chip." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/58900843305493473648.

Der volle Inhalt der Quelle

Annotation:

碩士<br>中華大學<br>電機工程學系碩士班<br>102<br>In recent years, the smart city, intelligent community, smart home, and energy efficient appliances have been provoked discussion so much by the electronics industry, the construction field. But it did not implement to families, and not be public accepted. The main reason is that the price of such products are too high. Base on this reason, I would try to study how to design a low-cost wireless intelligent power control outlet by using an embedded System on a Chip. Let it can assist monitoring electrical energy and controlling electrical products in the smart

APA, Harvard, Vancouver, ISO und andere Zitierweisen

26

Lu-AnChen and 陳律安. "Design of a Novel High Step-Up Multiple-Output Converter with Digital Control Chip Applied to a Grid-Connected PV System." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/70929538652068176892.

Der volle Inhalt der Quelle

APA, Harvard, Vancouver, ISO und andere Zitierweisen

27

Chen, Wen-Hsien, and 陳文獻. "Research on the Harmonic Signal Observed in the 2.4 GHz RF Output of a WLAN Chip During the Power-On IQ Calibration Process." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/86517377170391396543.

Der volle Inhalt der Quelle

Annotation:

碩士<br>國立交通大學<br>電機學院電信學程<br>102<br>The RF output of a wireless networking chip is found to generate ±80 MHz harmonics, which are located outside the 2.4 GHz ~ 2.5 GHz WLAN operating frequency range, during the power-on IQ calibration process. These harmonics are found to originate from the 80 MHz sampling frequency used by the baseband processor. Experimental results show that the parameters can be adjusted via the TX IQ, RX IQ and VGA (Variable Gain Control Amplifier) parameter adjustment, and thus achieve the purpose of no output harmonic, although these adjustments can solve the harmonic pr

APA, Harvard, Vancouver, ISO und andere Zitierweisen

28

Chen, Yen-Ming, and 陳彥名. "Design and Implementation of New On-Chip Current-Mode DC-DC Buck Converter and Low-Dropout Voltage Regulator with Negative Input-Output Voltage." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/xnpr38.

Der volle Inhalt der Quelle

Annotation:

碩士<br>國立臺北科技大學<br>電腦與通訊研究所<br>95<br>In the first part of this thesis, we present an integrated buck converter using hysteresis current controlled (HCC) techniques without slope compensation. The proposed current sensing circuit is very simple and only consists of few components, which can be designed easily. The designed buck converter using the current sensing circuit and HCC techniques can be stable even if the duty cycle is greater than 50%. The buck converter is implemented with 3.3-V TSMC 0.35μm CMOS DPQM processes, and the chip area is 2.33mm2 with PAD. In the second part of this thesis,

APA, Harvard, Vancouver, ISO und andere Zitierweisen

29

Tsung-HsienYu and 游宗憲. "Improving Light Output Power and Photovoltaic Performance of Thin-film Flip-chip InGaN-based Light-emitting Diodes Through KrF Laser Etching and Chemical Etching." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/tfnqc4.

Der volle Inhalt der Quelle

Annotation:

碩士<br>國立成功大學<br>微電子工程研究所<br>103<br>In this study, an efficient, fast and simple surface texturing process using KrF laser irradiation in conjunction with hot KOH chemical wet etching on the undoped GaN (u-GaN) surface of TFFC-LEDs with a CuW-bonded substrate is demonstrated. The surface roughening scheme that comprises of dome and curved ramp of circular protrusions superimposed by hexagonal cones could be defined a three-fold roughening surface. The proposed surface roughening scheme could effectively improve total internal reflection (TIR) at the u-GaN/air interface. The effects of surface m

APA, Harvard, Vancouver, ISO und andere Zitierweisen

30

Li, Cheng-Ting, and 李政廷. "Design of the Broadband Millimeter-Wave On-Chip Antenna, a Novel Structure of Decreasing Side Lobes and Increasing Frequency Scanning Region for Leaky Wave Antenna and High Isolation Multi-Input Multi-Output Antenna." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/33350568547591856787.

Der volle Inhalt der Quelle

Annotation:

碩士<br>國立交通大學<br>電信工程研究所<br>99<br>This paper proposes three designs of antennas. One is the research of the on-chip antenna, another is the research of the novel structure for the decreasing side-lobe and increasing beam steering range leaky-wave antenna, the other is the search of the low relationship multi-input multi-output antenna (MIMO). For the first topic, a broadband millimeter-wave on-chip antenna is presented here. We design the proposed antenna by using the construction of monopole antenna. To reach the End-Fired radiation pattern, the reflector of the Yagi-Uda construction is used i

APA, Harvard, Vancouver, ISO und andere Zitierweisen

Wir bieten Rabatte auf alle Premium-Pläne für Autoren, deren Werke in thematische Literatursammlungen aufgenommen wurden. Kontaktieren Sie uns, um einen einzigartigen Promo-Code zu erhalten!