Thematische Bibliographien / Trench transistor

Inhaltsverzeichnis

  1. Zeitschriftenartikel
  2. Dissertationen
  3. Bücher
  4. Buchteile
  5. Konferenzberichte
  6. Berichte der Organisationen

Auswahl der wissenschaftlichen Literatur zum Thema „Trench transistor“

Autor: Grafiati
Veröffentlicht am 25. Mai 2024
Zuletzt aktualisiert am 31. Juli 2025

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Zeitschriftenartikel zum Thema "Trench transistor"

1

Shichijo, H., S. K. Banerjee, S. D. S. Malhi, et al. "Trench transistor DRAM cell." IEEE Electron Device Letters 7, no. 2 (1986): 119–21. http://dx.doi.org/10.1109/edl.1986.26313.

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Gupta, Aakashdeep, K. Nidhin, Suresh Balanethiram, et al. "Static Thermal Coupling Factors in Multi-Finger Bipolar Transistors: Part I—Model Development." Electronics 9, no. 9 (2020): 1333. http://dx.doi.org/10.3390/electronics9091333.

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In this part, we propose a step-by-step strategy to model the static thermal coupling factors between the fingers in a silicon based multifinger bipolar transistor structure. First we provide a physics-based formulation to find out the coupling factors in a multifinger structure having no-trench isolation (cij,nt). As a second step, using the value of cij,nt, we propose a formulation to estimate the coupling factor in a multifinger structure having only shallow trench isolations (cij,st). Finally, the coupling factor model for a deep and shallow trench isolated multifinger device (cij,dt) is p
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Dai, Tian Xiang, A. B. Renz, Luyang Zhang, et al. "Design and Optimisation of Schottky Contact Integration in a 4H-SiC Trench MOSFET." Materials Science Forum 1004 (July 2020): 808–13. http://dx.doi.org/10.4028/www.scientific.net/msf.1004.808.

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Planar Schottky contact and various trench Schottky contacts have been integrated into the edge termination region of a 4H-SiC trench metal-oxide-semiconductor field-effect-transistor (MOSFET). The forward and reverse characteristics of various design splits have been benchmarked to determine the optimum method of the Schottky contact integration. As a result, the trench Schottky diode with Schottky metal contact in both the planar surface and the trench sidewall surface has been able to offer the best performance.
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Mukherjee, Kalparupa, Carlo De Santi, Matteo Borga, et al. "Challenges and Perspectives for Vertical GaN-on-Si Trench MOS Reliability: From Leakage Current Analysis to Gate Stack Optimization." Materials 14, no. 9 (2021): 2316. http://dx.doi.org/10.3390/ma14092316.

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The vertical Gallium Nitride-on-Silicon (GaN-on-Si) trench metal-oxide-semiconductor field effect transistor (MOSFET) is a promising architecture for the development of efficient GaN-based power transistors on foreign substrates for power conversion applications. This work presents an overview of recent case studies, to discuss the most relevant challenges related to the development of reliable vertical GaN-on-Si trench MOSFETs. The focus lies on strategies to identify and tackle the most relevant reliability issues. First, we describe leakage and doping considerations, which must be considere
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Banerjee, S., and D. M. Bordelon. "A model for the trench transistor." IEEE Transactions on Electron Devices 34, no. 12 (1987): 2485–92. http://dx.doi.org/10.1109/t-ed.1987.23339.

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6

Wang, Bo. "Analysis of base characteristics of trench gate field termination IGBT." E3S Web of Conferences 237 (2021): 02023. http://dx.doi.org/10.1051/e3sconf/202123702023.

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Trench gate structure represents the latest structure of Insulated Gate Bipolar Transistor(IGBT). Because there are great differences in model analysis coordinate system and carrier transport between trench gate structure and planar gate structure, the modeling method using planar gate structure will inevitably have great deviation. Based on the characteristics of trench gate structure and model analysis coordinate system, the base region is divided into PNP and PIN by considering the two-dimensional effect of carriers. According to whether the trench of PIN part can be covered by depletion la
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Manosukritkul, Phasapon, Amonrat Kerdpardist, Montree Saenlamool, Ekalak Chaowicharat, Amporn Poyai, and Wisut Titiroongruang. "An Improvement of the Breakdown Voltage Characteristics of NPT-TIGBT by Using a P-Buried Layer." Advanced Materials Research 717 (July 2013): 158–63. http://dx.doi.org/10.4028/www.scientific.net/amr.717.158.

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In this paper, we introduced a P-buried (Pb) layer under trench gate which relieved the electric field crowding in the Non Punch Through Trench gate Insulated Gate Bipolar Transistor (NPT-TIGBT) structure. The Pblayer, with carrier concentration of 5x1016cm-3, was created underneath the trench gate within the n-drift layer. In this way, the concentration of electric field at the trench bottom corner decreased. As a result, the breakdown voltage characteristics of NPT-TIGBT improved. The structures were proposed and verified by T-CAD Sentuarus simulation. From the simulation results, the breakd
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Chen, Q., B. You, A. Q. Huang, and J. K. O. Sin. "A new trench base-shielded bipolar transistor." IEEE Transactions on Electron Devices 47, no. 8 (2000): 1662–66. http://dx.doi.org/10.1109/16.853045.

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9

Yang, Ling Ling. "A Novel Structure Trench IGBT with Full Hole-Barrier Layer." Applied Mechanics and Materials 543-547 (March 2014): 757–61. http://dx.doi.org/10.4028/www.scientific.net/amm.543-547.757.

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A Full Hole-barrier Trench gate Insulated Gate Bipolar Transistor (FH-TIGBT) device structure is proposed for the first time. Compared with Carrier Stored Trench IGBT (CSTBT), which adds a carrier stored n layer between p base and n base in Trench IGBT (TIGBT), the new structure appends an n region located in the bottom of the trench gate. The result of Process and device simulations shows that the proposed device has lowered saturation voltage and larger capability of carrying current compared to either conventional trench IGBT or CSTBT. And the characteristics of turn-off time and breakdown
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Shu, Lei, Huai-Lin Liao, Zi-Yuan Wu, et al. "Effects of Gamma Irradiation on Switching Characteristics of SiC MOSFET Power Devices of Different Structures." Electronics 12, no. 10 (2023): 2194. http://dx.doi.org/10.3390/electronics12102194.

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The switching characteristics of silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) power devices of different structures were experimented after exposure to a gamma irradiation environment. The experimental results for on-state were studied. The comparisons are shown for SiC MOSFET power devices with planar, trench and double trench structures tested for total ionizing dose (TID). A higher degradation of the switching characteristics was observed for the double trench structure. The physical mechanisms for these switching characteristics variations were analyzed.
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Dissertationen zum Thema "Trench transistor"

1

Gay, Roméric. "Développement de composants analogiques embarqués dans des microcontrôleurs destinés à l'Internet des Objets (loT)." Electronic Thesis or Diss., Aix-Marseille, 2022. http://www.theses.fr/2022AIXM0218.

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L’objectif de ces travaux de thèse a été d'améliorer les performances, le coût et la surface de silicium occupés par un microcontrôleur fabriqué sur la base d’une technologie mémoire embarquée CMOS (eNVM) 40 nm. Ces améliorations ont été réalisées grâce au développement de nouvelles architectures de transistors adaptées au besoin du marché de l’IoT. Dans une première partie, le contexte dans lequel s’inscrit cette thèse est exposé par la présentation des limites technologiques et économiques de technologie CMOS. Dans une deuxième partie, le procédé de fabrication eNVM ainsi que l’architecture
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Forsberg, Markus. "Chemical Mechanical Polishing of Silicon and Silicon Dioxide in Front End Processing." Doctoral thesis, Uppsala : Acta Universitatis Upsaliensis : Univ.-bibl. [distributör], 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-4304.

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Ramadout, Benoit. "Capteurs d’images CMOS à haute résolution à Tranchées Profondes Capacitives." Thesis, Lyon 1, 2010. http://www.theses.fr/2010LYO10068.

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Les capteurs d'images CMOS ont connu au cours des six dernières années une réduction de la taille des pixels d'un facteur quatre. Néanmoins, cette miniaturisation se heurte à la diminution rapide du signal maximal de chaque pixel et à l'échange parasite entre pixels (diaphotie). C'est dans ce contexte qu'a été développé le Pixel à Tranchées Profondes Capacitives et Grille de Transfert verticale (pixel CDTI+VTG). Basé sur la structure d'un pixel « 4T », il intègre une isolation électrique par tranchées, une photodiode profonde plus volumineuse et une grille verticale permettant le stockage prof
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Maglie, Rodolphe de. "Modélisation de différentes technologies de transistors bipolaires à grille isolée pour la simulation d'applications en électronique de puissance." Toulouse 3, 2007. https://tel.archives-ouvertes.fr/tel-00153597.

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L'analyse et la conception des systèmes en électronique de puissance nécessitent la prise en compte de phénomènes complexes propres à chaque composant du système mais aussi en accord avec son environnement. La description précise du comportement d'un système passe par la simulation utilisant des modèles suffisamment précis de tous ces composants. Dans notre étude, les modèles basés sur la physique des semiconducteurs permettent de décrire le comportement de la charge stockée dans la base large et peu dopée des composants bipolaires. Cette description fine est indispensable à la bonne précision
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Ng, Chun Wai. "On the inversion and accumulation layer mobilities in N-channel trench DMOSFETS /." View abstract or full-text, 2005. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202005%20NG.

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6

Heinle, Ulrich. "Vertical High-Voltage Transistors on Thick Silicon-on-Insulator." Doctoral thesis, Uppsala universitet, Fasta tillståndets elektronik, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-3179.

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More and more electronic products, like battery chargers and power supplies, as well as applications in telecommunications and automotive electronics are based on System-on-Chip solutions, where signal processing and power devices are integrated on the same chip. The integration of different functional units offers many advantages in terms of reliability, reduced power consumption, weight and space reduction, leading to products with better performance at a hopefully lower price. This thesis focuses on the integration of vertical high-voltage double-diffused MOS transistors (DMOSFETs) on Silic
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Melul, Franck. "Développement d'une nouvelle génération de point mémoire de type EEPROM pour les applications à forte densité d'intégration." Electronic Thesis or Diss., Aix-Marseille, 2022. http://www.theses.fr/2022AIXM0266.

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L’objectif de ces travaux de thèse a été de développer une nouvelle génération de point mémoire de type EEPROM pour les applications à haute fiabilité et à haute densité d’intégration. Dans un premier temps, une cellule mémoire très innovante développée par STMicroelectronics – eSTM (mémoire à stockage de charges de type Splitgate avec transistor de sélection vertical enterré) – a été étudiée comme cellule de référence. Dans une deuxième partie, dans un souci d’améliorer la fiabilité de la cellule eSTM et de permettre une miniaturisation plus agressive de la cellule EEPROM, une nouvelle archit
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Grimminger, Marsha Loth. "PERIODIC TRENDS IN STRUCTURE FUNCTION RELATIONSHIP OF ORGANIC HETEROACENES." UKnowledge, 2011. http://uknowledge.uky.edu/gradschool_diss/850.

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Our group has previously shown that small changes to molecular structure result in large changes to device properties and stability in organic electronic applications. By functionalizing aromatic heteroacenes with group 14 and group 16 elements, it is possible to control morphology and improve stability for a variety of applications such as thin film transistors and solar cells. Functionalization within the heteroacene core led to changes in electronic structure as observed by electrochemistry and light absorption. By substituting down the periodic table, the carbon heteroatom bond length incr
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Tavernier, Aurélien. "Développement d'un procédé innovant pour le remplissage des tranchées d'isolation entre transistors des technologies CMOS avancées." Phd thesis, Université de Grenoble, 2014. http://tel.archives-ouvertes.fr/tel-00987019.

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Réalisées au début du processus de fabrication des circuits intégrés, les tranchées d'isolation permettent d'éviter les fuites de courant latérales qui pourraient avoir lieu entre les transistors. Les tranchées sont remplies par un film d'oxyde de silicium réalisé par des procédés de dépôt chimiques en phase vapeur (aussi appelés CVD). Le remplissage des tranchées est couramment réalisé par un procédé CVD à pression sub-atmosphérique (SACVD TEOS/O3). Cependant, la capacité de remplissage de ce procédé pour les nœuds technologiques CMOS 28 nm et inférieurs est dégradée à cause de profils trop v
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Tai, Shih-Hsiang, and 戴士翔. "Optimal Design of Trench Gate Insulted Gate Bipolar Transistor." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/99755982922692722594.

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碩士<br>國立臺灣科技大學<br>電子工程系<br>90<br>In recent years, the performance and fabrication of IGBT’s have been significantly improved and the application field of IGBT have widely been expending, especially in high power electronic device. It is reported that the Trench-Gate IGBT has superior characteristics in power loss compared to conventional planar IGBT. In this thesis, the Trench-Gate IGBT has a high power gain, high input impedance, and high switching speed. Due to these advantage, the effort to improve the Trench-Gate IGBT performances operating above 600V and 100A/cm² are the goal in this thes
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Bücher zum Thema "Trench transistor"

1

Bi, Zhenxing. Shallow Trench Isolation Recess Process Flow for Vertical Field Effect Transistor Fabrication: United States Patent 9985021. Independently Published, 2020.

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Buchteile zum Thema "Trench transistor"

1

Bharti, Deepshikha, and Aminul Islam. "U-Shaped Gate Trench Metal Oxide Semiconductor Field Effect Transistor: Structures and Characteristics." In Nanoscale Devices. CRC Press, 2018. http://dx.doi.org/10.1201/9781315163116-4.

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Erlbacher, Tobias. "Lateral Power Transistors with Trench Patterns." In Power Systems. Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-00500-3_7.

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3

Dyakonov, M. I., and M. S. Shur. "Field Effect Transistor as Electronic Flute." In Future Trends in Microelectronics. Springer Netherlands, 1996. http://dx.doi.org/10.1007/978-94-009-1746-0_22.

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Horowitz, G. "Organic Transistors — Present and Future." In Future Trends in Microelectronics. Springer Netherlands, 1996. http://dx.doi.org/10.1007/978-94-009-1746-0_28.

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5

Ghannam, M., J. Nijs, and R. Mertens. "Trends in Heterojunction Silicon Bipolar Transistors." In Ultra-Fast Silicon Bipolar Technology. Springer Berlin Heidelberg, 1988. http://dx.doi.org/10.1007/978-3-642-74360-3_7.

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Erlbacher, Tobias. "Lateral Power Transistors Combining Planar and Trench Gate Topologies." In Power Systems. Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-00500-3_8.

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7

de Castro, Ana Cristina Honorato, Suchismita Guha, and Wendel Andrade Alves. "Organic Electrochemical Transistors in Bioanalytical Chemistry." In Tools and Trends in Bioanalytical Chemistry. Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-82381-8_16.

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Mastrapasqua, M., C. A. King, P. R. Smith, and M. R. Pinto. "Charge Injection Transistor and Logic Elements in Si/Si1−xGex Heterostructures." In Future Trends in Microelectronics. Springer Netherlands, 1996. http://dx.doi.org/10.1007/978-94-009-1746-0_34.

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Zaumseil, Jana. "Recent Trends in Light-Emitting Organic Field-Effect Transistors." In Organic Electronics. Wiley-VCH Verlag GmbH & Co. KGaA, 2013. http://dx.doi.org/10.1002/9783527650965.ch08.

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10

Manju, C. S., N. Poovizhi, and R. Rajkumar. "Power Efficient Pulse Triggered Flip-Flop Design Using Pass Transistor Logic." In Emerging Trends in Computing and Expert Technology. Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-32150-5_5.

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Konferenzberichte zum Thema "Trench transistor"

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Chan, Lee Chao, Kao Yi Sheng, Yen Shih Keng, Xie Shang Rong, and Chien Feng Tso. "600V Insulated Gate Bipolar Transistor Design for Improving Breakdown Voltage in Trench Floating P-Well Charge Storage Layer Gate Bipolar Transistor." In 2024 7th International Conference on Electronics, Communications, and Control Engineering (ICECC). IEEE, 2024. http://dx.doi.org/10.1109/icecc63398.2024.00016.

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Vinciguerra, Vincenzo, Filippo Sabatini, Mohamed Boutaleb, et al. "Finite Element Analysis of the Asymmetric Warpage Induced by the Oxidation Process in Trench Insulated Gate Bipolar Transistor (Trench IGBT) 12” Si Patterned Wafers." In 2025 26th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE). IEEE, 2025. https://doi.org/10.1109/eurosime65125.2025.11006629.

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Jeyanathan, Josephine Selle, Afrid Shaik, J. Charles Pravin, and K. Nithin Chowdary. "Simulation of WO3 Thin Film Transistor for Biosensors." In 2025 5th International Conference on Trends in Material Science and Inventive Materials (ICTMIM). IEEE, 2025. https://doi.org/10.1109/ictmim65579.2025.10988043.

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B V, Srividya, Manasi V. Varma, Nidhi Mukesh, Ishwarya S, and Kavita S. "n-Bit ALU using CMOS Forced Transistor Stacking." In 2025 5th International Conference on Trends in Material Science and Inventive Materials (ICTMIM). IEEE, 2025. https://doi.org/10.1109/ictmim65579.2025.10988010.

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Sassi, Silpa, and Anjana Devi S. "Comparator Design using Carbon Nanotube Field-Effect Transistors." In 2025 2nd International Conference on Trends in Engineering Systems and Technologies (ICTEST). IEEE, 2025. https://doi.org/10.1109/ictest64710.2025.11042709.

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Zhang, Jinping, Pengjiao Wang, Rongrong Zhu, Xiang Xiao, Zehong Li, and Bo Zhang. "High Performance Carrier Stored Trench Bipolar Transistor with Shield Emitter Trench." In 2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT). IEEE, 2020. http://dx.doi.org/10.1109/icsict49897.2020.9278308.

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Richardson, W. F., D. M. Bordelon, G. P. Pollack, et al. "A trench transistor cross-point DRAM cell." In 1985 International Electron Devices Meeting. IRE, 1985. http://dx.doi.org/10.1109/iedm.1985.191075.

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8

Chen, Q., and J. K. O. Sin. "A new trench base-shielded bipolar transistor." In Proceedings of International Symposium on Power Semiconductor Devices and IC's. IEEE, 1998. http://dx.doi.org/10.1109/ispsd.1998.702661.

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Ruprecht, Michael W., Shengmin Wen, and Rolf-P. Vollertsen. "Sample Preparation for Vertical Transistors in DRAM." In ISTFA 2002. ASM International, 2002. http://dx.doi.org/10.31399/asm.cp.istfa2002p0307.

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Abstract This paper describes a newly developed preparation technique for vertical transistors in DRAM. The recently developed concept of DRAM cells combining a deep trench storage capacitor and a vertical access transistor promises a significant reduction in cell size. In the vertical transistor concept two gates are used to access one storage cell, which creates a challenge for the analysis of gate oxide fails. A gate oxide breakdown is determined and localized in the memory array by electrical probing and photoemission microscopy. The preparation technique combines focused ion beam (FIB) mi
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Spulber, O. "The Trench Planar Insulated Gate Bipolar Transistor (TPIGBT)." In IEE Colloquium Recent Advances in Power Devices. IEE, 1999. http://dx.doi.org/10.1049/ic:19990603.

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Berichte der Organisationen zum Thema "Trench transistor"

1

Pasupuleti, Murali Krishna. Neuromorphic Nanotech: 2D Materials for Energy-Efficient Edge Computing. National Education Services, 2025. https://doi.org/10.62311/nesx/rr325.

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Abstract The demand for energy-efficient, real-time computing is driving the evolution of neuromorphic computing and edge AI systems. Traditional silicon-based processors struggle with power inefficiencies, memory bottlenecks, and scalability limitations, making them unsuitable for next-generation low-power AI applications. This research report explores how 2D materials, such as graphene, transition metal dichalcogenides (TMDs), black phosphorus, and MXenes, are enabling the development of neuromorphic architectures that mimic biological neural networks for high-speed, ultra-low-power computat
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