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Dissertationen zum Thema „Trench transistor“

Autor: Grafiati

Veröffentlicht am 25. Mai 2024

Zuletzt aktualisiert am 31. Juli 2025

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1

Gay, Roméric. "Développement de composants analogiques embarqués dans des microcontrôleurs destinés à l'Internet des Objets (loT)." Electronic Thesis or Diss., Aix-Marseille, 2022. http://www.theses.fr/2022AIXM0218.

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L’objectif de ces travaux de thèse a été d'améliorer les performances, le coût et la surface de silicium occupés par un microcontrôleur fabriqué sur la base d’une technologie mémoire embarquée CMOS (eNVM) 40 nm. Ces améliorations ont été réalisées grâce au développement de nouvelles architectures de transistors adaptées au besoin du marché de l’IoT. Dans une première partie, le contexte dans lequel s’inscrit cette thèse est exposé par la présentation des limites technologiques et économiques de technologie CMOS. Dans une deuxième partie, le procédé de fabrication eNVM ainsi que l’architecture

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2

Forsberg, Markus. "Chemical Mechanical Polishing of Silicon and Silicon Dioxide in Front End Processing." Doctoral thesis, Uppsala : Acta Universitatis Upsaliensis : Univ.-bibl. [distributör], 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-4304.

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3

Ramadout, Benoit. "Capteurs d’images CMOS à haute résolution à Tranchées Profondes Capacitives." Thesis, Lyon 1, 2010. http://www.theses.fr/2010LYO10068.

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Les capteurs d'images CMOS ont connu au cours des six dernières années une réduction de la taille des pixels d'un facteur quatre. Néanmoins, cette miniaturisation se heurte à la diminution rapide du signal maximal de chaque pixel et à l'échange parasite entre pixels (diaphotie). C'est dans ce contexte qu'a été développé le Pixel à Tranchées Profondes Capacitives et Grille de Transfert verticale (pixel CDTI+VTG). Basé sur la structure d'un pixel « 4T », il intègre une isolation électrique par tranchées, une photodiode profonde plus volumineuse et une grille verticale permettant le stockage prof

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4

Maglie, Rodolphe de. "Modélisation de différentes technologies de transistors bipolaires à grille isolée pour la simulation d'applications en électronique de puissance." Toulouse 3, 2007. https://tel.archives-ouvertes.fr/tel-00153597.

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L'analyse et la conception des systèmes en électronique de puissance nécessitent la prise en compte de phénomènes complexes propres à chaque composant du système mais aussi en accord avec son environnement. La description précise du comportement d'un système passe par la simulation utilisant des modèles suffisamment précis de tous ces composants. Dans notre étude, les modèles basés sur la physique des semiconducteurs permettent de décrire le comportement de la charge stockée dans la base large et peu dopée des composants bipolaires. Cette description fine est indispensable à la bonne précision

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5

Ng, Chun Wai. "On the inversion and accumulation layer mobilities in N-channel trench DMOSFETS /." View abstract or full-text, 2005. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202005%20NG.

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6

Heinle, Ulrich. "Vertical High-Voltage Transistors on Thick Silicon-on-Insulator." Doctoral thesis, Uppsala universitet, Fasta tillståndets elektronik, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-3179.

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More and more electronic products, like battery chargers and power supplies, as well as applications in telecommunications and automotive electronics are based on System-on-Chip solutions, where signal processing and power devices are integrated on the same chip. The integration of different functional units offers many advantages in terms of reliability, reduced power consumption, weight and space reduction, leading to products with better performance at a hopefully lower price. This thesis focuses on the integration of vertical high-voltage double-diffused MOS transistors (DMOSFETs) on Silic

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7

Melul, Franck. "Développement d'une nouvelle génération de point mémoire de type EEPROM pour les applications à forte densité d'intégration." Electronic Thesis or Diss., Aix-Marseille, 2022. http://www.theses.fr/2022AIXM0266.

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L’objectif de ces travaux de thèse a été de développer une nouvelle génération de point mémoire de type EEPROM pour les applications à haute fiabilité et à haute densité d’intégration. Dans un premier temps, une cellule mémoire très innovante développée par STMicroelectronics – eSTM (mémoire à stockage de charges de type Splitgate avec transistor de sélection vertical enterré) – a été étudiée comme cellule de référence. Dans une deuxième partie, dans un souci d’améliorer la fiabilité de la cellule eSTM et de permettre une miniaturisation plus agressive de la cellule EEPROM, une nouvelle archit

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8

Grimminger, Marsha Loth. "PERIODIC TRENDS IN STRUCTURE FUNCTION RELATIONSHIP OF ORGANIC HETEROACENES." UKnowledge, 2011. http://uknowledge.uky.edu/gradschool_diss/850.

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Our group has previously shown that small changes to molecular structure result in large changes to device properties and stability in organic electronic applications. By functionalizing aromatic heteroacenes with group 14 and group 16 elements, it is possible to control morphology and improve stability for a variety of applications such as thin film transistors and solar cells. Functionalization within the heteroacene core led to changes in electronic structure as observed by electrochemistry and light absorption. By substituting down the periodic table, the carbon heteroatom bond length incr

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9

Tavernier, Aurélien. "Développement d'un procédé innovant pour le remplissage des tranchées d'isolation entre transistors des technologies CMOS avancées." Phd thesis, Université de Grenoble, 2014. http://tel.archives-ouvertes.fr/tel-00987019.

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Réalisées au début du processus de fabrication des circuits intégrés, les tranchées d'isolation permettent d'éviter les fuites de courant latérales qui pourraient avoir lieu entre les transistors. Les tranchées sont remplies par un film d'oxyde de silicium réalisé par des procédés de dépôt chimiques en phase vapeur (aussi appelés CVD). Le remplissage des tranchées est couramment réalisé par un procédé CVD à pression sub-atmosphérique (SACVD TEOS/O3). Cependant, la capacité de remplissage de ce procédé pour les nœuds technologiques CMOS 28 nm et inférieurs est dégradée à cause de profils trop v

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10

Tai, Shih-Hsiang, and 戴士翔. "Optimal Design of Trench Gate Insulted Gate Bipolar Transistor." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/99755982922692722594.

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碩士<br>國立臺灣科技大學<br>電子工程系<br>90<br>In recent years, the performance and fabrication of IGBT’s have been significantly improved and the application field of IGBT have widely been expending, especially in high power electronic device. It is reported that the Trench-Gate IGBT has superior characteristics in power loss compared to conventional planar IGBT. In this thesis, the Trench-Gate IGBT has a high power gain, high input impedance, and high switching speed. Due to these advantage, the effort to improve the Trench-Gate IGBT performances operating above 600V and 100A/cm² are the goal in this thes

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11

HUA, CHEN PING, and 陳秉樺. "Asymmetric Gate with Trench Structure for Juntionless Field-Effect Transistor." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/78037389074916331457.

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碩士<br>國立聯合大學<br>電子工程學系碩士班<br>103<br>This study describes the fabrication of a trench junctionless field-effect transistor (trench JL-FET) and asymmetric gate trench junctionless field-effect transistor (AG trench JL-FET). This study uses the dry oxidation to form the ultra-thin channel instead of directly depositing the thin-film as the poly-Si channel in JL-FET and it could get larger grain size and less grain boundary than directly depositing the thin-film. The dry etching process is utilized firstly in the fabrication of trench JL-FET is used to form a trench and define the channel thicknes

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12

Lai, Guan-Fu, and 賴冠甫. "Design of Nanoscale Lateral Trench-Type Tunneling Field-Effect Transistor." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/28823414545853161968.

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碩士<br>國立臺灣科技大學<br>電子工程系<br>103<br>In the progress of the electronics industry, the scaled down of the conventional MOSFET device will emerge some reliability problems, such as short-channel effect, hot-carrier effect, and gate-induced-drain leakage (GIDL). Tunneling Field Effect transistors (TFETs) are semiconductor devices that carry current via inter-band source-to- channel tunneling rather than by carrier transport over the source barrier. In other words, TFET has the immunity from these problems in high scaling fabrication due to its operation mechanism is different from the MOSFET device.

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13

LI, DONG-QI, and 李東奇. "The simulation and modeling of a trench-isolated MOS transistor." Thesis, 1990. http://ndltd.ncl.edu.tw/handle/91684391077102611194.

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14

Liu, Chu-Kuang, and 劉莒光. "Power Trench Junction Field Effect Transistor Integrated with Schottky Barrier Diode." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/49020093428820678056.

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碩士<br>國立交通大學<br>理學院碩士在職專班應用科技學程<br>97<br>Nowadays, Power MOSFETs are dominant products of switching converters in the application field of power supply. For high power conversion efficiency and high frequency operating consideration, adopting synchronous buck converter (SBC) design would meet this requirement. However, for the low-side switch device of SBC, there are still some drawback characteristics such as physical limit of on-state resistance of channel, high power loss during the dead time due to the inherent PN body diode etc. In this study, a novel structure of power trench junction

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15

Lee, Lung-Chieh, and 李龍杰. "Design and Simulation of SiC Dual Trench Accumulation Channel Field Effect Transistor (ACCUFET) Structure." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/87879839116508197352.

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碩士<br>國立臺灣大學<br>工程科學及海洋工程學研究所<br>102<br>To improve the energy conversion efficiency of power electronic systems, it is necessary to reduce the power losses during switching and on-state conduction of power semiconductor devices. SiC power devices are the best candidates because they have excellent material properties for high power density and high temperature applications. Among all sorts of power devices, SiC power MOSFET attracts the most attention because of its high frequency switching capability. However, low channel mobility, high interface state density as well as inferior oxide reliab

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16

Lin, Yang-You, and 林揚祐. "Lateral trench-type insulated-gate bipolar transistor triggered by using tunneling-field-effect structure." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/52173970303839533036.

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碩士<br>國立臺灣科技大學<br>電子工程系<br>103<br>The lateral insulated-gate bipolar transistor power device has been proposed that a smaller on-state voltage drop compared with metal-oxide-semiconductor field-effect transistor power device and tunneling-field-effect transistor power device. Because the P+-anode/N- drift junction of the device turn on, the large series resistance in the drift region can be effectively reduced. In this thesis, the results of different gate-positions of planar TFET-IGBT have been discussed, there is a trade-off between the electric field in P+-cathode/N- drift junction and N- d

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17

Wang, Yi-Ting, and 王怡婷. "A Design and Analysis of 600V Trench Gate Reverse Conducting Insulated Gate Bipolar Transistor." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/47047701468172285686.

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碩士<br>國立中央大學<br>電機工程研究所<br>100<br>Most of the development trend of electronic products has always been to achieve high performance and multi-function by consuming more power. In the energy industry equipment used by semiconductor, power semiconductors, the proportion of over 50%. Power semiconductors are widely used in the fields of home appliances, computers, automotive and railway. Since these applications are expected to expand the popularity of the use of power semiconductors has risen, the power semiconductor market will expand year by year growth. With crude oil prices rising year by yea

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18

Wu, Min-Hsin, and 吳明欣. "Study of Ultra-Thin Body Junctionless Poly-Si Fin Field-Effect Transistor with a Trench Structure." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/12621370582891883921.

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碩士<br>國立清華大學<br>工程與系統科學系<br>102<br>In this study, we describe the fabrication of a trench junctionless poly-Si field-effect transistor (trench JL-FET) with 2.4 nm ultra-thin channels. The dry etching process is utilized firstly in the fabrication of trench JL-FET is used to form a trench and define the channel thickness (TCH) and the gate length (LG) simultaneously. The trench structure was successfully and easily integrated into the JL-FET device. This work use the dry etching to form the ultra-thin channel instead of directly depositing the thin-film as the poly-Si channel in JL FETs and it

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19

Chiu, Hsien-Nan, and 邱憲楠. "Characteristics of a New Trench Oxide Layer Polysilicon Thin-Film Transistor and its 1T-DRAM Applications." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/62184136431112541817.

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碩士<br>國立中山大學<br>電機工程學系研究所<br>98<br>In this thesis, we propose a simple trench oxide layer polysilicon thin-film Transistor (TO TFT) process and the self-heating effects can be significantly reduced because of its structural advantages. According to the ISE-TCAD simulation results, our proposed TO TFT structure has novel features as follows: 1. The buried oxide and the isolation oxide are carried out simultaneously in order to achieve a goal of simple process. 2. The trench design is used to improve both the sensing current windows (~ 84%) and the retention time (~ 57%). 3. The thermal stabilit

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20

CHO, YU-HSIANG, and 卓裕翔. "A Novel Design of Four-Masks Bottom-Gate Poly-Si Thin Film Transistor and Study of High Voltage Planar-Gate Trench-Source VDMOSFET." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/dgax22.

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碩士<br>逢甲大學<br>電子工程學系<br>107<br>Most of the early monitors were cathode ray tube(CRT) screens, but cathode ray tubes have the disadvantages of large volume, heavy weight, high radiation and poor image quality. In recent years, with the polycrystalline germanium film transistor Thin Film Transistor(TFT) has a large number of research and structural breakthroughs, and its sophisticated technology is widely used in Active Matrix Liquid Crystal Display(AMLCD) and Three Dimensional-integrated Circuit(3D-IC). Compared with amorphous bismuth thin film transistors, polycrystalline germanium thin film t

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21

Liao, Li-Feng, and 廖麗鳳. "Structure Design of Trench Type Insulated-Gate Bipolar Transistors." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/44730090880226936125.

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碩士<br>國立臺灣科技大學<br>電子工程系<br>102<br>Power devices act as a switch to control the power delivered to the load. In this thesis, a novel trench-type insulated-gate bipolar transistor device has been proposed without p-n-p-n latch-up phenomenon, which shows better characteristics as compared with the conventional trench-gate power MOSFET. Moreover, by using the design of device structure and/or fabrication process to enhance the band-to-band tunneling or increase the electric field in drift region, the on-current of the trench-gate TFET-IGBT can be effectively improved. Accordingly, proper p+ sourc

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22

Liu, Hsu-Tang, and 劉旭唐. "Investigations of Rounding Corner Trench Structure for Organic Thin Film Transistors." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/43347580576415006054.

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碩士<br>國立暨南國際大學<br>電機工程學系<br>102<br>In this work, the organic thin film transistors (OTFTs) with periodical groove channels were fabricated by nano imprint lithography (NIL) technology. The periodical groove channels with sharp and rounded corners were first fabricated. Then, the device performances with various periods and different morphologies of groove channels were studied. The periodical groove channels were fabricated, on n+-Si substrate, by nano imprint technology. The sharp corners were rounded by thermal oxidation. Then the dielectric layers, HfO2/SiO2, were deposited by MOCVD and the

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23

Lin, Ko Wei, and 林个惟. "Study of Trench Junctionless Fin Field-Effect Transistors with Different Gate Structure." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/dv4bx4.

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碩士<br>國立清華大學<br>工程與系統科學系<br>103<br>With the development of Moore's Law, short channel effect (SCE) has been always a serious issue for CMOS technology. This study, we describe the fabrication of a trench junctionless poly-Si fin field-effect transistor (trench JL-FET) to further improve short channel effect. This trench JL Fin-FET enhances the gate control over its silicon channel. The trench JL Fin-FET can easily to form the ultra-thin channel thickness (TCH) and control the gate length (LG) by dry etching. And, having the heavily doping channel and source/drain (S/D) regions, the SCE in JL-F

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24

Wang, Cheng Ping, and 王政平. "Study of Hybrid Poly-Si Channel Junctionless Fin Field-Effect Transistors with Trench Structure." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/j4867d.

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碩士<br>國立清華大學<br>工程與系統科學系<br>103<br>Modern electronic devices become more and more useful, emphasizing on multifunctional, small size, light weight, etc. The rapid development in electronic industries has led to considerable increases in consumer’s purchasing desire, and triggered electronics industry to improve its products. However, the expectation of transistors in scaling suffered more and more difficult to design, whether the short channel effect in devices or the challenge of process are very important research issues. In this thesis, the hybrid junctionless field-effect-transistors with

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25

Cheng, Che Hsiang, and 鄭哲翔. "Hybrid p-Channel Poly-Si Junctionless Field-Effect Transistors with Trench and Gate-All-Around Structure." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/44388217998306619184.

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碩士<br>國立清華大學<br>工程與系統科學系<br>104<br>Modern electronic devices become more and more useful, emphasizing on multifunctional, small size, light weight, etc. as the feature size of logic device has been scaled continuously, conventional inversion-mode Metal-Oxide-Semiconductor Field-Effect-Transistors (MOSFETs) face a lot of challenges such as random dopant fluctuation, physical limitation and short channel effect (SCE). Junctionless FET is the one of the solution in the future devices. JL-FET is a novel device, which has heavily doping channel with the same type to that of source and drain. Theref

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26

Du, Yan-Ting, and 杜衍廷. "Analysis of Sub-5 nm Transistors Trend by 3D TCAD Simulation." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/2ec8c9.

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27

Chen, Chi-Fu, and 陳淇富. "Optimization of the Gate - Drain Capacitance to Improve the Switching Performance of Trench Power Metal-Oxide-Semiconductor Field-Effect Transistors." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/59181487297802687295.

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碩士<br>國立交通大學<br>工學院半導體材料與製程設備學程<br>100<br>Power MOSFETs are widely used as a switching device for high frequency and low voltage (<200 V) power converter. The switching rate depends on charging and discharging performance of the gate capacitor. Low gate - drain charge and low on-resistance can reduce switching power loss and thus improve the device performance. Many approaches have been developed to increase the unit cell density to reduce the on-resistance in trench type power MOSFETs, but the switching will become slower while the gate parasitic capacitance increases. This thesis presents th

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