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Zeitschriftenartikel zum Thema „Trench transistor“

Autor: Grafiati

Veröffentlicht am 25. Mai 2024

Zuletzt aktualisiert am 31. Juli 2025

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1

Shichijo, H., S. K. Banerjee, S. D. S. Malhi, et al. "Trench transistor DRAM cell." IEEE Electron Device Letters 7, no. 2 (1986): 119–21. http://dx.doi.org/10.1109/edl.1986.26313.

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2

Gupta, Aakashdeep, K. Nidhin, Suresh Balanethiram, et al. "Static Thermal Coupling Factors in Multi-Finger Bipolar Transistors: Part I—Model Development." Electronics 9, no. 9 (2020): 1333. http://dx.doi.org/10.3390/electronics9091333.

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In this part, we propose a step-by-step strategy to model the static thermal coupling factors between the fingers in a silicon based multifinger bipolar transistor structure. First we provide a physics-based formulation to find out the coupling factors in a multifinger structure having no-trench isolation (cij,nt). As a second step, using the value of cij,nt, we propose a formulation to estimate the coupling factor in a multifinger structure having only shallow trench isolations (cij,st). Finally, the coupling factor model for a deep and shallow trench isolated multifinger device (cij,dt) is p

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3

Dai, Tian Xiang, A. B. Renz, Luyang Zhang, et al. "Design and Optimisation of Schottky Contact Integration in a 4H-SiC Trench MOSFET." Materials Science Forum 1004 (July 2020): 808–13. http://dx.doi.org/10.4028/www.scientific.net/msf.1004.808.

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Planar Schottky contact and various trench Schottky contacts have been integrated into the edge termination region of a 4H-SiC trench metal-oxide-semiconductor field-effect-transistor (MOSFET). The forward and reverse characteristics of various design splits have been benchmarked to determine the optimum method of the Schottky contact integration. As a result, the trench Schottky diode with Schottky metal contact in both the planar surface and the trench sidewall surface has been able to offer the best performance.

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4

Mukherjee, Kalparupa, Carlo De Santi, Matteo Borga, et al. "Challenges and Perspectives for Vertical GaN-on-Si Trench MOS Reliability: From Leakage Current Analysis to Gate Stack Optimization." Materials 14, no. 9 (2021): 2316. http://dx.doi.org/10.3390/ma14092316.

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The vertical Gallium Nitride-on-Silicon (GaN-on-Si) trench metal-oxide-semiconductor field effect transistor (MOSFET) is a promising architecture for the development of efficient GaN-based power transistors on foreign substrates for power conversion applications. This work presents an overview of recent case studies, to discuss the most relevant challenges related to the development of reliable vertical GaN-on-Si trench MOSFETs. The focus lies on strategies to identify and tackle the most relevant reliability issues. First, we describe leakage and doping considerations, which must be considere

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5

Banerjee, S., and D. M. Bordelon. "A model for the trench transistor." IEEE Transactions on Electron Devices 34, no. 12 (1987): 2485–92. http://dx.doi.org/10.1109/t-ed.1987.23339.

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6

Wang, Bo. "Analysis of base characteristics of trench gate field termination IGBT." E3S Web of Conferences 237 (2021): 02023. http://dx.doi.org/10.1051/e3sconf/202123702023.

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Trench gate structure represents the latest structure of Insulated Gate Bipolar Transistor(IGBT). Because there are great differences in model analysis coordinate system and carrier transport between trench gate structure and planar gate structure, the modeling method using planar gate structure will inevitably have great deviation. Based on the characteristics of trench gate structure and model analysis coordinate system, the base region is divided into PNP and PIN by considering the two-dimensional effect of carriers. According to whether the trench of PIN part can be covered by depletion la

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7

Manosukritkul, Phasapon, Amonrat Kerdpardist, Montree Saenlamool, Ekalak Chaowicharat, Amporn Poyai, and Wisut Titiroongruang. "An Improvement of the Breakdown Voltage Characteristics of NPT-TIGBT by Using a P-Buried Layer." Advanced Materials Research 717 (July 2013): 158–63. http://dx.doi.org/10.4028/www.scientific.net/amr.717.158.

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In this paper, we introduced a P-buried (Pb) layer under trench gate which relieved the electric field crowding in the Non Punch Through Trench gate Insulated Gate Bipolar Transistor (NPT-TIGBT) structure. The Pblayer, with carrier concentration of 5x1016cm-3, was created underneath the trench gate within the n-drift layer. In this way, the concentration of electric field at the trench bottom corner decreased. As a result, the breakdown voltage characteristics of NPT-TIGBT improved. The structures were proposed and verified by T-CAD Sentuarus simulation. From the simulation results, the breakd

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8

Chen, Q., B. You, A. Q. Huang, and J. K. O. Sin. "A new trench base-shielded bipolar transistor." IEEE Transactions on Electron Devices 47, no. 8 (2000): 1662–66. http://dx.doi.org/10.1109/16.853045.

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9

Yang, Ling Ling. "A Novel Structure Trench IGBT with Full Hole-Barrier Layer." Applied Mechanics and Materials 543-547 (March 2014): 757–61. http://dx.doi.org/10.4028/www.scientific.net/amm.543-547.757.

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A Full Hole-barrier Trench gate Insulated Gate Bipolar Transistor (FH-TIGBT) device structure is proposed for the first time. Compared with Carrier Stored Trench IGBT (CSTBT), which adds a carrier stored n layer between p base and n base in Trench IGBT (TIGBT), the new structure appends an n region located in the bottom of the trench gate. The result of Process and device simulations shows that the proposed device has lowered saturation voltage and larger capability of carrying current compared to either conventional trench IGBT or CSTBT. And the characteristics of turn-off time and breakdown

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10

Shu, Lei, Huai-Lin Liao, Zi-Yuan Wu, et al. "Effects of Gamma Irradiation on Switching Characteristics of SiC MOSFET Power Devices of Different Structures." Electronics 12, no. 10 (2023): 2194. http://dx.doi.org/10.3390/electronics12102194.

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The switching characteristics of silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) power devices of different structures were experimented after exposure to a gamma irradiation environment. The experimental results for on-state were studied. The comparisons are shown for SiC MOSFET power devices with planar, trench and double trench structures tested for total ionizing dose (TID). A higher degradation of the switching characteristics was observed for the double trench structure. The physical mechanisms for these switching characteristics variations were analyzed.

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11

Hung, Chia Lung, Yi Kai Hsiao, Chang Ching Tu, and Hao Chung Kuo. "Investigation of 4H-SiC UMOSFET Architectures for High Voltage and High Speed Power Switching Applications." Materials Science Forum 1088 (May 18, 2023): 41–49. http://dx.doi.org/10.4028/p-56sbi2.

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A comparative TCAD (Technology Computer Aided Design) simulation study of various 4H-SiC trench gate MOSFET (Metal Oxide Semiconductor Field Effect Transistor) (or U-shaped trench gate MOSFET abbreviated for UMOSFET) architectures for high voltage and high-speed switching applications is reported. The DC (Direct Current) and AC (Alternating Current) characteristics of the different trench gate structures are investigated. Particularly, compared to conventional 4H-SiC UMOSFETs, the breakdown voltage of the UMOSFET having a p-type implanted bottom shield is increased by 44%. However, due to the

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12

Wang, Bo. "Analysis of junction capacitance characteristics of trench gate IGBT." E3S Web of Conferences 237 (2021): 02024. http://dx.doi.org/10.1051/e3sconf/202123702024.

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Trench gate field termination IGBT represents the latest structure of insulated gate bipolar transistor (IGBT). Because the internal current of IGBT includes the charging and discharging current of gate capacitance and internal junction capacitance during switching transient, the influence of junction capacitance should be considered. The conductive channel of trench gate structure is different from that of planar gate structure, and the analysis method of junction capacitance using planar gate structure will inevitably bring some deviation. Based on the characteristics of trench gate structur

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13

Banzhaf, Christian T., Michael Grieb, Achim Trautmann, Anton J. Bauer, and Lothar Frey. "Investigation of Trenched and High Temperature Annealed 4H-SiC." Materials Science Forum 778-780 (February 2014): 742–45. http://dx.doi.org/10.4028/www.scientific.net/msf.778-780.742.

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This study focuses on the effects of a high temperature anneal after dry etching of trenches (post-trench anneal, PTA) on 4Hsilicon carbide (4H-SiC). We aim at the optimum 4H-SiC post-trench treatment with respect to the fabrication and the operation of a trenched gate metal oxide semiconductor field effect transistor (Trench-MOSFET). PTA significantly reduces micro-trenches, also called sub-trenches [, in the corners of the bottom of the trench. This is highly beneficial in case the etched trench sidewall is used as the channel of a Trench-MOSFET. However, PTA is also shown to cause a slight

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14

Kakarla, Bhagyalakshmi, Thomas Ziemann, Selamnesh Nida, Elias Doenni, and Ulrike Grossner. "Planar to Trench: Short Circuit Capability Analysis of 1.2 kV SiC MOSFETs." Materials Science Forum 924 (June 2018): 782–85. http://dx.doi.org/10.4028/www.scientific.net/msf.924.782.

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This paper presents an insight into the short circuit (SC) capability of Rohm’s discrete 1.2 kV, 80 mΩ state-of-the-art silicon carbide (SiC) double trench metal-oxide-semiconductor field effect transistor (MOSFET). SC measurements are performed to compare the behavior of Wolfspeed’s similarly rated 1.2 kV, 80 mΩ planar MOSFET with the Rohm trench devices. Short circuit withstand time (SCWT) of both designs under nominal operating conditions at room temperature is measured by performing destructive SC tests.

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15

Shah, A. H., C. Wang, R. H. Womack, et al. "A 4-Mbit DRAM with trench-transistor cell." IEEE Journal of Solid-State Circuits 21, no. 5 (1986): 618–26. http://dx.doi.org/10.1109/jssc.1986.1052586.

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16

Huang, Q., and G. A. J. Amaratunga. "Analysis of double trench insulated gate bipolar transistor." Solid-State Electronics 38, no. 4 (1995): 829–38. http://dx.doi.org/10.1016/0038-1101(94)00110-2.

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17

Aur, S., and Ping Yang. "IVB-6 hot-carrier reliability of trench transistor." IEEE Transactions on Electron Devices 34, no. 11 (1987): 2374. http://dx.doi.org/10.1109/t-ed.1987.23289.

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18

Banerjee, S., D. Coleman, W. Richardson, and A. Shah. "Leakage mechanisms in the trench transistor DRAM cell." IEEE Transactions on Electron Devices 35, no. 1 (1988): 108–16. http://dx.doi.org/10.1109/16.2425.

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19

Hueting, R. J. E., J. W. Slotboom, J. Melai, P. Agarwal, and P. H. C. Magnee. "A New Trench Bipolar Transistor for RF Applications." IEEE Transactions on Electron Devices 51, no. 7 (2004): 1108–13. http://dx.doi.org/10.1109/ted.2004.829867.

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20

Sugiyama, Naohiro, Yuuichi Takeuchi, Mitsuhiro Kataoka, Adolf Schöner, and Rajesh Kumar Malhan. "Growth Mechanism and 2D Aluminum Dopant Distribution of Embedded Trench 4H-SiC Region." Materials Science Forum 600-603 (September 2008): 171–74. http://dx.doi.org/10.4028/www.scientific.net/msf.600-603.171.

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The migration enhanced embedded epitaxy (ME3) mechanism and 2D dopant distribution of the embedded trench region is investigated with the aim to realize the all-epitaxial, normally-off junction field effect transistor (JFET). We found that the embedded growth consists of two main components. First one is the direct supply without gas scattering and the other one is the surface migration supply via the trench opening edge, which dominate the ME3 process. An inhomogeneous 2D distribution of Aluminum (Al) concentration was revealed for the first time in the 4H-SiC embedded trench regions by the c

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21

Jiang, Dandan, Lei Jin, and Zongliang Huo. "A Quantitative Approach to Characterize Total Ionizing Dose Effect of Periphery Device for 65 nm Flash Memory." Nanoscience and Nanotechnology Letters 10, no. 3 (2018): 378–82. http://dx.doi.org/10.1166/nnl.2018.2604.

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To evaluate the total ionizing dose (TID) response of periphery devices with 65 nm flash memory, the TID effects of the main and parasitic transistor have been investigated based on the proposed novel parameter extraction approach. By analyzing post-radiation behavior of the device's drain current and interface trap density, it has been proven that the parasitic transistor demonstrates stronger radiation dependence than the main transistor. With the proposed approach, the roles of the parasitic transistor and main transistor in the TID effect are quantitatively characterized. For a W =10 μm HV

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22

Zhang, Meng, Baikui Li, Zheyang Zheng, Xi Tang, and Jin Wei. "A New SiC Planar-Gate IGBT for Injection Enhancement Effect and Low Oxide Field." Energies 14, no. 1 (2020): 82. http://dx.doi.org/10.3390/en14010082.

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A new silicon carbide (SiC) planar-gate insulated-gate bipolar transistor (IGBT) is proposed and comprehensively investigated in this paper. Compared to the traditional SiC planar-gate IGBT, the new IGBT boasts a much stronger injection enhancement effect, which leads to a low on-state voltage (VON) approaching the SiC trench-gate IGBT. The strong injection enhancement effect is obtained by a heavily doped carrier storage layer (CSL), which creates a hole barrier under the p-body to hinder minority carriers from being extracted away through the p-body. A p-shield is located at the bottom of th

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23

Na, Jaeyeop, Jinhee Cheon, and Kwangsoo Kim. "4H-SiC Double Trench MOSFET with Split Heterojunction Gate for Improving Switching Characteristics." Materials 14, no. 13 (2021): 3554. http://dx.doi.org/10.3390/ma14133554.

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In this paper, a novel 4H-SiC split heterojunction gate double trench metal-oxide-semiconductor field-effect transistor (SHG-DTMOS) is proposed to improve switching speed and loss. The device modifies the split gate double trench MOSFET (SG-DTMOS) by changing the N+ polysilicon split gate to the P+ polysilicon split gate. It has two separate P+ shielding regions under the gate to use the P+ split polysilicon gate as a heterojunction body diode and prevent reverse leakage `current. The static and most dynamic characteristics of the SHG-DTMOS are almost like those of the SG-DTMOS. However, the r

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Li, Xuan, Xing Tong, Alex Q. Huang, et al. "Shielded Gate SiC Trench Power MOSFET with Ultra-Low Switching Loss." Materials Science Forum 924 (June 2018): 765–69. http://dx.doi.org/10.4028/www.scientific.net/msf.924.765.

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A shielded gate trench silicon carbide (SiC) metal oxide semiconductor field effect transistor (SG-TMOS) is proposed and investigated by simulation in this paper. The impact of shielded gate design in SG-TMOS on Miller charge (Qgd) as well as conduction resistance (Ron) are comprehensively discussed, showing a tradeoff between Qgdand Ron. Furthermore, the Huang’s Figure of Merit (HFOM) of the SG-TMOS with reasonable design of SG is reduced more than 20%, compared with the conventional trench MOSFET (C-TMOS). Therefore, the proposed SG-TMOS is a competitive next generation device structure for

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Shu, Lei, Huai-Lin Liao, Zi-Yuan Wu, et al. "Comparison of Gamma Irradiation Effects on Short Circuit Characteristics of SiC MOSFET Power Devices between Planar and Trench Structures." Electronics 12, no. 13 (2023): 2891. http://dx.doi.org/10.3390/electronics12132891.

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The short circuit withstand energy (SCWE) variations, and short circuit withstand time (SCWT) variations, of planar and trench silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) power devices are studied after exposure to a total ionizing dose (TID). The results for ON bias are explored. The SCWE and SCWT are studied for planar and trench SiC MOSFET power devices tested for TID with gamma irradiation. A higher degradation phenomenon for the SCWE and SCWT are observed for the planar SiC MOSFET. The physical mechanisms for these variations are analyzed and confirmed

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Son, Won-So, Young-Ho Sohn, and Sie-young Choi. "SOI RESURF LDMOS transistor using trench filled with oxide." Electronics Letters 39, no. 24 (2003): 1760. http://dx.doi.org/10.1049/el:20031115.

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27

Cai, J., J. K. O. Sin, P. K. T. Mok, Wai-Tung Ng, and P. P. T. Lai. "A new lateral trench-gate conductivity modulated power transistor." IEEE Transactions on Electron Devices 46, no. 8 (1999): 1788–93. http://dx.doi.org/10.1109/16.777171.

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28

Spulber, O., M. Sweet, K. Vershinin, et al. "A novel trench clustered insulated gate bipolar transistor (TCIGBT)." IEEE Electron Device Letters 21, no. 12 (2000): 613–15. http://dx.doi.org/10.1109/55.887483.

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29

Takeuchi, Wakana, Eiji Kagoshima, Kazushi Sumitani, et al. "Visualization of local strain in 4H-SiC trench metal-oxide-semiconductor field-effect transistor using synchrotron nanobeam X-ray diffraction." Japanese Journal of Applied Physics 61, SC (2022): SC1072. http://dx.doi.org/10.35848/1347-4065/ac4c6d.

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Abstract We investigated the local strain in a silicon carbide (4H-SiC) (0001) trench metal-oxide semiconductor field-effect transistor (MOSFET) using synchrotron nanobeam X-ray diffraction (nano-XRD) at the SPring-8 BL13XU beamline. Using X-rays incident on the 4H-SiC trench cross section, diffraction measurements were performed on the ( 11 2 ¯ 0 ) and ( 11 2 ¯ 4 ) planes. Intensity maps of the 11 2 ¯ 0 and 11 2 ¯ 4 diffractions yielded images reflecting the trench structure. The spatial resolution of the 4H-SiC 11 2 ¯ 4 intensity map in the [0001] direction was higher than that for the 11 2

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Na, Jaeyeop, Jinhee Cheon, and Kwangsoo Kim. "High performance 4H-SiC MOSFET with deep source trench." Semiconductor Science and Technology 37, no. 4 (2022): 045004. http://dx.doi.org/10.1088/1361-6641/ac5103.

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Abstract In this study, we investigated a 4H-SiC deep source trench metal-oxide semiconductor field-effect transistor (DST-MOSFET) using technology computer-aided design numerical simulations. The proposed DST-MOSFET comprises a P-pillar formed along with the DST and a side P+ shielding region (SPR), which replaces the gate trench bottom SPR. Owing to the superjunction generated by the P-pillar and N-drift region, the static characteristics of the DST-MOSFET were superior to those of the trench gate MOSFET (UMOSFET) and double-trench MOSFET (DT-MOSFET). The specific on-resistance and Baliga’s

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31

Jeong, Jee-Hun, Ju-Hong Cha, Goon-Ho Kim, Sung-Hwan Cho, and Ho-Jun Lee. "Study of a SiC Trench MOSFET Edge-Termination Structure with a Bottom Protection Well for a High Breakdown Voltage." Applied Sciences 10, no. 3 (2020): 753. http://dx.doi.org/10.3390/app10030753.

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A novel edge-termination structure for a SiC trench metal–oxide semiconductor field-effect transistor (MOSFET) power device is proposed. The key feature of the proposed structure is a periodically formed SiC trench with a bottom protection well (BPW) implantation region. The trench can be filled with oxide or gate materials. Indeed, it has almost the same cross-sectional structure as the active region of a SiC trench MOSFET. Therefore, there is little or no additional process loads. A conventional floating field ring (FFR) structure utilizes the spreading of the electric field in the periodica

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Zhang, Meng, Baikui Li, and Jin Wei. "Exploring SiC Planar IGBTs towards Enhanced Conductivity Modulation Comparable to SiC Trench IGBTs." Crystals 10, no. 5 (2020): 417. http://dx.doi.org/10.3390/cryst10050417.

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The state-of-the-art silicon insulated-gate bipolar transistor (IGBT) features a trench gate, since it enhances the conductivity modulation. The SiC trench IGBT, however, faces the critical challenge of a high electric field in the gate oxide, which is a crucial threat to the device’s reliability. In this work, we explore the possibility of using a SiC planar IGBT structure to approach high performance to the level of a SiC trench IGBT, without suffering the high gate oxide field. The proposed SiC planar IGBT features buried p-layers directly under the p-bodies, and thus can be formed using th

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Zhou, Xuanze, Yongjian Ma, Guangwei Xu та ін. "Enhancement-mode β-Ga₂O₃ U-shaped gate trench vertical MOSFET realized by oxygen annealing". Applied Physics Letters 121, № 22 (2022): 223501. http://dx.doi.org/10.1063/5.0130292.

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Vertical metal–oxide–semiconductor field effect transistor (MOSFET) is essential to the future application of ultrawide bandgap β-Ga2O3. In this work, we demonstrated an enhancement-mode β-Ga2O3 U-shaped gate trench vertical metal–oxide–semiconductor field effect transistor (UMOSFET) featuring a current blocking layer (CBL). The CBL was realized by high-temperature annealing under oxygen ambient, which provided electrical isolation between the source and drain electrodes. The CBL thicknesses of different annealing temperatures were derived from C–V measurements and the Fermi level position of

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Yang, Jianan, John P. Denton, and Gerold W. Neudeck. "Edge transistor elimination in oxide trench isolated N-channel metal–oxide–semiconductor field effect transistors." Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures 19, no. 2 (2001): 327. http://dx.doi.org/10.1116/1.1358854.

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Qian, Zhehong, Wenrong Cui, Tianyang Feng, et al. "A Novel High-Speed Split-Gate Trench Carrier-Stored Trench-Gate Bipolar Transistor with Enhanced Short-Circuit Roughness." Micromachines 15, no. 6 (2024): 680. http://dx.doi.org/10.3390/mi15060680.

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A novel high-speed and process-compatible carrier-stored trench-gate bipolar transistor (CSTBT) combined with split-gate technology is proposed in this paper. The device features a split polysilicon electrode in the trench, where the left portion is equipotential with the cathode. This design mitigates the impact of the anode on the trench gate, resulting in a reduction in the gate-collector capacitance (CGC) to improve the dynamic characteristics. On the left side of the device cell, the P-layer, the carrier-stored (CS) layer and the P-body are formed from the bottom up by ion implantation an

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Ma, Rongyao, Ruoyu Wang, Hao Fang, et al. "A Novel Deep-Trench Super-Junction SiC MOSFET with Improved Specific On-Resistance." Micromachines 15, no. 6 (2024): 684. http://dx.doi.org/10.3390/mi15060684.

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In this paper, a novel 4H-SiC deep-trench super-junction MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) with a split-gate is proposed and theoretically verified by Sentaurus TCAD simulations. A deep trench filled with P-poly-Si combined with the P-SiC region leads to a charge balance effect. Instead of a full-SiC P region in conventional super-junction MOSFET, this new structure reduces the P region in a super-junction MOSFET, thus helping to lower the specific on-resistance. As a result, the figure of merit (FoM, BV2/Ron,sp) of the proposed new structure is 642% and 39.65% higher

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Akiyama, Satoru, Haruka Shimizu, Natsuki Yokoyama та ін. "A 69-mΩ 600-V-Class Hybrid JFET". Materials Science Forum 740-742 (січень 2013): 925–28. http://dx.doi.org/10.4028/www.scientific.net/msf.740-742.925.

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A hybrid silicon-carbide junction-gate field-effect transistor (HJT: hybrid JFET) is proposed. The HJT consists of a silicon-carbide (SiC) normally-on vertical JFET and a low-voltage normally-off silicon metal-oxide-semiconductor field-effect transistor (Si-MOS: silicon MOSFET). These two devices are connected by bonding wire as a cascode circuit [1] and packaged in a TO-3P split-lead-frame package with the same pin arrangement as conventional silicon power devices, which can thus be easily replaced by the proposed HJT. The vertical JFET has a steep-junction deep-trench structure in its channe

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Wu, Jiale, Houyong Zhou, and Yi Chen. "A Novel Super-junction MOSFET with Enhanced Switching Performance and Ruggedness." Journal of Physics: Conference Series 2524, no. 1 (2023): 012028. http://dx.doi.org/10.1088/1742-6596/2524/1/012028.

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Abstract In this paper, a novel super-junction (SJ) MOSFET with enhanced switching performance and ruggedness is proposed and investigated by the method of TCAD simulations. An N+/P- polysilicon junction gate electrode and separation layer between P-base and P-pillar are introduced to the trench SJ-MOSFET. For the N+/P- junction trench gate, the P- polysilicon located in the bottom of the trench plays the role of insulating layer, which efficiently reduces the gate charge (QG), thus increasing the switching speed and reducing the switching loss. The P-pillar does not contact with P-base so a d

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Zeng, J., P. A. Mawby, M. S. Towers, and K. Board. "THERMO‐ELECTRIC STUDY OF THE TRENCH‐GATE POWER VDMOS TRANSISTOR." COMPEL - The international journal for computation and mathematics in electrical and electronic engineering 13, no. 4 (1994): 735–42. http://dx.doi.org/10.1108/eb051891.

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40

Rongyao, Ma, Li Zehong, Hong Xin, and Zhang Bo. "Carrier stored trench-gate bipolar transistor with p-floating layer." Journal of Semiconductors 31, no. 2 (2010): 024004. http://dx.doi.org/10.1088/1674-4926/31/2/024004.

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41

Hieda, K., F. Horiguchi, H. Watanabe, K. Sunouchi, I. Inoue, and T. Hamamoto. "Effects of a new trench-isolated transistor using sidewall gates." IEEE Transactions on Electron Devices 36, no. 9 (1989): 1615–19. http://dx.doi.org/10.1109/16.34221.

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42

Maralani, A., Michael S. Mazzola, David C. Sheridan, Igor Sankin, and Volodymyr Bondarenko. "Characterization and Modeling of SiC LTJFET for Analog Integrated Circuit Simulation and Design." Materials Science Forum 615-617 (March 2009): 915–18. http://dx.doi.org/10.4028/www.scientific.net/msf.615-617.915.

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The design of analog integrated circuits, for instance, the operational amplifiers, have been widely perfected with devices and processes available in silicon. However, analogous circuits have been the subject of research in Silicon Carbide (SiC). Among SiC devices, 4H-SiC Lateral-Trench JFET (LTJFET) transistor offers advantages and new opportunities to make affordable and reliable analog integrated circuits for harsh environment. In this paper: (1) SiC LTJFET is characterized for modeling and simulation, (2) effect of temperature variation on SiC LTJFET threshold voltage and small signal par

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Ni, Wei, Kenta Emori, Toshiharu Marui, et al. "SiC Trench MOSFET with an Integrated Low Von Unipolar Heterojunction Diode." Materials Science Forum 778-780 (February 2014): 923–26. http://dx.doi.org/10.4028/www.scientific.net/msf.778-780.923.

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We demonstrate a SiC trench MOSFET with an integrated low Von unipolar heterojunction diode (MOSHJD). A region of the heterojunction diode (HJD) was fabricated in a trench with p+-type poly-crystalline silicon on an n--type epitaxial layer of 4H-SiC. The measured on-resistance (Ron) of the transistor action was 15 mΩcm2. The measured Von of the diode action was 2.2 V at a forward current density of 100 A/cm2. The fabrication process of the MOSHJD is simple. First, the trenches of the MOSFET region and the HJD region are formed simultaneously; then poly-crystalline silicon is deposited to form

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Chong, Chen, Hongxia Liu, Shougang Du, Shulong Wang, and Hao Zhang. "Study on the Simulation of Biosensors Based on Stacked Source Trench Gate TFET." Nanomaterials 13, no. 3 (2023): 531. http://dx.doi.org/10.3390/nano13030531.

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In order to detect biomolecules, a biosensor based on a dielectric-modulated stacked source trench gate tunnel field effect transistor (DM-SSTGTFET) is proposed. The stacked source structure can simultaneously make the on-state current higher and the off-state current lower. The trench gate structure will increase the tunneling area and tunneling probability. Technology computer-aided design (TCAD) is used for the sensitivity study of the proposed structured biosensor. The results show that the current sensitivity of the DM-SSTGTFET biosensor can be as high as 108, the threshold voltage sensit

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Lee, Hoontaek, Junsoo Kim, Kumjae Shin, and Wonkyu Moon. "Improving the Performance of the ToGoFET Probe: Advances in Design, Fabrication, and Signal Processing." Micromachines 12, no. 11 (2021): 1303. http://dx.doi.org/10.3390/mi12111303.

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We report recent improvements of the tip-on-gate of field-effect-transistor (ToGoFET) probe used for capacitive measurement. Probe structure, fabrication, and signal processing were modified. The inbuilt metal-oxide-semiconductor field-effect-transistor (MOSFET) was redesigned to ensure reliable probe operation. Fabrication was based on the standard complementary metal-oxide-semiconductor (CMOS) process, and trench formation and the channel definition were modified. Demodulation of the amplitude-modulated drain current was varied, enhancing the signal-to-noise ratio. The I-V characteristics of

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46

Yahata, Akihiro, Satoshi Urano, Tomoki Inoue, and Takashi Shinohe. "Improvement of Channel Mobility for Trench Metal-Oxide-Semiconductor Field Effect Transistor by Smoothing Trench Sidewall Surface." Japanese Journal of Applied Physics 40, Part 1, No. 1 (2001): 116–17. http://dx.doi.org/10.1143/jjap.40.116.

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47

Volcheck, V. S., and V. R. Stempitsky. "Gallium nitride heterostructure field-effect transistor with a heat-removal system based on a trench in the passivation layer filled by a high thermal conductivity material." Doklady BGUIR 19, no. 6 (2021): 74–82. http://dx.doi.org/10.35596/1729-7648-2021-19-6-74-82.

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The self-heating effect poses a main problem for high-power electronic and optoelectronic devices based on gallium nitride. A non-uniform distribution of the dissipated power and a rise of the average temperature inside the gallium nitride heterostructure field-effect transistor lead to the formation of a hot spot near the conducting channel and result in the degradation of the drain current, output power and device reliability. The purpose of this work is to develop the design of a gallium nitride heterostructure field-effect transistor with an effective heat-removal system and to study using

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Volcheck, V. S., and V. R. Stempitsky. "Large Signal Performance of the Gallium Nitride Heterostructure Field-Effect Transistor With a Graphene Heat-Removal System." Doklady BGUIR 20, no. 1 (2022): 40–47. http://dx.doi.org/10.35596/1729-7648-2022-20-1-40-47.

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The self-heating effect exerts a considerable influence on the characteristics of high-power electronic and optoelectronic devices based on gallium nitride. An extremely non-uniform distribution of the dissipated power and a rise in the average temperature in the gallium nitride heterostructure field-effect transistor lead to the formation of a hot spot near the conductive channel and result in the degradation of the drain current, power gain and device reliability. The purpose of this work is to design a gallium nitride heterostructure field-effect transistor with an effective graphene heat-r

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Deng, Xiao Chuan, Hao Zhu, Xuan Li та ін. "Avalanche Ruggedness Assessment of 1.2kV 45mΩ Asymmetric Trench SiC MOSFETs". Materials Science Forum 1004 (липень 2020): 837–42. http://dx.doi.org/10.4028/www.scientific.net/msf.1004.837.

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In this paper, avalanche ruggedness of the commercial 1.2kV 45mΩ asymmetric silicon carbide (SiC) metal oxide semiconductor field effect transistor (MOSFET) is investigated by single-pulse unclamped inductive switching (UIS) test. The avalanche safe operation area (SOA) of the MOSFET is established. The impact of inductance and temperature on avalanche capability is exhibited, which is valuable for many application circuits. The variation in critical avalanche energy with peak avalanche current, peak avalanche current with avalanche time, and temperatures dependence of critical avalanche energ

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Bellini, Marco, and Lars Knoll. "Advanced TCAD Design Techniques for the Performance Improvement of SiC MOSFETs." Materials Science Forum 1004 (July 2020): 865–71. http://dx.doi.org/10.4028/www.scientific.net/msf.1004.865.

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This paper introduces novel TCAD post-processing techniques for SiC MOSFETs with the aim of understanding which parts of the device limit the on-state performance. Typically, analytical models of MOSFETs are used as a starting point for the TCAD design process or as a simple way to understand the influence of complex design choices, as discussed in the works of [1-3]. These lumped element models result in a relatively straightforward approach because they explicitly identify the contributions of the regions of the transistor, facilitating the understanding of basic design choices and performan

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