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Thematische Bibliographien / Triple gate transistor / Zeitschriftenartikel

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Zeitschriftenartikel zum Thema „Triple gate transistor“

Autor: Grafiati

Veröffentlicht am 25. Mai 2024

Zuletzt aktualisiert am 19. Juli 2025

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1

Grossl Bade, Tamiris, Hassan Hamad, Adrien Lambert, Hervé Morel, and Dominique Planson. "Threshold Voltage Measurement Protocol “Triple Sense” Applied to GaN HEMTs." Electronics 12, no. 11 (2023): 2529. http://dx.doi.org/10.3390/electronics12112529.

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The threshold voltage instability in p-GaN gate high electron mobility transistors (HEMTs) has been brought into evidence in recent years. It can lead to reliability issues in switching applications, and it can be followed by other degradation mechanisms. In this paper, a Vth measurement protocol established for SiC MOSFETs is applied to GaN HEMTs: the triple sense protocol, which uses voltage bias to precondition the transistor gate. It has been experimentally verified that the proposed protocol increased the stability of the Vth measurement, even for measurements following degrading voltage

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Cho, Seong-Kun, and Won-Ju Cho. "Highly Sensitive and Transparent Urea-EnFET Based Point-of-Care Diagnostic Test Sensor with a Triple-Gate a-IGZO TFT." Sensors 21, no. 14 (2021): 4748. http://dx.doi.org/10.3390/s21144748.

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In this study, we propose a highly sensitive transparent urea enzymatic field-effect transistor (EnFET) point-of-care (POC) diagnostic test sensor using a triple-gate amorphous indium gallium zinc oxide (a-IGZO) thin-film pH ion-sensitive field-effect transistor (ISFET). The EnFET sensor consists of a urease-immobilized tin-dioxide (SnO2) sensing membrane extended gate (EG) and an a-IGZO thin film transistor (TFT), which acts as the detector and transducer, respectively. To enhance the urea sensitivity, we designed a triple-gate a-IGZO TFT transducer with a top gate (TG) at the top of the chan

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Conde, Jorge E., Antonio Cereira, and M. Estrada. "Distortion Analysis of Triple-Gate Transistor in Saturation." ECS Transactions 9, no. 1 (2019): 67–73. http://dx.doi.org/10.1149/1.2766875.

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4

Gay, R., V. Della Marca, H. Aziza, et al. "Gate stress reliability of a novel trench-based Triple Gate Transistor." Microelectronics Reliability 126 (November 2021): 114233. http://dx.doi.org/10.1016/j.microrel.2021.114233.

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5

P., Kiran Kumar, Sunil Kumar G., and Karthik A. "Triple Gate Spin Field-Effect Transistor Modeling and Applications." Journal of VLSI Design and its Advancement 6, no. 1 (2023): 7–13. https://doi.org/10.5281/zenodo.7751334.

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<em>In this research, a mathematical model is used to simulate a Triple Gate Spin-FET with Indium Arsenide in the channel. DC simulations verify the simulation results. Later, different logic functions are achieved by specifying the appropriate channels and several other parameters like spin injection, spin detection, etc. Each gate terminal receives a unique set of inputs. One multi gate spin-FET is used to attain the desired functionality. Using conventional CMOS to achieve the same goals would require a far greater number of chips. The attained capabilities are competitive with designs usin

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6

SHAHHOSEINI, ALI, KAMYAR SAGHAFI, MOHAMMAD KAZEM MORAVVEJ-FARSHI, and RAHIM FAEZ. "TRIPLE-TUNNEL JUNCTION SINGLE ELECTRON TRANSISTOR (TTJ-SET)." Modern Physics Letters B 25, no. 17 (2011): 1487–501. http://dx.doi.org/10.1142/s0217984911026346.

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We propose a triple-tunnel junction single electron transistor (TTJ-SET). The proposed structure consists of a metallic quantum-dot island that is capacitive coupled to a gate contact and surrounded by three tunnel junctions. To the best of our knowledge, this is the first instance of introducing this new structure that is suitable for both digital and analog applications. I–V D characteristics of the proposed TTJ-SET, simulated by a HSPICE macro model for various gate voltages, are in excellent agreement with those obtained by SIMON, which is a Monte-Carlo based simulator. We show how one can

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Pandey, Neeta, Kirti Gupta, and Bharat Choudhary. "New Proposal for MCML Based Three-Input Logic Implementation." VLSI Design 2016 (September 19, 2016): 1–10. http://dx.doi.org/10.1155/2016/8712768.

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This paper presents a new proposal for three-input logic function implementation in MOS current mode logic (MCML) style. The conventional realization of such logic employs three levels of stacked source-coupled transistor pairs. It puts restriction on minimum power supply requirement and results in increased static power. The new proposal presents a circuit element named as quad-tail cell which reduces number of stacked source-coupled transistor levels by two. A three-input exclusive-OR (XOR) gate, a vital element in digital system design, is chosen to elaborate the approach. Its behavior is a

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Manikandan, S., P. Suveetha Dhanaselvam, and M. Karthigai Pandian. "A Quasi 2-D Electrostatic Potential and Threshold Voltage Model for Junctionless Triple Material Cylindrical Surrounding Gate Si Nanowire Transistor." Journal of Nanoelectronics and Optoelectronics 16, no. 2 (2021): 318–23. http://dx.doi.org/10.1166/jno.2021.2951.

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A mathematical model used for determining the threshold voltage characteristics and electrostatic potential of a Junctionless Triple Material Cylindrical Surrounding Gate Silicon Nanowire Transistor (JLTMCSGSiNWT) is proposed in this research work and is obtained by resolving the poison equation. Three materials with dissimilar metal functions are used in the construction of the device gate structure. Device parameters used to determine the electrical characteristics are also included in the model. Behavior of the device is investigated through its vertical electrical field distribution along

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de Araujo, Gustavo Vinicius, Joao Martino, and Paula Agopian. "Operational Transconductance Amplifier Designed with Experimental Omega-Gate Nanowire SOI MOSFETs." ECS Meeting Abstracts MA2023-01, no. 33 (2023): 1861. http://dx.doi.org/10.1149/ma2023-01331861mtgabs.

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The nanowire omega-gate technology is one of the possible technologies to replace the FinFET one in the semiconductor chip market. The omega-gate nanowire SOI MOSFET is considered a triple plus gate device, near the gate-all-around performance (figure 1) [1]. Due to the omega gate structure this device presents a better gate to channel electrostatic coupling than the FinFET devices, resulting in a greater immunity to short channel effects [1,2]. The Operational Transconductance Amplifier (OTA) is a frequently used analog block in the integrated circuits. The studied OTA consists in a two-stage

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Fui, Tan Chun, Ajay Kumar Singh, and Lim Way Soong. "Performance Characterization of Dual-Metal Triple- Gate-Dielectric (DM_TGD) Tunnel Field Effect Transistor (TFET)." International Journal of Robotics and Automation Technology 8 (December 31, 2021): 83–89. http://dx.doi.org/10.31875/2409-9694.2021.08.8.

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Abstract: Since, Dual Metal Gate (DMG) technology alone is not enough to rectify the problem of low ON current and large ambipolar current in the TFET, therefore, a novel TFET structure, known as dual metal triple-gate-dielectric (DM_TGD) TFET, has been proposed. We have combined the dielectric and gate material work function engineering to enhance the performance of the conventional FET. In the proposed structure, the gate region is divided into three dielectric materials: TiO2/Al2O3/SiO2. This approach is chosen because high dielectric material alone near the source cannot improve the perfor

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Yadala, Gowthami, Balaji Bukya, and Srinivasa Rao Karumuri. "Design and performance analysis of front and back Pi 6 nm gate with high K dielectric passivated high electron mobility transistor." International Journal of Electrical and Computer Engineering (IJECE) 13, no. 4 (2023): 3788–95. https://doi.org/10.11591/ijece.v13i4.pp3788-3795.

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Advanced high electron mobility transistor (HEMT) with dual front gate, back gate with silicon nitride/aluminum oxide (Si3N4/Al2O3) as passivation layer, has been designed. The dependency on DC characteristics and radio frequency characteristics due to GaN cap layers, multi gate (FG and BG), and high K dielectric material is established. Further compared single gate (SG) passivated HEMT, double gate (DG) passivated HEMT, double gate triple (DGT) tooth passivated HEMT, high K dielectric front Pi gate (FG) and back Pi gate (BG) HEMT. It is observed that there is an increased drain current (Ion)

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Darwin, S., and T. S. Arun Samuel. "Mathematical Modeling of Junctionless Triple Material Double Gate MOSFET for Low Power Applications." Journal of Nano Research 56 (February 2019): 71–79. http://dx.doi.org/10.4028/www.scientific.net/jnanor.56.71.

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This paper describes the analytical modeling and simulation of Triple Material Double Gate Metal Oxide Semiconductor Field Effect Transistor (TMDG MOSFET) with no junctions. Three kind of gate materials with different work function values over the channel helps to improve the ON current and to form a barrier in the channel helps to reduce OFF current. It has been found from the obtained results that the OFF current or leakage current of the device is exactly low (IOFF =10-11 A) which is fit for low power applications. Also, the extracted value of ION current (10-3 A) has proved that there is a

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Müller, M. R., A. Gumprich, F. Schütte, et al. "Buried triple-gate structures for advanced field-effect transistor devices." Microelectronic Engineering 119 (May 2014): 95–99. http://dx.doi.org/10.1016/j.mee.2014.02.001.

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14

Gowthami, Yadala, Bukya Balaji, and Karumuri Srinivasa Rao. "Design and performance analysis of front and back Pi 6 nm gate with high K dielectric passivated high electron mobility transistor." International Journal of Electrical and Computer Engineering (IJECE) 13, no. 4 (2023): 3788. http://dx.doi.org/10.11591/ijece.v13i4.pp3788-3795.

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Advanced high electron mobility transistor (HEMT) with dual front gate, back gate with silicon nitride/aluminum oxide (Si3N4/Al2O3) as passivation layer, has been designed. The dependency on DC characteristics and radio frequency characteristics due to GaN cap layers, multi gate (FG and BG), and high K dielectric material is established. Further compared single gate (SG) passivated HEMT, double gate (DG) passivated HEMT, double gate triple (DGT) tooth passivated HEMT, high K dielectric front Pi gate (FG) and back Pi gate (BG) HEMT. It is observed that there is an increased drain current (Ion)

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15

Molaei Imen Abadi, Rouzbeh, and Seyed Ali Sedigh Ziabari. "A Comparative Numerical Study of Junctionless and p-i-n Tunneling Carbon Nanotube Field Effect Transistor." Journal of Nano Research 45 (January 2017): 55–75. http://dx.doi.org/10.4028/www.scientific.net/jnanor.45.55.

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In this paper, a gate-all-around junctionless tunnel field effect transistor (JL-TFET) based on carbon nanotube (CNT) material is introduced and simulated. The JL-TFET is a CNT-channel heavily n-type-doped junctionless field effect transistor (JLFET) which utilizes two insulated gates (Control-Gate, P-Gate) with two different metal workfunctions in order to treat like tunnel field effect transistor (TFET). In this design, the privileges of JLTFET and TFET are mixed together. The numerical comparative study on the performance characteristics of JL-TFET and conventional p-i-n TFET demonstrated t

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Gay, R., V. Della Marca, H. Aziza, et al. "A Novel Trench-Based Triple Gate Transistor With Enhanced Driving Capability." IEEE Electron Device Letters 42, no. 6 (2021): 832–34. http://dx.doi.org/10.1109/led.2021.3076609.

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17

Lim, Sang Woo, and Brian Winstead. "Surface Preparation for Transistor Performance Improvement in Triple Gate Oxide Integration." Journal of The Electrochemical Society 152, no. 9 (2005): G714. http://dx.doi.org/10.1149/1.1973245.

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18

Zakarya, Kourdi, and Abdelkhader Hamdoun. "A modeling and performance of the triple field plate HEMT." International Journal of Power Electronics and Drive Systems (IJPEDS) 10, no. 1 (2019): 398. http://dx.doi.org/10.11591/ijpeds.v10.i1.pp398-405.

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We present this work by two steps. In the first one, the new structure proposed of the FP-HEMTs device (Field plate High Electron Mobility Transistor) with a T-gate on an 4H-SIC substrate to optimize these electrical performances, multiple field-plates were used with aluminum oxide to split the single electric field peak into several smaller peaks, and as passivation works to reduce scaling leakage current. In the next, we include a modeling of a simulation in the Tcad-Silvaco Software for realizing the study of the influence of negative voltage applied to gate T-shaped in OFF state time and h

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Kourdi, Zakarya, and Hamdoun Abdelkhader. "A modeling and performance of the triple field plate HEMT." International Journal of Power Electronics and Drive System (IJPEDS) 10, no. 1 (2019): 398–405. https://doi.org/10.11591/ijpeds.v10.i1.pp398-405.

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We present this work by two steps. In the first one, the new structure proposed of the FP-HEMTs device (Field plate High Electron Mobility Transistor) with a T-gate on an 4H-SIC substrate to optimize these electrical performances, multiple field-plates were used with aluminum oxide to split the single electric field peak into several smaller peaks, and as passivation works to reduce scaling leakage current. In the next, we include a modeling of a simulation in the Tcad-Silvaco Software for realizing the study of the influence of negative voltage applied to gate T-shaped in OFF state time and h

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20

Gowthami, Y., B.Balaji, and K. Srinivasa Rao. "Qualitative Analysis & Advancement of Asymmetric Recessed Gates with Dual Floating Material GaN HEMT for Quantum Electronics." Journal of Integrated Circuits and Systems 18, no. 1 (2023): 1–8. http://dx.doi.org/10.29292/jics.v18i1.657.

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The Impact of Aluminium nitride (AlN) Spacer, Gallium Nitride (GaN) Cap Layer, Front Pi Gate (FG) and Back Pi Gate(BG), High K dielectric material such as Hafnium dioxide(HfO2), Aluminium Oxide (Al2O3), Silicon nitride (Si3N4) on Aluminium Galium Nitride/ Gallium Nitride (AlGaN/GaN), Heterojunction High Electron Mobility Transistor (HEMT) of 6nm(nanometer) technology is simulated and extracted the results using the Silvaco Atlas TCAD tool. The importance of High K dielectric materials like Al2O3 and Si3N4 are studied for the proposal of GaN HEMT. AlN, GaN Cap Layers, and High K Dielectric mate

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Dubey, Shashank Kumar, and Aminul Islam. "Al_0.30Ga_0.70N /GaN MODFET with triple-teeth metal for RF and high-power applications." Physica Scripta 97, no. 3 (2022): 034003. http://dx.doi.org/10.1088/1402-4896/ac50c3.

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Abstract A modulation-doped field-effect transistor (MODFET) has been investigated in this paper. It is also called HEMT (high electron mobility transistor). The proposed MODFET is made up of Al0.30Ga0.70N as supply layer and GaN as channel or buffer layer, in which floating metal is embedded. Its T-gate is recessed to obtain higher gm, which results in improved RF characteristics. T-gate is used to minimize the gate resistance which reduces the power consumption of the proposed HEMT. A floating metal having triple teeth (TT), which resembles a comb is developed in GaN channel/buffer layer bet

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Samuel, T. S. Arun, and S. Komalavalli. "Analytical Modelling and Simulation of Triple Material Quadruple Gate Tunnel Field Effect Transistors." Journal of Nano Research 54 (August 2018): 146–57. http://dx.doi.org/10.4028/www.scientific.net/jnanor.54.146.

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We build up the electrostatic model for Triple Material Quadruple Gate (TMQG) Tunnel Field Effect Transistor of rectangular cross area, in view of semi 3D strategy in this paper. The Parabolic approximation method is utilized to tackle the 2-D Poisson condition with appropriate device boundary conditions and logical articulations for surface potential and electric fields are determined. The electric field dispersion is additionally used to ascertain the tunneling generation rate. The created show furnishes the plan rules of TMQG with enhanced IONcurrent. The diagnostic outcomes are contrasted

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Pizzanelli, Riccardo, Rhaycen Prates, Marcelo Antonio Pavanello, and Michelly de Souza. "(Digital Presentation) Comparison of Width and Temperature Influence on DIBL Effect in Junctionless and Inversion Mode Nanowire MOSFETs." ECS Meeting Abstracts MA2023-01, no. 33 (2023): 1872. http://dx.doi.org/10.1149/ma2023-01331872mtgabs.

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Nanowire transistors constitute an alternative for the continuous downscaling of MOSFETs. These devices present a trigate architecture featuring the fin width (WFIN) and height (HFIN) with similar dimensions, in the order of tenths of nanometers [1], which improves the gate control on the channel charges, reducing short-channel effects (SCE) and improves electrical properties in both digital and analog applications [1]. Junctionless nanowire transistors (JL) are easier to fabricate than inversion-mode MOSFETs [2]. They also are less vulnerable to the occurrence of SCE, which is one of the main

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Et.al, R. Jeyarohini. "A performance Analysis of DM-DG and TM-DG TFETs Analytical Models for Low Power Applications." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 3 (2021): 4642–51. http://dx.doi.org/10.17762/turcomat.v12i3.1874.

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Device Modeling is utilized to engendering incipient device models for the demeanor of the electrical devices predicated on fundamental physics. Modeling of the device may also include the creation of Compact models. An emerging device type of transistor is the Tunnel Field-Effect transistor that achieves compactness and speed during device modeling. This article presents an analytical comparative study of duel material DG TFETs and triple Material DG TFETs with gate oxide structure . Here the implementation of device modeling is done by solving Poisson’s equation with Parabolic Approximation

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Liu, Fayong, Kouta Ibukuro, Muhammad Khaled Husain, et al. "Manipulation of random telegraph signals in a silicon nanowire transistor with a triple gate." Nanotechnology 29, no. 47 (2018): 475201. http://dx.doi.org/10.1088/1361-6528/aadfa6.

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Venkatesh, M., and N. B. Balamurugan. "New subthreshold performance analysis of germanium based dual halo gate stacked triple material surrounding gate tunnel field effect transistor." Superlattices and Microstructures 130 (June 2019): 485–98. http://dx.doi.org/10.1016/j.spmi.2019.05.016.

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Lima, Vitor Gonçalves, Guilherme Paim, Rodrigo Wuerdig, et al. "Enhancing Side Channel Attack-Resistance of the STTL Combining Multi-Vt Transistors with Capacitance and Current Paths Counterbalancing." Journal of Integrated Circuits and Systems 15, no. 1 (2020): 1–11. http://dx.doi.org/10.29292/jics.v15i1.100.

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Differential power analysis (DPA) exploits the difference between the instantaneous power of the circuit arches transitions to stole the state as information aiming to unveil the cryptographic key. Secure triple track logic (STTL) is a circuit-level countermeasure to DPA attacks based on dual-rail precharge logic (DPL). STTL is robust to attacks due to the delay in an insensitive feature that mitigates the logic glitches generated by the different path delays that lead to the logic gate inputs until they stabilize. The main STTL drawback, however, is the asymmetry of the transistor topology. A

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Kumar, A., A. Chaudhry, V. Kumar, and V. Sharma. "A Two Dimensional Surface Potential Model for Triple Material Double Gate Junctionless Field Effect Transistor." Journal of Nano- and Electronic Physics 8, no. 4(1) (2016): 04042–1. http://dx.doi.org/10.21272/jnep.8(4(1)).04042.

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Chien, Feng-Tso, Zhi-Zhe Wang, Cheng-Li Lin, Tsung-Kuei Kang, Chii-Wen Chen, and Hsien-Chin Chiu. "150–200 V Split-Gate Trench Power MOSFETs with Multiple Epitaxial Layers." Micromachines 11, no. 5 (2020): 504. http://dx.doi.org/10.3390/mi11050504.

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A rating voltage of 150 and 200 V split-gate trench (SGT) power metal-oxide- semiconductor field-effect transistor (Power MOSFET) with different epitaxial layers was proposed and studied. In order to reduce the specific on-resistance (Ron,sp) of a 150 and 200 V SGT power MOSFET, we used a multiple epitaxies (EPIs) structure to design it and compared other single-EPI and double-EPIs devices based on the same fabrication process. We found that the bottom epitaxial (EPI) layer of a double-EPIs structure can be designed to support the breakdown voltage, and the top one can be adjusted to reduce th

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Koide, Yasuo. "(Invited) Leading-Edge Diamond FET, MEMS, and Photodetector Devices." ECS Meeting Abstracts MA2023-02, no. 30 (2023): 1541. http://dx.doi.org/10.1149/ma2023-02301541mtgabs.

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Diamond is a candidate material for next-generation power electronics, micro-electro mechanical systems (MEMS), and solar-blind deep-ultraviolet (DUV) photodetector devices with excellent thermal stability and radiation hardness, which operate under extreme environment. In order to use an advantage of high-density hole channel of hydrogenated diamond (H-diamond) surface, we have developed the high-k stack gate dielectrics and AlN heterojuction gate for H-diamond FETs, such as HfO2/HfO2, LaAlO3/Al2O3 Ta2O5/Al2O3, and ZrO2/Al2O3, AlN/Al2O3 prepared by a combination of sputter-deposition (SD) and

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Kashem, Md Tashfiq Bin, and Samia Subrina. "Computational Analysis of Joule Heating Effect in Triple Material Gate AlGaN/GaN High Electron Mobility Transistor." ECS Transactions 102, no. 3 (2021): 43–52. http://dx.doi.org/10.1149/10203.0043ecst.

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Chawla, Tulika, Mamta Khosla, and Balwinder Raj. "Design and simulation of triple metal double-gate germanium on insulator vertical tunnel field effect transistor." Microelectronics Journal 114 (August 2021): 105125. http://dx.doi.org/10.1016/j.mejo.2021.105125.

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Kashem, Md Tashfiq Bin, and Samia Subrina. "Computational Analysis of Joule Heating Effect in Triple Material Gate AlGaN/GaN High Electron Mobility Transistor." ECS Meeting Abstracts MA2021-01, no. 33 (2021): 1074. http://dx.doi.org/10.1149/ma2021-01331074mtgabs.

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Mahdia, Marjana, and Quazi Deen Mohd Khosru. "Analytical modeling of transport phenomena in heterojunction triple metal gate all around tunneling field effect transistor." AIP Advances 10, no. 9 (2020): 095125. http://dx.doi.org/10.1063/5.0024864.

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Jeon, Jin-Hyeok, and Won-Ju Cho. "Triple Gate Polycrystalline-Silicon-Based Ion-Sensitive Field-Effect Transistor for High-Performance Aqueous Chemical Application." IEEE Electron Device Letters 40, no. 2 (2019): 318–20. http://dx.doi.org/10.1109/led.2018.2890741.

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Mushtaq, Umar, Leo Raj Solay, S. Intekhab Amin, and Sunny Anand. "Design and Analog Performance Analysis of Triple Material Gate Based Doping-Less Tunnel Field Effect Transistor." Journal of Nanoelectronics and Optoelectronics 14, no. 8 (2019): 1177–82. http://dx.doi.org/10.1166/jno.2019.2662.

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Boukortt, Nour El Islam, Baghdad Hadri, Alina Caddemi, Giovanni Crupi, and Salvatore Patane. "Temperature Dependence of Electrical Parameters of Silicon-on-Insulator Triple Gate n-Channel Fin Field Effect Transistor." Transactions on Electrical and Electronic Materials 17, no. 6 (2016): 329–34. http://dx.doi.org/10.4313/teem.2016.17.6.329.

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Shringi, Shivangi, Ashish Raman, Sarabdeep Singh, and Naveen Kumar. "Design and Analysis of Source Engineered with High Electron Mobility Material Triple Gate Junctionless Field Effect Transistor." Journal of Nanoelectronics and Optoelectronics 14, no. 6 (2019): 825–32. http://dx.doi.org/10.1166/jno.2019.2558.

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Saha, Priyanka, Rudra Sankar Dhar, Swagat Nanda, Kuleen Kumar, and Moath Alathbah. "The Optimization and Analysis of a Triple-Fin Heterostructure-on-Insulator Fin Field-Effect Transistor with a Stacked High-k Configuration and 10 nm Channel Length." Nanomaterials 13, no. 23 (2023): 3008. http://dx.doi.org/10.3390/nano13233008.

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The recent developments in the replacement of bulk MOSFETs with high-performance semiconductor devices create new opportunities in attaining the best device configuration with drive current, leakage current, subthreshold swing, Drain-Induced Barrier Lowering (DIBL), and other short-channel effect (SCE) parameters. Now, multigate FETs (FinFET and tri-gate (TG)) are advanced methodologies to continue the scaling of devices. Also, strain technology is used to gain a higher current drive, which raises the device performance, and high-k dielectric material is used to minimize the subthreshold curre

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Baral, Biswajit, Aloke Kumar Das, Debashis De, and Angsuman Sarkar. "An analytical model of triple-material double-gate metal-oxide-semiconductor field-effect transistor to suppress short-channel effects." International Journal of Numerical Modelling: Electronic Networks, Devices and Fields 29, no. 1 (2015): 47–62. http://dx.doi.org/10.1002/jnm.2044.

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41

Choudhury, Sagarika, Krishna Lal Baishnab, Koushik Guha, Zoran Jakšić, Olga Jakšić, and Jacopo Iannacci. "Modeling and Simulation of a TFET-Based Label-Free Biosensor with Enhanced Sensitivity." Chemosensors 11, no. 5 (2023): 312. http://dx.doi.org/10.3390/chemosensors11050312.

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This study discusses the use of a triple material gate (TMG) junctionless tunnel field-effect transistor (JLTFET) as a biosensor to identify different protein molecules. Among the plethora of existing types of biosensors, FET/TFET-based devices are fully compatible with conventional integrated circuits. JLTFETs are preferred over TFETs and JLFETs because of their ease of fabrication and superior biosensing performance. Biomolecules are trapped by cavities etched across the gates. An analytical mathematical model of a TMG asymmetrical hetero-dielectric JLTFET biosensor is derived here for the f

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Sharma, Dheeraj, Bhagwan Ram Raad, Dharmendra Singh Yadav, Pravin Kondekar, and Kaushal Nigam. "Two‐dimensional potential, electric field and drain current model of source pocket hetero gate dielectric triple work function tunnel field‐effect transistor." Micro & Nano Letters 12, no. 1 (2017): 11–16. http://dx.doi.org/10.1049/mnl.2016.0351.

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43

Venkatesh, M., M. Suguna, and N. B. Balamurugan. "Subthreshold Performance Analysis of Germanium Source Dual Halo Dual Dielectric Triple Material Surrounding Gate Tunnel Field Effect Transistor for Ultra Low Power Applications." Journal of Electronic Materials 48, no. 10 (2019): 6724–34. http://dx.doi.org/10.1007/s11664-019-07492-0.

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44

Popov, Vladimir P., Valentin A. Antonov, Andrey V. Miakonkikh, and Konstantin V. Rudenko. "Ion Drift and Polarization in Thin SiO2 and HfO2 Layers Inserted in Silicon on Sapphire." Nanomaterials 12, no. 19 (2022): 3394. http://dx.doi.org/10.3390/nano12193394.

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To reduce the built-in positive charge value at the silicon-on-sapphire (SOS) phase border obtained by bonding and a hydrogen transfer, thermal silicon oxide (SiO2) layers with a thickness of 50–310 nm and HfO2 layers with a thickness of 20 nm were inserted between silicon and sapphire by plasma-enhanced atomic layer deposition (PEALD). After high-temperature annealing at 1100 °C, these layers led to a hysteresis in the drain current–gate voltage curves and a field-induced switching of threshold voltage in the SOS pseudo-MOSFET. For the inserted SiO2 with a thickness of 310 nm, the transfer tr

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Borghei, Moein, and Mona Ghassemi. "Characterization of Partial Discharge Activities in WBG Power Converters under Low-Pressure Condition." Energies 14, no. 17 (2021): 5394. http://dx.doi.org/10.3390/en14175394.

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Many sectors, such as transportation systems, are undergoing rapid electrification due to the need for the mitigation of CO2 emissions. To ensure safe and reliable operation, the electrical equipment must be able to work under various environmental conditions. At high altitudes, the low pressure can adversely affect the health of insulating materials of electrical systems in electric aircraft. A well-known, primary aging mechanism in dielectrics is partial discharge (PD). This study targets internal PD evaluation in an insulated-gate bipolar transistor (IGBT) module under low-pressure conditio

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Choi, Sung-Hwan, Hee-Sun Shin, and Min-Koo Han. "Novel F-Shaped Triple-Gate Structure for Suppression of Kink Effect and Improvement of Hot Carrier Reliability in Low-Temperature Polycrystalline Silicon Thin-Film Transistor." Japanese Journal of Applied Physics 48, no. 4 (2009): 04C155. http://dx.doi.org/10.1143/jjap.48.04c155.

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Tsutsumi, Toshiyuki. "Very low and broad threshold voltage fluctuation caused by ion implantation to silicon-on-insulator triple-gate fin-type field effect transistor using three-dimensional process and device simulations." Japanese Journal of Applied Physics 56, no. 6S1 (2017): 06GF12. http://dx.doi.org/10.7567/jjap.56.06gf12.

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G., Naveen Balaji, Chenthur Pandian S., and Rajesh D. "High Performance Triplex Adder using CNTFET." International Journal of Trend in Scientific Research and Development 1, no. 5 (2017): 368–73. https://doi.org/10.31142/ijtsrd2300.

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Carbon Nanotubes Field Effect Transistors CNTFETs is used to implement a two new design of triplex half adder. conventional binary logic has a capable alternate called triplex logic, since it is possible to accomplish uncomplicatedness and energy efficiency in modern digital design due to shortened circuit overhead such as interconnect and chip area. Triplex decoders and binary logic gates are used to present two novel half adders. To obtain power, delay and power delay product the circuits are simulated using HSPICE . Recently reported designs are compared with these circuits. These triplex a

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NA, KYOUNG-IL, JUNG-HEE LEE, SORIN CRISTOLOVEANU, YOUNG-HO BAE, PAUL PATRUNO, and WADE XIONG. "SHORT CHANNEL, FLOATING BODY, AND 3D COUPLING EFFECTS IN TRIPLE-GATE MOSFET." International Journal of High Speed Electronics and Systems 18, no. 04 (2008): 773–82. http://dx.doi.org/10.1142/s0129156408005758.

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We have investigated the short-channel effect (SCE), floating-body effect, and three-dimensional coupling effect in triple-gate MOSFET with various fin widths, gate lengths and number of fins. It is found that the SCE of these devices is alleviated as the fin width shrinks and does not depend on the number of fins. The gate-induced floating-body effect (GIFBE) is visible even in fully depleted (FD) triple-gate transistors when the film-buried oxide (BOX) interface is swept from depletion to accumulation by the back-gate bias. The 3-D coupling effect in vertical, lateral, and longitudinal direc

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Yang, J. W., and J. G. Fossum. "On the Feasibility of Nanoscale Triple-Gate CMOS Transistors." IEEE Transactions on Electron Devices 52, no. 6 (2005): 1159–64. http://dx.doi.org/10.1109/ted.2005.848109.

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