Bibliografías temáticas / Coarse-Grained Reconfigurable Architecture

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Literatura académica sobre el tema "Coarse-Grained Reconfigurable Architecture"

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Publicado: 4 de junio de 2021
Última modificación: 6 de septiembre de 2023

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Artículos de revistas sobre el tema "Coarse-Grained Reconfigurable Architecture"

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Lopes, João D., Mário P. Véstias, Rui Policarpo Duarte , Horácio C. Neto y José T. de Sousa. "Coarse-Grained Reconfigurable Computing with the Versat Architecture". Electronics 10, n.º 6 (12 de marzo de 2021): 669. http://dx.doi.org/10.3390/electronics10060669.

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Reconfigurable computing architectures allow the adaptation of the underlying datapath to the algorithm. The granularity of the datapath elements and data width determines the granularity of the architecture and its programming flexibility. Coarse-grained architectures have shown the right balance between programmability and performance. This paper provides an overview of coarse-grained reconfigurable architectures and describes Versat, a Coarse-Grained Reconfigurable Array (CGRA) with self-generated partial reconfiguration, presented as a case study for better understanding these architectures. Unlike most of the existing approaches, which mainly use pre-compiled configurations, a Versat program can generate and apply myriads of on-the-fly configurations. Partial reconfiguration plays a central role in this approach, as it speeds up the generation of incrementally different configurations. The reconfigurable array has a complete graph topology, which yields unprecedented programmability, including assembly programming. Besides being useful for optimising programs, assembly programming is invaluable for working around post-silicon hardware, software, or compiler issues. Results on core area, frequency, power, and performance running different codes are presented and compared to other implementations.
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Paek, Jong Kyung, Kiyoung Choi y Jongeun Lee. "Binary acceleration using coarse-grained reconfigurable architecture". ACM SIGARCH Computer Architecture News 38, n.º 4 (14 de septiembre de 2010): 33–39. http://dx.doi.org/10.1145/1926367.1926374.

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Wijtvliet, Mark, Henk Corporaal y Akash Kumar. "CGRA-EAM—Rapid Energy and Area Estimation for Coarse-grained Reconfigurable Architectures". ACM Transactions on Reconfigurable Technology and Systems 14, n.º 4 (31 de diciembre de 2021): 1–28. http://dx.doi.org/10.1145/3468874.

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Reconfigurable architectures are quickly gaining in popularity due to their flexibility and ability to provide high energy efficiency. However, reconfigurable systems allow for a huge design space. Iterative design space exploration (DSE) is often required to achieve good Pareto points with respect to some combination of performance, area, and/or energy. DSE tools depend on information about hardware characteristics in these aspects. These characteristics can be obtained from hardware synthesis and net-list simulation, but this is very time-consuming. Therefore, architecture models are common. This work introduces CGRA-EAM (Coarse-Grained Reconfigurable Architecture - Energy & Area Model), a model for energy and area estimation framework for coarse-grained reconfigurable architectures. The model is evaluated for the Blocks CGRA. The results demonstrate that the mean absolute percentage error is 15.5% and 2.1% for energy and area, respectively, while the model achieves a speedup of close to three orders of magnitude compared to synthesis.
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Thomas, Alexander, Michael Rückauer y Jürgen Becker. "HoneyComb: An Application-Driven Online Adaptive Reconfigurable Hardware Architecture". International Journal of Reconfigurable Computing 2012 (2012): 1–17. http://dx.doi.org/10.1155/2012/832531.

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Since the introduction of the first reconfigurable devices in 1985 the field of reconfigurable computing developed a broad variety of architectures from fine-grained to coarse-grained types. However, the main disadvantages of the reconfigurable approaches, the costs in area, and power consumption, are still present. This contribution presents a solution for application-driven adaptation of our reconfigurable architecture at register transfer level (RTL) to reduce the resource requirements and power consumption while keeping the flexibility and performance for a predefined set of applications. Furthermore, implemented runtime adaptive features like online routing and configuration sequencing will be presented and discussed. A presentation of the prototype chip of this architecture designed in 90 nm standard cell technology manufactured by TSMC will conclude this contribution.
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YIN, Shouyi, Chongyong YIN, Leibo LIU, Min ZHU y Shaojun WEI. "Configuration Context Reduction for Coarse-Grained Reconfigurable Architecture". IEICE Transactions on Information and Systems E95-D, n.º 2 (2012): 335–44. http://dx.doi.org/10.1587/transinf.e95.d.335.

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Wang, Chao, Peng Cao y Jun Yang. "Efficient AES cipher on coarse-grained reconfigurable architecture". IEICE Electronics Express 14, n.º 11 (2017): 20170449. http://dx.doi.org/10.1587/elex.14.20170449.

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Choi, Kiyoung. "Coarse-Grained Reconfigurable Array: Architecture and Application Mapping". IPSJ Transactions on System LSI Design Methodology 4 (2011): 31–46. http://dx.doi.org/10.2197/ipsjtsldm.4.31.

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Atak, Oguzhan y Abdullah Atalar. "BilRC: An Execution Triggered Coarse Grained Reconfigurable Architecture". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21, n.º 7 (julio de 2013): 1285–98. http://dx.doi.org/10.1109/tvlsi.2012.2207748.

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Kim, Yoonjin, Hyejin Joo y Sohyun Yoon. "Inter‐coarse‐grained reconfigurable architecture reconfiguration technique for efficient pipelining of kernel‐stream on coarse‐grained reconfigurable architecture‐based multi‐core architecture". IET Circuits, Devices & Systems 10, n.º 4 (julio de 2016): 251–65. http://dx.doi.org/10.1049/iet-cds.2015.0047.

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Munaf, S., Dr A. Bharathi y Dr A. N. Jayanthi. "Double Pumping Low Power Technique for Coarse - Grained Reconfigurable Architecture". International Journal of Electrical and Electronics Research 4, n.º 1 (31 de marzo de 2016): 10–15. http://dx.doi.org/10.37391/ijeer.040103.

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Coarse-grained reconfigurable architectures (CGRAs) require many processing elements (PEs) and a con- figuration memory unit (configuration cache) for reconfiguration of its PE array. Though this architecture is meant for high performance and flexibility. Power reduction is very crucial for CGRA to be more competitive and reliable processing core in embedded systems. We propose a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) architecture to reduce power-overhead caused by reconfiguration. The power reduction can be achieved by using the characteristics like double pumping the data bus and an I/O buffer between the memory and the data bus of DDR SDRAM. All modules have been designed at behavioral level with VHDL coding and to Simulate in Xilinx ISE navigator.
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Tesis sobre el tema "Coarse-Grained Reconfigurable Architecture"

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Guo, Yuanqing. "Mapping applications to a coarse-grained reconfigurable architecture". Enschede : University of Twente [Host], 2006. http://doc.utwente.nl/57121.

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Lee, Jong-Suk Mark. "FleXilicon: a New Coarse-grained Reconfigurable Architecture for Multimedia and Wireless Communications". Diss., Virginia Tech, 2010. http://hdl.handle.net/10919/77094.

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High computing power and flexibility are important design factors for multimedia and wireless communication applications due to the demand for high quality services and frequent evolution of standards. The ASIC (Application Specific Integrated Circuit) approach provides an area efficient, high performance solution, but is inflexible. In contrast, the general purpose processor approach is flexible, but often fails to provide sufficient computing power. Reconfigurable architectures, which have been introduced as a compromise between the two extreme solutions, have been applied successfully for multimedia and wireless communication applications. In this thesis, we investigated a new coarse-grained reconfigurable architecture called FleXilicon which is designed to execute critical loops efficiently, and is embedded in an SOC with a host processor. FleXilicon improves resource utilization and achieves a high degree of loop level parallelism (LLP). The proposed architecture aims to mitigate major shortcomings with existing architectures through adoption of three schemes, (i) wider memory bandwidth, (ii) adoption of a reconfigurable controller, and (iii) flexible wordlength support. Increased memory bandwidth satisfies memory access requirement in LLP execution. New design of reconfigurable controller minimizes overhead in reconfiguration and improves area efficiency and reconfiguration overhead. Flexible word-length support improves LLP by increasing the number of processing elements executable. The simulation results indicate that FleXilicon reduces the number of clock cycles and increases the speed for all five applications simulated. The speedup ratios compared with conventional architectures are as large as two orders of magnitude for some applications. VLSI implementation of FleXilicon in 65 nm CMOS process indicates that the proposed architecture can operate at a high frequency up to 1 GHz with moderate silicon area.
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3

Yang, Yu. "BENCHMARK OF TRIGGERED INSTRUCTION BASED COARSE GRAINED RECONFIGURABLE ARCHITECTURE FOR RADIO BASE STATION". Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-177446.

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Spatially-programmed architectures such as FPGA are among the most prevailing hardware in various application areas. However FPGA suffers from great overheads such as area, latency and power efficiency. Coarse-grained Reconfigurable Architecture (CGRA) is designed in order to compensate these disadvantages of FPGA. In this thesis, a Triggered Instruction based novel CGRA designed by Intel is evaluated. Benchmark work in this thesis focuses on signal processing area. Three performance limiting functions, Channel Estimation, Radix-2 FFT and Interleaving are selected from LTE Uplink Receiver PHY Benchmark which is an open source benchmark, and implemented and analyzed in Triggered Instruction Architecture (TIA). Throughput-area relationships and throughput/area-area relationships are summarized in curves using a resource estimation method. The benchmark result shows that TIA offers good flexibility for temporal and spatial execution, and a mix of them. Designs in TIA are scalable and adjustable according to different performance requirement. Moreover, based on the development work, this thesis discusses development flow of TIA, various programming techniques, low latency mapping solutions, code size comparison, development environment and integration of heterogeneous system with TIA.
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Malik, Omer. "Pragma-Based Approach For Mapping DSP Functions On A Coarse Grained Reconfigurable Architecture". Licentiate thesis, KTH, Elektronik och Inbyggda System, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-166410.

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Zhao, Xin. "High efficiency coarse-grained customised dynamically reconfigurable architecture for digital image processing and compression technologies". Thesis, University of Edinburgh, 2012. http://hdl.handle.net/1842/6187.

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Digital image processing and compression technologies have significant market potential, especially the JPEG2000 standard which offers outstanding codestream flexibility and high compression ratio. Strong demand for high performance digital image processing and compression system solutions is forcing designers to seek proper architectures that offer competitive advantages in terms of all performance metrics, such as speed and power. Traditional architectures such as ASIC, FPGA and DSPs have limitations in either low flexibility or high power consumption. On the other hand, through the provision of a degree of flexibility similar to that of a DSP and performance and power consumption advantages approaching that of an ASIC, coarse-grained dynamically reconfigurable architectures are proving to be strong candidates for future high performance digital image processing and compression systems. This thesis investigates dynamically reconfigurable architectures and especially the newly emerging RICA paradigm. Case studies such as Reed- Solomon decoder and WiMAX OFDM timing synchronisation engine are implemented in order to explore the potential of RICA-based architectures and the possible optimisation approaches such as eliminating conditional branches, reducing memory accesses and constructing kernels. Based on investigations in this thesis, a novel customised dynamically reconfigurable architecture targeting digital image processing and compression applications is devised, which can be tailored to adopt different applications. A demosaicing engine based on the Freeman algorithm is designed and implemented on the proposed architecture as the pre-processing module in a digital imaging system. An efficient data buffer rotating scheme is designed with the aim of reducing memory accesses. Meanwhile an investigation targeting mapping the demosaicing engine onto a dual-core RICA platform is performed. After optimisation, the performance of the proposed engine is carefully evaluated and compared in aspects of throughput and consumed computational resources. When targeting the JPEG2000 standard, the core tasks such as 2-D Discrete Wavelet Transform (DWT) and Embedded Block Coding with Optimal Truncation (EBCOT) are implemented and optimised on the proposed architecture. A novel 2-D DWT architecture based on vector operations associated with RICA paradigm is developed, and the complete DWT application is highly optimised for both throughput and area. For the EBCOT implementation, a novel Partial Parallel Architecture (PPA) for the most computationally intensive module in EBCOT, termed Context Modeling (CM), is devised. Based on the algorithm evaluation, an ARM core is integrated into the proposed architecture for performance enhancement. A Ping-Pong memory switching mode with carefully designed communication scheme between RICA based architecture and ARM is proposed. Simulation results demonstrate that the proposed architecture for JPEG2000 offers significant advantage in throughput.
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Saraswat, Rohit. "A Finite Domain Constraint Approach for Placement and Routing of Coarse-Grained Reconfigurable Architectures". DigitalCommons@USU, 2010. https://digitalcommons.usu.edu/etd/689.

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Scheduling, placement, and routing are important steps in Very Large Scale Integration (VLSI) design. Researchers have developed numerous techniques to solve placement and routing problems. As the complexity of Application Specific Integrated Circuits (ASICs) increased over the past decades, so did the demand for improved place and route techniques. The primary objective of these place and route approaches has typically been wirelength minimization due to its impact on signal delay and design performance. With the advent of Field Programmable Gate Arrays (FPGAs), the same place and route techniques were applied to FPGA-based design. However, traditional place and route techniques may not work for Coarse-Grained Reconfigurable Architectures (CGRAs), which are reconfigurable devices offering wider path widths than FPGAs and more flexibility than ASICs, due to the differences in architecture and routing network. Further, the routing network of several types of CGRAs, including the Field Programmable Object Array (FPOA), has deterministic timing as compared to the routing fabric of most ASICs and FPGAs reported in the literature. This necessitates a fresh look at alternative approaches to place and route designs. This dissertation presents a finite domain constraint-based, delay-aware placement and routing methodology targeting an FPOA. The proposed methodology takes advantage of the deterministic routing network of CGRAs to perform a delay aware placement.
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Das, Satyajit. "Architecture and Programming Model Support for Reconfigurable Accelerators in Multi-Core Embedded Systems". Thesis, Lorient, 2018. http://www.theses.fr/2018LORIS490/document.

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La complexité des systèmes embarqués et des applications impose des besoins croissants en puissance de calcul et de consommation énergétique. Couplé au rendement en baisse de la technologie, le monde académique et industriel est toujours en quête d'accélérateurs matériels efficaces en énergie. L'inconvénient d'un accélérateur matériel est qu'il est non programmable, le rendant ainsi dédié à une fonction particulière. La multiplication des accélérateurs dédiés dans les systèmes sur puce conduit à une faible efficacité en surface et pose des problèmes de passage à l'échelle et d'interconnexion. Les accélérateurs programmables fournissent le bon compromis efficacité et flexibilité. Les architectures reconfigurables à gros grains (CGRA) sont composées d'éléments de calcul au niveau mot et constituent un choix prometteur d'accélérateurs programmables. Cette thèse propose d'exploiter le potentiel des architectures reconfigurables à gros grains et de pousser le matériel aux limites énergétiques dans un flot de conception complet. Les contributions de cette thèse sont une architecture de type CGRA, appelé IPA pour Integrated Programmable Array, sa mise en œuvre et son intégration dans un système sur puce, avec le flot de compilation associé qui permet d'exploiter les caractéristiques uniques du nouveau composant, notamment sa capacité à supporter du flot de contrôle. L'efficacité de l'approche est éprouvée à travers le déploiement de plusieurs applications de traitement intensif. L'accélérateur proposé est enfin intégré à PULP, a Parallel Ultra-Low-Power Processing-Platform, pour explorer le bénéfice de ce genre de plate-forme hétérogène ultra basse consommation
Emerging trends in embedded systems and applications need high throughput and low power consumption. Due to the increasing demand for low power computing and diminishing returns from technology scaling, industry and academia are turning with renewed interest toward energy efficient hardware accelerators. The main drawback of hardware accelerators is that they are not programmable. Therefore, their utilization can be low is they perform one specific function and increasing the number of the accelerators in a system on chip (SoC) causes scalability issues. Programmable accelerators provide flexibility and solve the scalability issues. Coarse-Grained Reconfigurable Array (CGRA) architecture consisting of several processing elements with word level granularity is a promising choice for programmable accelerator. Inspired by the promising characteristics of programmable accelerators, potentials of CGRAs in near threshold computing platforms are studied and an end-to-end CGRA research framework is developed in this thesis. The major contributions of this framework are: CGRA design, implementation, integration in a computing system, and compilation for CGRA. First, the design and implementation of a CGRA named Integrated Programmable Array (IPA) is presented. Next, the problem of mapping applications with control and data flow onto CGRA is formulated. From this formulation, several efficient algorithms are developed using internal resources of a CGRA, with a vision for low power acceleration. The algorithms are integrated into an automated compilation flow. Finally, the IPA accelerator is augmented in PULP - a Parallel Ultra-Low-Power Processing-Platform to explore heterogeneous computing
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Peyret, Thomas. "Architecture matérielle et flot de programmation associé pour la conception de systèmes numériques tolérants aux fautes". Thesis, Lorient, 2014. http://www.theses.fr/2014LORIS348/document.

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Que ce soit dans l’automobile avec des contraintes thermiques ou dans l’aérospatial et lenucléaire soumis à des rayonnements ionisants, l’environnement entraîne l’apparition de fautesdans les systèmes électroniques. Ces fautes peuvent être transitoires ou permanentes et vontinduire des résultats erronés inacceptables dans certains contextes applicatifs. L’utilisation decomposants dits « rad-hard » est parfois compromise par leurs coûts élevés ou les difficultésd’approvisionnement liés aux règles d’exportation.Cette thèse propose une approche conjointe matérielle et logicielle indépendante de la technologied’intégration permettant d’utiliser des composants numériques programmables dans desenvironnements susceptibles de générer des fautes. Notre proposition comporte la définitiond’une Architecture Reconfigurable à Gros Grains (CGRA) capable d’exécuter des codes applicatifscomplets mais aussi l’ensemble des mécanismes matériels et logiciels permettant de rendrecette architecture tolérante aux fautes. Ce résultat est obtenu par l’association de redondance etde reconfiguration dynamique du CGRA en s’appuyant sur une banque de configurations généréepar une chaîne de programmation complète. Cette chaîne outillée repose sur un flot permettantde porter un code sous forme de Control and Data Flow Graph (CDFG) sur l’architecture enobtenant un grand nombre de configurations différentes et qui permet d’exploiter au mieux lepotentiel de l’architecture.Les travaux, qui ont été validés aux travers d’expériences sur des applications du domaine dutraitement du signal et de l’image, ont fait l’objet de publications en conférences internationaleset de dépôts de brevets
Whether in automotive with heat stress or in aerospace and nuclear field subjected to cosmic,neutron and gamma radiation, the environment can lead to the development of faults in electronicsystems. These faults, which can be transient or permanent, will lead to erroneous results thatare unacceptable in some application contexts. The use of so-called rad-hard components issometimes compromised due to their high costs and supply problems associated with exportrules.This thesis proposes a joint hardware and software approach independent of integrationtechnology for using digital programmable devices in environments that generate faults. Ourapproach includes the definition of a Coarse Grained Reconfigurable Architecture (CGRA) ableto execute entire application code but also all the hardware and software mechanisms to make ittolerant to transient and permanent faults. This is achieved by the combination of redundancyand dynamic reconfiguration of the CGRA based on a library of configurations generated by acomplete conception flow. This implemented flow relies on a flow to map a code represented as aControl and Data Flow Graph (CDFG) on the CGRA architecture by obtaining directly a largenumber of different configurations and allows to exploit the full potential of architecture.This work, which has been validated through experiments with applications in the field ofsignal and image processing, has been the subject of two publications in international conferencesand of two patents
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Zain-ul-Abdin. "Programming of coarse-grained reconfigurable architectures". Doctoral thesis, Örebro universitet, Akademin för naturvetenskap och teknik, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:oru:diva-15246.

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Coarse-grained reconfigurable architectures, which offer massive parallelism coupled with the capability of undergoing run-time reconfiguration, are gaining attention in order to meet not only the increased computational demands of high-performance embedded systems, but also to fulfill the need of adaptability to functional requirements of the application. This thesis focuses on the programming aspects of such coarse-grained reconfigurable computing devices, including the relevant computation models that are capable of exposing different kinds of parallelism inherent in the application and the ability of these models to capture the adaptability requirements of the application. The thesis suggests the occam-pi language for programming of a broad class of coarse-grained reconfigurable architectures as an intermediate language; we call it intermediate, since we believe that the applicationprogramming is best done in a high-level domain-specific language. The salient properties of the occam-pi language are explicit concurrency with built-in mechanisms for interprocessorcommunication, provision for expressing dynamic parallelism, support for the expression of dynamic reconfigurations, and placement attributes. To evaluate the programming approach, a compiler framework was extended to support the language extensions in the occam-pi language, and backends were developed to target two different coarse-grained reconfigurable architectures. XPP and Ambric. The results on XPP reveal that the occam-pi based implementations produce comparable throughput to those of NML programs, while programming at a much higher level of abstraction than that of NML. Similarly the two occam-pi implementations of autofocus criterion calculation targeted to the Ambric platform outperform the CPU implementation by factors of 11-23. Thus, the results of the implemented case-studies suggest that the occam-pi language based approach simplifies the development of applications employing run-time reconfigurable devices without compromising the performance benefits.
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Ul-Abdin, Zain. "Programming of Coarse-Grained Reconfigurable Architectures". Doctoral thesis, Högskolan i Halmstad, Centrum för forskning om inbyggda system (CERES), 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-15050.

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Coarse-grained reconfigurable architectures, which offer massive parallelism coupled with the capability of undergoing run-time reconfiguration, are gaining attention in order to meet not only the increased computational demands of high-performance embedded systems, but also to fulfill the need of adaptability to functional requirements of the application. This thesis focuses on the programming aspects of such coarse-grained reconfigurable computing devices, including the relevant computation models that are capable of exposing different kinds of parallelism inherent in the application and the ability of these models to capture the adaptability requirements of the application. The thesis suggests the occam-pi language for programming of a broad class of coarse-grained reconfigurable architectures as an intermediate language; we call it intermediate, since we believe that the applicationprogramming is best done in a high-level domain-specific language. The salient properties of the occam-pi language are explicit concurrency with built-in mechanisms for interprocessorcommunication, provision for expressing dynamic parallelism, support for the expression of dynamic reconfigurations, and placement attributes. To evaluate the programming approach, a compiler framework was extended to support the language extensions in the occam-pi language, and backends were developed to target two different coarse-grained reconfigurable architectures. XPP and Ambric. The results on XPP reveal that the occam-pi based implementations produce comparable throughput to those of NML programs, while programming at a much higher level of abstraction than that of NML. Similarly the two occam-pi implementations of autofocus criterion calculation targeted to the Ambric platform outperform the CPU implementation by factors of 11-23. Thus, the results of the implemented case-studies suggest that the occam-pi language based approach simplifies the development of applications employing run-time reconfigurable devices without compromising the performance benefits.
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Libros sobre el tema "Coarse-Grained Reconfigurable Architecture"

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N, Mahapatra Rabi, ed. Design of low-power coarse-grained reconfigurable architectures. Boca Raton, FL: CRC Press, 2011.

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Wijtvliet, Mark, Henk Corporaal y Akash Kumar. Blocks, Towards Energy-efficient, Coarse-grained Reconfigurable Architectures. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-030-79774-4.

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Mahapatra, Rabi N. y Yoonjin Kim. Design of Low-Power Coarse-Grained Reconfigurable Architectures. Taylor & Francis Group, 2010.

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Mahapatra, Rabi N. y Yoonjin Kim. Design of Low-Power Coarse-Grained Reconfigurable Architectures. Taylor & Francis Group, 2017.

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Mahapatra, Rabi N. y Yoonjin Kim. Design of Low-Power Coarse-Grained Reconfigurable Architectures. Taylor & Francis Group, 2010.

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Mahapatra, Rabi N. y Yoonjin Kim. Design of Low-Power Coarse-Grained Reconfigurable Architectures. Taylor & Francis Group, 2010.

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Corporaal, Henk, Akash Kumar y Mark Wijtvliet. Blocks, Towards Energy-Efficient, Coarse-grained Reconfigurable Architectures. Springer International Publishing AG, 2021.

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Corporaal, Henk, Akash Kumar y Mark Wijtvliet. Blocks, Towards Energy-Efficient, Coarse-grained Reconfigurable Architectures. Springer International Publishing AG, 2022.

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Capítulos de libros sobre el tema "Coarse-Grained Reconfigurable Architecture"

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Wijtvliet, Mark, Henk Corporaal y Akash Kumar. "Concept of the Blocks Architecture". En Blocks, Towards Energy-efficient, Coarse-grained Reconfigurable Architectures, 61–92. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-79774-4_3.

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Bouwens, Frank, Mladen Berekovic, Bjorn De Sutter y Georgi Gaydadjiev. "Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array". En High Performance Embedded Architectures and Compilers, 66–81. Berlin, Heidelberg: Springer Berlin Heidelberg, 2008. http://dx.doi.org/10.1007/978-3-540-77560-7_6.

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Xu, Jinhui, Guiming Wu, Yong Dou y Yazhuo Dong. "Designing a Coarse-Grained Reconfigurable Architecture Using Loop Self-Pipelining". En Advances in Computer Systems Architecture, 567–73. Berlin, Heidelberg: Springer Berlin Heidelberg, 2006. http://dx.doi.org/10.1007/11859802_59.

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de Moura, Rafael Fão, Michael Guilherme Jordan, Antonio Carlos Schneider Beck y Mateus Beck Rutzig. "Exploiting Partial Reconfiguration on a Dynamic Coarse Grained Reconfigurable Architecture". En Applied Reconfigurable Computing. Architectures, Tools, and Applications, 355–66. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-78890-6_29.

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Käsgen, Philipp S., Markus Weinhardt y Christian Hochberger. "Dynamic Scheduling of Pipelined Functional Units in Coarse-Grained Reconfigurable Array Elements". En Architecture of Computing Systems – ARCS 2019, 156–67. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-18656-2_12.

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Ngouanga, Alex, Gilles Sassatelli, Lionel Torres, Thierry Gil, André Borin Suarez y Altamiro Amadeu Susin. "Run-Time Resources Management on Coarse Grained, Packet-Switching Reconfigurable Architecture: A Case Study Through the APACHES’ Platform". En Reconfigurable Computing: Architectures and Applications, 134–45. Berlin, Heidelberg: Springer Berlin Heidelberg, 2006. http://dx.doi.org/10.1007/11802839_19.

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Lee, Ganghee, Seokhyun Lee, Kiyoung Choi y Nikil Dutt. "Routing-Aware Application Mapping Considering Steiner Points for Coarse-Grained Reconfigurable Architecture". En Lecture Notes in Computer Science, 231–43. Berlin, Heidelberg: Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-12133-3_22.

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Jiao, Yuzhong, Xin’an Wang y Xuewen Ni. "A Fully Data-Driven Reconfigurable Architecture with Very Coarse-Grained Execution Units". En Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, 1–13. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-642-10485-5_1.

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Chen, Ren, Lu Ma, Du Yue, Wen Wen y Zhi Qi. "Hierarchy Modeling and Co-simulation of a Dynamically Coarse-Grained Reconfigurable Architecture". En Informatics in Control, Automation and Robotics, 589–98. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-25992-0_80.

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Mei, Bingfeng, Serge Vernalde, Diederik Verkest, Hugo De Man y Rudy Lauwereins. "ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix". En Field Programmable Logic and Application, 61–70. Berlin, Heidelberg: Springer Berlin Heidelberg, 2003. http://dx.doi.org/10.1007/978-3-540-45234-8_7.

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Actas de conferencias sobre el tema "Coarse-Grained Reconfigurable Architecture"

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Deng, Jinyi, Linyun Zhang, Lei Wang, Jiawei Liu, Kexiang Deng, Shibin Tang, Jiangyuan Gu et al. "Mixed-granularity parallel coarse-grained reconfigurable architecture". En DAC '22: 59th ACM/IEEE Design Automation Conference. New York, NY, USA: ACM, 2022. http://dx.doi.org/10.1145/3489517.3530454.

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Yin, Shouyi, Chongyong Yin, Leibo Liu, Min Zhu, Yansheng Wang y Shaojun Wei. "Reducing configuration contexts for coarse-grained reconfigurable architecture". En 2012 IEEE International Symposium on Circuits and Systems - ISCAS 2012. IEEE, 2012. http://dx.doi.org/10.1109/iscas.2012.6271452.

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Azad, Siavoosh Payandeh, Nasim Farahini y Ahmed Hemani. "Customization methodology of a Coarse Grained Reconfigurable architecture". En 2014 NORCHIP. IEEE, 2014. http://dx.doi.org/10.1109/norchip.2014.7004736.

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Jo, Manhwee, Ganghee Lee, Kyungwook Chang, Kyuseung Han, Kiyoung Choi, Hoonmo Yang y Kiwook Yoon. "Coarse-grained reconfigurable architecture for multiple application domains". En the 2009 International Conference. New York, New York, USA: ACM Press, 2009. http://dx.doi.org/10.1145/1644993.1645095.

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Cao, Lan, Xinhong Hao y Xiaolin Chen. "Automatic visualization interface for coarse grained reconfigurable architecture". En 2013 6th International Conference on Biomedical Engineering and Informatics (BMEI). IEEE, 2013. http://dx.doi.org/10.1109/bmei.2013.6747033.

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Alnajiar, Dawood, Younghun Ko, Takashi Imagawa, Hiroaki Konoura, Masayuki Hiromoto, Yukio Mitsuyama, Masanori Hashimoto, Hiroyuki Ochi y Takao Onoye. "Coarse-grained dynamically reconfigurable architecture with flexible reliability". En 2009 International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2009. http://dx.doi.org/10.1109/fpl.2009.5272317.

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Ran, Duan y Liang Jie. "A Mapping Strategy for Coarse-grained Reconfigurable Architecture". En 2011 First International Conference on Instrumentation, Measurement, Computer, Communication and Control (IMCCC). IEEE, 2011. http://dx.doi.org/10.1109/imccc.2011.164.

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Akbari, Omid, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram y Muhammad Shafique. "PX-CGRA: Polymorphic approximate coarse-grained reconfigurable architecture". En 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2018. http://dx.doi.org/10.23919/date.2018.8342045.

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Rakossy, Zoltan Endre, Tejas Naphade y Anupam Chattopadhyay. "Design and analysis of layered coarse-grained reconfigurable architecture". En 2012 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2012). IEEE, 2012. http://dx.doi.org/10.1109/reconfig.2012.6416736.

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Padole, Dinesh y Rahul Hiware. "Configuration memory based dynamic coarse grained reconfigurable multicore architecture". En TENCON 2013 - 2013 IEEE Region 10 Conference. IEEE, 2013. http://dx.doi.org/10.1109/tencon.2013.6719038.

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