Bibliografías temáticas / Electrical and Computer Engineering. Metal oxide semiconductors

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Literatura académica sobre el tema "Electrical and Computer Engineering. Metal oxide semiconductors"

Autor: Grafiati
Publicado: 4 de junio de 2021
Última modificación: 16 de febrero de 2022

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Artículos de revistas sobre el tema "Electrical and Computer Engineering. Metal oxide semiconductors"

1

Saha, H., and C. Chaudhuri. "Complementary Metal Oxide Semiconductors Microelectromechanical Systems Integration." Defence Science Journal 59, no. 6 (2009): 557–67. http://dx.doi.org/10.14429/dsj.59.1560.

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Chavan, YV, and DK Mishra. "Improved Complementary Metal Oxide Semiconductor Digital Pixel Sensor." IETE Journal of Research 55, no. 5 (2009): 222. http://dx.doi.org/10.4103/0377-2063.57600.

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Fadavi Roudsari, Anita, Iman Khodadad, Simarjeet Singh Saini, and M. P. Anantram. "Photon-Induced Negative Capacitance in Metal Oxide Semiconductor Structures." IEEE Transactions on Nanotechnology 15, no. 5 (2016): 715–19. http://dx.doi.org/10.1109/tnano.2016.2519897.

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Zhou, Huimei, Bei Li, Zheng Yang, et al. "$\hbox{TiSi}_{2}$ Nanocrystal Metal Oxide Semiconductor Field Effect Transistor Memory." IEEE Transactions on Nanotechnology 10, no. 3 (2011): 499–505. http://dx.doi.org/10.1109/tnano.2010.2049271.

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McDonough, Colin, Doug La Tulipe, Dan Pascual, et al. "Heterogeneous Integration of a 300-mm Silicon Photonics-CMOS Wafer Stack by Direct Oxide Bonding and Via-Last 3-D Interconnection." Journal of Microelectronics and Electronic Packaging 13, no. 2 (2016): 71–76. http://dx.doi.org/10.4071/imaps.494.

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A fully functional Si photonics and 65-nm complementary metal-oxide semiconductor (CMOS) heterogeneous three-dimensional (3-D) integration is demonstrated for the first time in a 300-mm production environment. Direct oxide wafer bonding was developed to eliminate voids between silicon on insulator photonics and bulk Si CMOS wafers. A via-last, Cu through-oxide via 3-D integration was developed for low capacitance electrical connections with no impact on the CMOS performance. The 3-D yield approaching 100% was demonstrated on >20,000 via chains.
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6

Yoshikawa, Masahito, Takeshi Ohshima, Hisayoshi Itoh, et al. "Effects of gamma-ray irradiation on the electrical characteristics of SiC metal-oxide-semiconductor structures." Electronics and Communications in Japan (Part II: Electronics) 81, no. 10 (1998): 37–47. http://dx.doi.org/10.1002/(sici)1520-6432(199810)81:10<37::aid-ecjb5>3.0.co;2-h.

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Ghosh, Sumalya, Bishnu Prasad De, Rajib Kar, Durbadal Mandal, and Ashis Kumar Mal. "Optimal design of complementary metal-oxide-semiconductor analogue circuits: An evolutionary approach." Computers & Electrical Engineering 80 (December 2019): 106485. http://dx.doi.org/10.1016/j.compeleceng.2019.106485.

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Krik, Soufiane, Andrea Gaiardo, Matteo Valt, et al. "First-Principles Study of Electronic Conductivity, Structural and Electronic Properties of Oxygen-Vacancy-Defected SnO2." Journal of Nanoscience and Nanotechnology 21, no. 4 (2021): 2633–40. http://dx.doi.org/10.1166/jnn.2021.19116.

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The use of computer simulations has become almost essential for prediction and interpretation of device's performance. In gas sensing field, the simulation of specific conditions, which determine the physical-chemical properties of widely used metal oxide semiconductors, can be used to investigate the performance of gas sensors based on these kinds of materials. The aim of this work was to evaluate the physical-chemical properties of tin dioxide employed for environmental and health gas sensing application and to investigate the influence of oxygen vacancies on its properties by means of densi
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Wang, Chen, Xiuli Zhao, Hao Liu, Xin Chao, Hao Zhu, and Qingqing Sun. "A High-Density Memory Design Based on Self-Aligned Tunneling Window for Large-Capacity Memory Application." Electronics 10, no. 16 (2021): 1954. http://dx.doi.org/10.3390/electronics10161954.

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Despite the continuous downscaling of complementary metal–oxide–semiconductor (CMOS) devices, various scenarios of technology have also been proposed toward the shrinking of semiconductor memory. In this paper, a high-density memory (HDM) has been proposed on the basis of band-to-band tunneling (BTBT) for low-power, high density, and high-speed memory applications. The geometric structure and electrical properties have been demonstrated by using TCAD tools. Typical memory operations including read, program, and erase have been designed and performed. High operation speed, lower power consumpti
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Saraniti, M., G. Zandler, G. Formicone, and S. Goodnick. "Cellular Automata Studies of Vertical Silicon Devices." VLSI Design 8, no. 1-4 (1998): 111–15. http://dx.doi.org/10.1155/1998/89897.

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We present systematic theoretical Cellular Automata (CA) studies of a novel nanometer scale Si device, namely vertically grown Metal Oxide Field Effect Transistors (MOSFET) with channel lengths between 65 and 120 nm. The CA simulations predict drain characteristics and output conductance as a function of gate length. The excellent agreement with available experimental data indicates a high quality oxide/semiconductor interface. Impact ionization is shown to be of minor importance. For inhomogeneous p-doping profiles along the channel, significantly improved drain current saturation is predicte
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Tesis sobre el tema "Electrical and Computer Engineering. Metal oxide semiconductors"

1

Bonhome, Waldack. "Analysis of the lateral diffuse metal-oxide semiconductor (LDMOS) power amplifier for cellular base stations." FIU Digital Commons, 2003. http://digitalcommons.fiu.edu/etd/1727.

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The primary purpose of this thesis was to present a theoretical large-signal analysis to study the power gain and efficiency of a microwave power amplifier for LS-band communications using software simulation. Power gain, efficiency, reliability, and stability are important characteristics in the power amplifier design process. These characteristics affect advance wireless systems, which require low-cost device amplification without sacrificing system performance. Large-signal modeling and input and output matching components are used for this thesis. Motorola's Electro Thermal LDMOS model is
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2

Shen, Pin-Chun. "Large-area CVD growth of two-dimensional transition metal dichalcogenides and monolayer MoS₂ and WS₂ metal-oxide-semiconductor field-effect transistors." Thesis, Massachusetts Institute of Technology, 2017. http://hdl.handle.net/1721.1/112003.

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Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2017.<br>This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.<br>Cataloged from student-submitted PDF version of thesis.<br>Includes bibliographical references (pages 54-55).<br>Two-dimensional semiconducting materials such as MoS₂ and WS₂ have been attractive for use in ultra-scaled electronic and optoelectronic devices because of their atomically-thin thickness, direct band gap, and lack o
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3

Mahooti, Rabe'eh. "A CMOS circuit generator using differential pass transistors for implementing Boolean functions." PDXScholar, 1988. https://pdxscholar.library.pdx.edu/open_access_etds/3805.

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This study uses differential pass transistor methodology for implementing and evaluating Boolean functions. The main goal is investigation of CMOS and nMOS approaches in pass transistor logic design. Pass-transistor logic is most effective in the implementation of Boolean functions when the vectors are in the same format. It has been demonstrated that nMOS pass transistor logic driven by a control signal voltage above the V dd level offers a significant improvement in speed. nMOS pass transistorsalso offer less area consumption in comparison to the CMOS approach. The philosophy developed here
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Skaria, Giji. "Class F and inverse class F power amplifier subject to electrical stress effect." Master's thesis, University of Central Florida, 2011. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/5038.

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This study investigated the Class F and inverse Class F RF power amplifier operating at 5.8 GHz. The major challenging issue in design and implementation of CMOS power transistor is the breakdown voltage especially in sub-micron CMOS technologies. In order to eliminate this problem a Cascode topologies were implemented to reduce the Drain-to-Source voltage (stress). A Cascode Class F & Inverse Class F RF power amplifier were designed, and optimized in order to improve efficiency and reliability using 0.18micrometers] CMOS technology process. A 50% decrease in the stress has been achieved in th
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5

Jia, Joey Zong-yi. "Voltage controlled resistance model for MOS transistors." PDXScholar, 1988. https://pdxscholar.library.pdx.edu/open_access_etds/3802.

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The voltage controlled resistance model is developed for a reliable MOS transistor resistance mapping. The model includes both system and local parameters, and incorporates the effect of rise and fall time variations on the gate delay. MOS transistor resistance mapping is applied in logic simulation and timing verification. Also, it can be used in automatic transistor sizing and critical path analysis.
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Peršun, Marijan. "Scaling of the Silicon-on-Insulator Si and Si1-xGex p-MOSFETs." PDXScholar, 1995. https://pdxscholar.library.pdx.edu/open_access_etds/4934.

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Two-dimensional numerical simulation was used to study the scaling properties of SOI p-MOSFETs. Based on the design criteria for the threshold voltage and DIBL, a set of design curves for different designs was developed. Data for subthreshold slope, SCE and threshold voltage sensitivity to silicon film thickness are also given. Results show that short-channel effects can be controlled by increasing the doping level or by thinning the silicon film thickness. The first approach is more effective for p+ gate design with high body doping, while the second approach is much more effective for n+ gat
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Zhou, Sida. "Mobility Modeling and Simulation of SOI Si1-x Gex p-MOSFET." PDXScholar, 1995. https://pdxscholar.library.pdx.edu/open_access_etds/4954.

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With increasing demand for complex and faster circuits, CMOS technologies are progressing towards the deep-submicron level. Process complexity increases dramatically, and costly techniques are to be developed to create dense field isolation and shallow junctions. Silicon-On-Insulator (SOI) may solve some of these problems. On the other hand, strained Si 1_xGex layers have been successfully grown on Si substrates and demonstrated much higher hole mobility than bulk Si. This can be used to build high-mobility p-MOSFET with a buried Si 1_xGex channel. A high mobility p-MOSFET would improve both t
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8

Xiao, Haiqiao. "Design of Radio-Frequency Filters and Oscillators in Deep-Submicron CMOS Technology." PDXScholar, 2008. https://pdxscholar.library.pdx.edu/open_access_etds/5233.

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Radio-frequency filters and oscillators are widely used in wireless communication and high-speed digital systems, and they are mostly built on passive integrated inductors, which occupy a relative large silicon area. This research attempted to implement filters and oscillators operating at 1-5 GHz using transistors only, to reduce the circuits’ area. The filters and oscillators are designed using active inductors, based on the gyrator principle; they are fabricated in standard digital CMOS technology to be compatible with logic circuits and further lower the cost. To obtain the highest operati
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9

Nehl, Albert Henry. "Investigation of techniques for high speed CMOS arbitrary waveform generation." PDXScholar, 1990. https://pdxscholar.library.pdx.edu/open_access_etds/4109.

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Today a growing number of applications in design engineering, production and environmental testing, and system service require specific analog waveforms and digital patterns. Such requirements are neither satisfactorily nor easily met by the use of standard function or single purpose, custom generators. Traditional methods of waveform generation suffer from undesirable complexity or mediocre performance and are otherwise limited. For the majority of arbitrary waveform generation applications, including medical engineering, modal analysis and electronic engineering, direct digital synthesis tec
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Chan, Chi Hang. "A study on comparator and offset calibration techniques in high speed Nyquist ADCs." Thesis, University of Macau, 2011. http://umaclib3.umac.mo/record=b2493284.

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Libros sobre el tema "Electrical and Computer Engineering. Metal oxide semiconductors"

1

1948-, Liu Wentai, and Cavin Ralph K. 1939-, eds. Wave pipelining: Theory and CMOS implementation. Kluwer Academic Publishers, 1994.

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2

Power management of digital circuits in deep sub-micron CMOS technologies. Springer, 2007.

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C, Vital João, and Franca José, eds. Systematic design for optimisation of pipelined ADCs. Kluwer Academic Publishers, 2001.

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4

Bernstein, Kerry. SOI circuit design concepts. Kluwer Academic Publishers, 2000.

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5

Anis, Mohab. Multi-threshold CMOS digital circuits: Managing leakage power. Kluwer Academic Publishers, 2004.

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1943-, Elmasry Mohamed I., ed. Multi-threshold CMOS digital circuits: Managing leakage power. Kluwer Academic Publishers, 2003.

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Muer, Bram de. CMOS fractional-N synthesizers: Design for high spectral purity and monolithic integration. Kluwer Academic Publishers, 2003.

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1959-, Steyaert Michiel, ed. CMOS fractional-N synthesizers: Design for high spectral purity and monolithic integration. Kluwer Academic Publishers, 2003.

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Tuijl, Ed A. J. M. van., ed. Power trade-offs and low-power in analog CMOS ICs. Kluwer Academic Publishers, 2002.

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10

Sakurai, Satoshi. Low-voltage CMOS operational amplifiers: Theory, design, and implementation. Kluwer Academic, 1995.

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Capítulos de libros sobre el tema "Electrical and Computer Engineering. Metal oxide semiconductors"

1

Krik, Soufiane, Andrea Gaiardo, Matteo Valt, et al. "Influence of Oxygen Vacancies in Gas Sensors Based on Metal-Oxide Semiconductors: A First-Principles Study." In Lecture Notes in Electrical Engineering. Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-37558-4_47.

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Bala, Shashi, Mamta Khosla, and Raj Kumar. "CNTFET-Based Memory Design." In Advances in Computer and Electrical Engineering. IGI Global, 2020. http://dx.doi.org/10.4018/978-1-7998-1393-4.ch002.

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As the feature size of device has been scaling down for many decades, conventional CMOS technology-based static random access memory (SRAM) has reached its limit due to significant leakage power. Therefore, carbon nanotube field effect transistor (CNTFET) can be considered most suitable alternative for SRAM. In this chapter, the performance and stability of CNTFET-based SRAM cells have been analyzed. Numerous figures of merit (FOM) (e.g., read/write noise margin, power dissipation, and read/write delay) have been considered to analyze the performance of CNTFET-based. The static power consumption in CNTFET-based SRAM cell was compared with conventional complementary metal oxide semiconductor (CMOS)-based SRAM cell. Conventional CNTFET and tunnel CNTFET-based SRAMs have also been considered for comparison. From the simulation results, it is observed that tunnel CNTFET SRAM cells have shown improved FOM over conventional CNTFET 6T SRAM cells without losing stability.
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Polanco-Martagón, Said, Gerardo Reyes Salgado, Georgina Flores Becerra, and Esteban Tlelo Cuautle. "Distributed Selection of the Optimal Sizes of Analog Unity Gain Cells by Fuzzy Set Intersection." In Advances in Computer and Electrical Engineering. IGI Global, 2015. http://dx.doi.org/10.4018/978-1-4666-6627-6.ch008.

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A distributed system based on Fuzzy sets to select the optimal sizes of Unity Gain Cells (UGCs) is introduced. A zoom technique is also introduced to search for the optimal sizes in a more refined way. The selected sizes accomplish target specifications established by linguistic variables, namely gain “closer to” unity and “large” bandwidth, which are represented by fuzzy sets. The case of study is focused on three Voltage Follower and a CFOA whose performance characteristics are evaluated by using IC technology of 0.35µm and 180µm, respectively, and the circuit simulation program SPICE. Every circuit is codified by the width and large (W/L) of every Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) and by its bias current source. From the population of feasible solutions computed by evolutionary algorithms, the optimal W/L sizes are selected by the proposed distributed system through the intersection of fuzzy sets.
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Actas de conferencias sobre el tema "Electrical and Computer Engineering. Metal oxide semiconductors"

1

Zainuddin, A. N. M., and A. Haque. "Direct Tunneling Gate Current in Strained-Si/SiGe Metal-Oxide-Semiconductor Structures." In 2006 International Conference on Electrical and Computer Engineering. IEEE, 2006. http://dx.doi.org/10.1109/icece.2006.355678.

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Menkad, Tarik, D. Alexandrov, and K. S. A. Butcher. "Modeling of metal-oxide-semiconductor capacitor on Indium Gallium Nitride 1- channel model." In 2012 25th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE). IEEE, 2012. http://dx.doi.org/10.1109/ccece.2012.6334924.

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Ivanov, Denis, Ilya Marinov, Yuriy Gorbachev, Alexander Smirnov, and Valeria Krzhizhanovskaya. "Computer Simulation of Laser Annealing of a Nanostructured Surface." In ASME 2009 International Design Engineering Technical Conferences and Computers and Information in Engineering Conference. ASMEDC, 2009. http://dx.doi.org/10.1115/detc2009-87087.

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Laser annealing technology is used in mass production of new-generation semiconductor materials and nano-electronic devices like the MOS-based (metal–oxide–semiconductor) integrated circuits. Manufacturing sub-100 nm MOS devices demands application of ultra-shallow doping (junctions), which requires rapid high-temperature annealing to increase dopant electrical activation and remove implantation defects in the silicon [1].
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Yu, Shifeng, Shuyu Wang, Ming Lu, and Lei Zuo. "Semiconductor to Metal Transition Study of Oxidized Vanadium Thin Film." In ASME 2017 International Design Engineering Technical Conferences and Computers and Information in Engineering Conference. American Society of Mechanical Engineers, 2017. http://dx.doi.org/10.1115/detc2017-67926.

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Since vanadium atom has a half-filled d-shell, there exist a set of valence states to form a number of oxide phases. In this paper, the deposited vanadium thin film is oxidized under different conditions. The electrical characterization shows some oxides of vanadium undergo a transition from semiconductor state to a metal phase at a critical temperature. Such vanadium oxides have potential use, particularly in thin film form, for a wide variety of applications involving thermally activated electronic switching devices. The surface morphology is studied under SEM. The temperature coefficient of
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Osseily, Hassan Amine, and Ali Massoud Haidar. "Hexadecimal to binary conversion using multi-input floating gate complementary metal oxide semiconductors." In 2015 International Conference on Applied Research in Computer Science and Engineering (ICAR). IEEE, 2015. http://dx.doi.org/10.1109/arcse.2015.7338134.

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Ghosh, Arnob, Shahriyar Safat, and Md Shafiqul Islam. "Stable and Efficient Perovskite Solar Cell with Metal Oxide Transport Layers." In 2019 International Conference on Electrical, Computer and Communication Engineering (ECCE). IEEE, 2019. http://dx.doi.org/10.1109/ecace.2019.8679418.

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Dibelka, Jessica, Mark Steimer, Julianna Twomey, et al. "Design of a Heat Removal Method for the Electronics in Lithium-Ion Cordless Power Tools." In ASME 2008 International Design Engineering Technical Conferences and Computers and Information in Engineering Conference. ASMEDC, 2008. http://dx.doi.org/10.1115/detc2008-49930.

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Cordless power drills are currently being designed with lithium-ion battery technology to produce more power per unit mass as compared to legacy nickel-cadmium battery packs. With this increase in power, more complex heat removal solutions are needed to dissipate heat resulting from electrical circuit resistance and insure electronic components, specifically the metal oxide semiconductor field effect transistor (MOSFET), will remain below its maximum operating temperature of 175°C. Heat spreaders, ventilation methods, and heat sinks were considered, with a newly designed heat sink being determ
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Rahman, Md Sazzadur, Suman Miah, Ma Sing Wang Marma, and Tishna Sabrina. "Simulation based Investigation of Inverted Planar Perovskite Solar Cell with All Metal Oxide Inorganic Transport Layers." In 2019 International Conference on Electrical, Computer and Communication Engineering (ECCE). IEEE, 2019. http://dx.doi.org/10.1109/ecace.2019.8679283.

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Dutta, Tonushree, Md Tawsif Rahman Chowdhury, and Anowarul Azim. "Enhancement in Optical and Electrical Properties of Si and GaAs Solar Cells Using Metal-oxide Anti-reflective Coatings." In 2021 International Conference on Electrical, Communication, and Computer Engineering (ICECCE). IEEE, 2021. http://dx.doi.org/10.1109/icecce52056.2021.9514100.

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Srisukkhom, Chaleamchon, and Peerapol Jirapong. "Analysis of electrical and thermal characteristics of gapless metal oxide arresters using thermal images." In 2011 8th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON 2011). IEEE, 2011. http://dx.doi.org/10.1109/ecticon.2011.5947930.

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