Bibliografías temáticas / Hardware Security

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Literatura académica sobre el tema "Hardware Security"

Autor: Grafiati
Publicado: 4 de junio de 2021
Última modificación: 25 de mayo de 2024

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Artículos de revistas sobre el tema "Hardware Security"

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Polian, Ilia. "Hardware-oriented security". it - Information Technology 61, n.º 1 (25 de febrero de 2019): 1–2. http://dx.doi.org/10.1515/itit-2019-0008.

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Hunter, Philip. "Hardware-based security". Computer Fraud & Security 2004, n.º 2 (febrero de 2004): 11–12. http://dx.doi.org/10.1016/s1361-3723(04)00029-6.

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Sengupta, Anirban. "Hardware Security of CE Devices [Hardware Matters]". IEEE Consumer Electronics Magazine 6, n.º 1 (enero de 2017): 130–33. http://dx.doi.org/10.1109/mce.2016.2614552.

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Jin, Yier. "Introduction to Hardware Security". Electronics 4, n.º 4 (13 de octubre de 2015): 763–84. http://dx.doi.org/10.3390/electronics4040763.

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Koushanfar, Farinaz y Miodrag Potkonjak. "What is hardware security?" ACM SIGDA Newsletter 40, n.º 9 (septiembre de 2010): 1. http://dx.doi.org/10.1145/1866978.1866979.

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Fox, Dirk. "Hardware Security Module (HSM)". Datenschutz und Datensicherheit - DuD 33, n.º 9 (septiembre de 2009): 564. http://dx.doi.org/10.1007/s11623-009-0145-9.

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Guin, Ujjwal, Navid Asadizanjani y Mark Tehranipoor. "Standards for Hardware Security". GetMobile: Mobile Computing and Communications 23, n.º 1 (24 de julio de 2019): 5–9. http://dx.doi.org/10.1145/3351422.3351424.

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Sidhu, Simranjeet, Bassam J. Mohd y Thaier Hayajneh. "Hardware Security in IoT Devices with Emphasis on Hardware Trojans". Journal of Sensor and Actuator Networks 8, n.º 3 (10 de agosto de 2019): 42. http://dx.doi.org/10.3390/jsan8030042.

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Security of IoT devices is getting a lot of attention from researchers as they are becoming prevalent everywhere. However, implementation of hardware security in these devices has been overlooked, and many researches have mainly focused on software, network, and cloud security. A deeper understanding of hardware Trojans (HTs) and protection against them is of utmost importance right now as they are the prime threat to the hardware. This paper emphasizes the need for a secure hardware-level foundation for security of these devices, as depending on software security alone is not adequate enough. These devices must be protected against sophisticated attacks, especially if the groundwork for the attacks is already laid in devices during design or manufacturing process, such as with HTs. This paper will discuss the stealthy nature of these HT, highlight HT taxonomy and insertion methods, and provide countermeasures.
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Adlkofer, Hans. "Safety and Security Need Hardware". ATZelectronics worldwide 16, n.º 10 (octubre de 2021): 66. http://dx.doi.org/10.1007/s38314-021-0699-3.

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D.S, Suresh y V. Udayashankara. "External Hardware Security for Steganography". i-manager's Journal on Future Engineering and Technology 2, n.º 2 (15 de enero de 2007): 17–22. http://dx.doi.org/10.26634/jfet.2.2.874.

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Tesis sobre el tema "Hardware Security"

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Kalibjian, Jeff. "Securing Telemetry Post Processing Applications with Hardware Based Security". International Foundation for Telemetering, 2004. http://hdl.handle.net/10150/605052.

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International Telemetering Conference Proceedings / October 18-21, 2004 / Town & Country Resort, San Diego, California
The use of hardware security for telemetry in satellites utilized for intelligence and defense applications is well known. Less common is the use of hardware security in ground-based computers hosting applications that post process telemetry data. Analysis reveals vulnerabilities in software only security solutions that can result in the compromise of telemetry data housed on ground-based computer systems. Such systems maybe made less susceptible to compromise with the use of hardware based security.
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Chakraborty, Rajat Subhra. "Hardware Security through Design Obfuscation". Cleveland, Ohio : Case Western Reserve University, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=case1270133481.

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Thesis (Doctor of Philosophy)--Case Western Reserve University, 2010
Department of EECS - Computer Engineering Title from PDF (viewed on 2010-05-25) Includes abstract Includes bibliographical references and appendices Available online via the OhioLINK ETD Center
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Tselekounis, Ioannis. "Cryptographic techniques for hardware security". Thesis, University of Edinburgh, 2018. http://hdl.handle.net/1842/33148.

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Traditionally, cryptographic algorithms are designed under the so-called black-box model, which considers adversaries that receive black-box access to the hardware implementation. Although a "black-box" treatment covers a wide range of attacks, it fails to capture reality adequately, as real-world adversaries can exploit physical properties of the implementation, mounting attacks that enable unexpected, non-black-box access, to the components of the cryptographic system. This type of attacks is widely known as physical attacks, and has proven to be a significant threat to the real-world security of cryptographic systems. The present dissertation is (partially) dealing with the problem of protecting cryptographic memory against physical attacks, via the use of non-malleable codes, which is a notion introduced in a preceding work, aiming to provide privacy of the encoded data, in the presence of adversarial faults. In the present thesis we improve the current state-of-the-art on non-malleable codes and we provide practical solutions for protecting real-world cryptographic implementations against physical attacks. Our study is primarily focusing on the following adversarial models: (i) the extensively studied split-state model, which assumes that private memory splits into two parts, and the adversary tampers with each part, independently, and (ii) the model of partial functions, which is introduced by the current thesis, and models adversaries that access arbitrary subsets of codeword locations, with bounded cardinality. Our study is comprehensive, covering one-time and continuous, attacks, while for the case of partial functions, we manage to achieve a stronger notion of security, that we call non-malleability with manipulation detection, that in addition to privacy, it also guarantees integrity of the private data. It should be noted that, our techniques are also useful for the problem of establishing, private, keyless communication, over adversarial communication channels. Besides physical attacks, another important concern related to cryptographic hardware security, is that the hardware fabrication process is assumed to be trusted. In reality though, when aiming to minimize the production costs, or whenever access to leading-edge manufacturing facilities is required, the fabrication process requires the involvement of several, potentially malicious, facilities. Consequently, cryptographic hardware is susceptible to the so-called hardware Trojans, which are hardware components that are maliciously implanted to the original circuitry, having as a purpose to alter the device's functionality, while remaining undetected. Part of the present dissertation, deals with the problem of protecting cryptographic hardware against Trojan injection attacks, by (i) proposing a formal model for assessing the security of cryptographic hardware, whose production has been partially outsourced to a set of untrusted, and possibly malicious, manufacturers, and (ii) by proposing a compiler that transforms any cryptographic circuit, into another, that can be securely outsourced.
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Edmison, Joshua Nathaniel. "Hardware Architectures for Software Security". Diss., Virginia Tech, 2006. http://hdl.handle.net/10919/29244.

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The need for hardware-based software protection stems primarily from the increasing value of software coupled with the inability to trust software that utilizes or manages shared resources. By correctly utilizing security functions in hardware, trust can be removed from software. Existing hardware-based software protection solutions generally suffer from utilization of trusted software, lack of implementation, and/or extreme measures such as processor redesign. In contrast, the research outlined in this document proposes that substantial, hardware-based software protection can be achieved, without trusting software or redesigning the processor, by augmenting existing processors with security management hardware placed outside of the processor boundary. Benefits of this approach include the ability to add security features to nearly any processor, update security features without redesigning the processor, and provide maximum transparency to the software development and distribution processes. The major contributions of this research include the the augmentation methodology, design principles, and a graph-based method for analyzing hardware-based security systems.
Ph. D.
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Leonhard, Julian. "Analog hardware security and trust". Electronic Thesis or Diss., Sorbonne université, 2021. http://www.theses.fr/2021SORUS246.

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La mondialisation et la spécialisation de la chaîne d'approvisionnement des circuits intégrés (CI) ont conduit les entreprises de semi-conducteurs à partager leur précieuse propriété intellectuelle (PI) avec de nombreuses parties pour les faire fabriquer, tester, etc. En conséquence, les PI et les CI sensibles sont exposés à des parties potentiellement malveillantes, ce qui entraîne de graves menaces de piratage telles que la contrefaçon ou la retro ingénierie. Dans cette thèse, nous développons des méthodes pour sécuriser les IP/CI analogiques et mixtes contre les menaces de piratage dans la chaîne d'approvisionnement. Nous proposons une méthodologie anti-piratage pour verrouiller les circuits intégrés mixtes via l'application de logic locking à leur partie numérique. En outre, nous proposons une méthodologie contre la rétro ingénierie camouflant la géométrie effective des composants de layout. Enfin, nous proposons une attaque pour contourner toutes les techniques de verrouillage des circuits analogiques qui agissent sur la polarisation du circuit. Les techniques présentées ont le potentiel de protéger les circuits analogiques et mixtes contre une grande partie de tous les scénarios de risque possibles tout en infligeant de faibles coûts en termes de surface, de puissance et de performance
The ongoing globalization and specialization of the integrated circuit (IC) supply chain has led semiconductor companies to share their valuable intellectual property (IP) assets with numerous parties for means of manufacturing, testing, etc. As a consequence, sensitive IPs and ICs are being exposed to untrusted parties, resulting in serious piracy threats such as counterfeiting or reverse engineering. In this thesis we develop methods to secure analog and mixed signal IPs/ICs from piracy threats within the supply chain. We propose an anti-piracy methodology for locking mixed-signal ICs via logic locking of their digital part. Furthermore, we propose an anti-reverse engineering methodology camouflaging the effective geometry of layout components. Finally, we propose an attack to break all analog circuit locking techniques that act upon the biasing of the circuit. The presented techniques have the potential to protect analog and mixed-signal circuits against a large subset of all the possible risk scenarios while inflicting low overheads in terms of area, power and performance
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Bilzor, Michael B. "Defining and enforcing hardware security requirements". Monterey, California. Naval Postgraduate School, 2011. http://hdl.handle.net/10945/10741.

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Security in computing systems to date has focused mostly on software. In this research, we explore the application and enforceability of well-defined security requirements in hardware designs. The principal threats to hardware systems demonstrated in the academic literature to date involve some type of subversion, often called a Hardware Trojan or malicious inclusion. Detecting these has proved very difficult. We demonstrate a method whereby the dynamic enforcement of a processor's security requirements can be used to detect the presence of some of these malicious inclusions. Although there are theoretical limits on which security properties can be dynamically enforced using the techniques we describe, our research does provide a novel method for expressing and enforcing security requirements at runtime in hardware designs. While the method does not guarantee the detection of all possible malicious inclusions in a given processor, it addresses a large class of inclusions-those detectable as violations of behavioral restrictions in the architectural specification-which provides significant progress against the general case, given a suitably complete set of checkers.
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Sekar, Sanjana. "Logic Encryption Methods for Hardware Security". University of Cincinnati / OhioLINK, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1505124923353686.

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Xue, Hao. "Hardware Security and VLSI Design Optimization". Wright State University / OhioLINK, 2018. http://rave.ohiolink.edu/etdc/view?acc_num=wright1546466777397815.

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Valea, Emanuele. "Security Techniques for Test Infrastructures". Thesis, Montpellier, 2020. http://www.theses.fr/2020MONTS042.

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Les infrastructures de test sont essentielles pour l'industrie moderne des circuits intégrés. La nécessité de détecter les défauts de fabrication et de prévenir les défaillances des systèmes sur le terrain, rend leur présence inévitable dans chaque circuit intégré et ses sous-modules. Malheureusement, les infrastructures de test représentent également une menace pour la sécurité en raison de la contrôlabilité et de l'observabilité accrues qu'elles offrent généralement sur les circuits internes. Dans cette thèse, nous présentons une analyse complète des menaces existantes et des contre-mesures respectives, en fournissant également une classification et une taxonomie de l'état de l'art. En outre, nous proposons de nouvelles solutions de sécurité, basées sur la cryptographie légère, pour la conception d'infrastructures de test. Toutes les contre-mesures proposées appartiennent à la catégorie des solutions dit de scan encryption et leur but est de garantir la confidentialité des données et l'authentification des utilisateurs. Chaque solution proposée est évaluée en termes de coûts de mise en œuvre et de capacités de sécurité. Les travaux qui ont été réalisés et qui sont présentés dans cette thèse, indiquent que la scan encryption est une solution prometteuse pour garantir une conception sécurisée des infrastructures de test
Test infrastructures are crucial to the modern Integrated Circuits (ICs) industry. The necessity of detecting manufacturing defects and preventing system failures in the field, makes their presence inevitable in every IC and its sub-modules. Unfortunately, test infrastructures also represent a security threat due to the augmented controllability and observability on the IC internals that they typically provide. In this thesis, we present a comprehensive analysis of the existing threats and the respective countermeasures, also providing a classification and a taxonomy of the state-of-the-art. Furthermore, we propose new security solutions, based on lightweight cryptography, for the design of test infrastructures. All proposed countermeasures belong to the category of scan encryption solutions and their purpose is to guarantee data confidentiality and user authentication. Each proposed solution is evaluated in terms of implementation costs and security capabilities. The works that have been carried out and are presented in this thesis, indicate that scan encryption is a promising solution for granting a secure design of test infrastructures
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Wenhua, Qi, Zhang Qishan y Liu Hailong. "RESEARCH OF SECURITY HARDWARE IN PKI SYSTEM". International Foundation for Telemetering, 2003. http://hdl.handle.net/10150/606688.

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International Telemetering Conference Proceedings / October 20-23, 2003 / Riviera Hotel and Convention Center, Las Vegas, Nevada
Security hardware based on asymmetric algorithm is the key component of Public Key Infrastructure (PKI), which decides the safety and performance of system. Security device in server or client have some common functions. We designed the client token and cryptographic server to improve the performance of PKI, and got obvious effect.
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Libros sobre el tema "Hardware Security"

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Tehranipoor, Mark, Nitin Pundir, Nidish Vashistha y Farimah Farahmandi. Hardware Security Primitives. Cham: Springer International Publishing, 2023. http://dx.doi.org/10.1007/978-3-031-19185-5.

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Sadeghi, Ahmad-Reza y David Naccache, eds. Towards Hardware-Intrinsic Security. Berlin, Heidelberg: Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-14452-3.

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Sklavos, Nicolas, Ricardo Chaves, Giorgio Di Natale y Francesco Regazzoni, eds. Hardware Security and Trust. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-44318-8.

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Halak, Basel, ed. Hardware Supply Chain Security. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-62707-2.

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Farahmandi, Farimah, M. Sazadur Rahman, Sree Ranjani Rajendran y Mark Tehranipoor. CAD for Hardware Security. Cham: Springer International Publishing, 2023. http://dx.doi.org/10.1007/978-3-031-26896-0.

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Tehranipoor, Mark, ed. Emerging Topics in Hardware Security. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-64448-2.

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Katkoori, Srinivas y Sheikh Ariful Islam, eds. Behavioral Synthesis for Hardware Security. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-030-78841-4.

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Mishra, Prabhat, Swarup Bhunia y Mark Tehranipoor, eds. Hardware IP Security and Trust. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-49025-0.

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Tehranipoor, Mark, N. Nalla Anandakumar y Farimah Farahmandi. Hardware Security Training, Hands-on! Cham: Springer International Publishing, 2023. http://dx.doi.org/10.1007/978-3-031-31034-8.

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Kelly, Wayne. Security hardware and security system planning for museums. Ottawa, Ont: Canadian Conservation Institute, 1998.

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Capítulos de libros sobre el tema "Hardware Security"

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Tehranipoor, Mark, Nitin Pundir, Nidish Vashistha y Farimah Farahmandi. "Analog Security". En Hardware Security Primitives, 245–60. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-031-19185-5_14.

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Sommerhalder, Maria. "Hardware Security Module". En Trends in Data Protection and Encryption Technologies, 83–87. Cham: Springer Nature Switzerland, 2023. http://dx.doi.org/10.1007/978-3-031-33386-6_16.

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AbstractHardware security modules are specialized devices that perform cryptographic operations. Their functions include key generation, key management, encryption, decryption, and hashing. The advent of cloud computing has increased the complexity of securing critical data. As a result, double-key encryption has become increasingly popular, which encrypts data using two keys. A copy is stored on an HSM, and a copy is stored in the cloud. Furthermore, as Hardware security modules can manage keys and enable users to manage keys, they provide significant security benefits to applications utilizing cryptography.
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Huffmire, Ted, Cynthia Irvine, Thuy D. Nguyen, Timothy Levin, Ryan Kastner y Timothy Sherwood. "Hardware Security Challenges". En Handbook of FPGA Design Security, 71–85. Dordrecht: Springer Netherlands, 2010. http://dx.doi.org/10.1007/978-90-481-9157-4_3.

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Mavrovouniotis, Stathis y Mick Ganley. "Hardware Security Modules". En Secure Smart Embedded Devices, Platforms and Applications, 383–405. New York, NY: Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4614-7915-4_17.

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Tuyls, Pim. "Hardware Intrinsic Security". En Radio Frequency Identification: Security and Privacy Issues, 123. Berlin, Heidelberg: Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-16822-2_11.

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Sustek, Laurent. "Hardware Security Module". En Encyclopedia of Cryptography and Security, 535–38. Boston, MA: Springer US, 2011. http://dx.doi.org/10.1007/978-1-4419-5906-5_509.

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Bertino, Elisa, Sonam Bhardwaj, Fabrizio Cicala, Sishuai Gong, Imtiaz Karim, Charalampos Katsis, Hyunwoo Lee, Adrian Shuai Li y Ashraf Y. Mahgoub. "Hardware Security Analysis". En Synthesis Lectures on Information Security, Privacy, and Trust, 71–77. Cham: Springer International Publishing, 2023. http://dx.doi.org/10.1007/978-3-031-28259-1_5.

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Döttling, Nico, Daniel Kraschewski, Jörn Müller-Quade y Tobias Nilges. "From Stateful Hardware to Resettable Hardware Using Symmetric Assumptions". En Provable Security, 23–42. Cham: Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-26059-4_2.

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Tehranipoor, Mark, Nitin Pundir, Nidish Vashistha y Farimah Farahmandi. "Intrinsic Racetrack PUF". En Hardware Security Primitives, 1–16. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-031-19185-5_1.

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Tehranipoor, Mark, Nitin Pundir, Nidish Vashistha y Farimah Farahmandi. "Fault Injection Resistant Cryptographic Hardware". En Hardware Security Primitives, 333–46. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-031-19185-5_19.

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Actas de conferencias sobre el tema "Hardware Security"

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Sadeghi, Ahmad-Reza. "Hardware-Assisted Security". En CCS '17: 2017 ACM SIGSAC Conference on Computer and Communications Security. New York, NY, USA: ACM, 2017. http://dx.doi.org/10.1145/3139324.3139326.

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Leef, Serge. "Hardware cyber security". En the 2014. New York, New York, USA: ACM Press, 2014. http://dx.doi.org/10.1145/2560519.2565868.

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Chandra, Vikas y Rob Aitken. "Mobile hardware security". En 2014 IEEE Hot Chips 26 Symposium (HCS). IEEE, 2014. http://dx.doi.org/10.1109/hotchips.2014.7478796.

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Lee, Ruby, Simha Sethumadhavan y G. Edward Suh. "Hardware enhanced security". En the 2012 ACM conference. New York, New York, USA: ACM Press, 2012. http://dx.doi.org/10.1145/2382196.2382323.

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Burleson, Wayne y Yusuf Leblebici. "Hardware security in VLSI". En the 21st edition of the great lakes symposium. New York, New York, USA: ACM Press, 2011. http://dx.doi.org/10.1145/1973009.1973109.

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Tsvetanov, Filip. "Sensor network hardware security". En THE 9TH INTERNATIONAL CONFERENCE OF THE INDONESIAN CHEMICAL SOCIETY ICICS 2021: Toward a Meaningful Society. AIP Publishing, 2022. http://dx.doi.org/10.1063/5.0099518.

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Gu, Jie y Carlos Tokunaga. "Session details: Hardware Security". En ISLPED '16: International Symposium on Low Power Electronics and Design. New York, NY, USA: ACM, 2016. http://dx.doi.org/10.1145/3256017.

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Chan, Philip, Thomas Barnett, Abdel-Hameed Badawy y Patrick W. Jungwirth. "Cyber defense through hardware security". En Disruptive Technologies in Information Sciences, editado por Misty Blowers, Russell D. Hall y Venkateswara R. Dasari. SPIE, 2018. http://dx.doi.org/10.1117/12.2302805.

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"2.2 Special session: Hardware security". En 2014 International Conference on Field-Programmable Technology (FPT). IEEE, 2014. http://dx.doi.org/10.1109/fpt.2014.7082767.

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Lo, Dan Chia-Tien, Kai Qian y Wei Chen. "Hardware Attacks and Security Education". En 2016 IEEE 40th Annual Computer Software and Applications Conference (COMPSAC). IEEE, 2016. http://dx.doi.org/10.1109/compsac.2016.128.

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Informes sobre el tema "Hardware Security"

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Souppaya, Murugiah. Hardware-Enabled Security:. Gaithersburg, MD: National Institute of Standards and Technology, 2022. http://dx.doi.org/10.6028/nist.ir.8320b.

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Souppaya, Murugiah. Hardware-Enabled Security:. Gaithersburg, MD: National Institute of Standards and Technology, 2022. http://dx.doi.org/10.6028/nist.ir.8320.

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Bartock, Michael. Hardware Enabled Security:. Gaithersburg, MD: National Institute of Standards and Technology, 2022. http://dx.doi.org/10.6028/nist.ir.8320c.ipd.

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Bartock, Michael. Hardware Enabled Security:. Gaithersburg, MD: National Institute of Standards and Technology, 2023. http://dx.doi.org/10.6028/nist.ir.8320d.ipd.

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Bartock, Michael. Hardware Enabled Security:. Gaithersburg, MD: National Institute of Standards and Technology, 2024. http://dx.doi.org/10.6028/nist.ir.8320d.

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Mell, Peter. Hardware Security Failure Scenarios:. Gaithersburg, MD: National Institute of Standards and Technology, 2024. http://dx.doi.org/10.6028/nist.ir.8517.ipd.

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Bartock, Michael, Murugiah Souppaya, Jerry Wheeler, Tim Knoll, Uttam Shetty, Ryan Savino, Joseprabu Inbaraj, Stefano Righi y Karen Scarfone. Hardware-Enabled Security: Container Platform Security Prototype. National Institute of Standards and Technology, junio de 2021. http://dx.doi.org/10.6028/nist.ir.8320a.

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Nguyen, Thuy D., Timothy E. Levin, Cynthia E. Irvin, Terry V. Benzel y Ganesha Bhaskara. Preliminary Security Requirements for SecureCore Hardware. Fort Belvoir, VA: Defense Technical Information Center, septiembre de 2006. http://dx.doi.org/10.21236/ada457517.

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Kastner, Ryan y Ted Huffmire. Threats and Challenges in Reconfigurable Hardware Security. Fort Belvoir, VA: Defense Technical Information Center, julio de 2008. http://dx.doi.org/10.21236/ada511928.

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Rushby, John. Formally Verified Hardware Encapsulation Mechanism for Security, Integrity, and Safety. Fort Belvoir, VA: Defense Technical Information Center, abril de 2002. http://dx.doi.org/10.21236/ada403303.

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