Bibliografías temáticas / Protection ESD

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Literatura académica sobre el tema "Protection ESD"

Autor: Grafiati
Publicado: 4 de junio de 2021
Última modificación: 4 de mayo de 2024

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Artículos de revistas sobre el tema "Protection ESD"

1

Mohan, N. y A. Kumar. "Modeling ESD protection". IEEE Potentials 24, n.º 1 (febrero de 2005): 21–24. http://dx.doi.org/10.1109/mp.2005.1405797.

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Lee, J. H., S. C. Huang, Y. H. Wu y K. H. Chen. "1 fF ESD protection device for gigahertz high-frequency output ESD protection". Electronics Letters 47, n.º 18 (2011): 1021. http://dx.doi.org/10.1049/el.2011.1904.

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Li, Cheng, Zijin Pan, Weiquan Hao, Xunyu Li, Runyu Miao y Albert Wang. "Graphene-Based ESD Protection for Future ICs". Nanomaterials 13, n.º 8 (20 de abril de 2023): 1426. http://dx.doi.org/10.3390/nano13081426.

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On-chip electrostatic discharge (ESD) protection is required for all integrated circuits (ICs). Conventional on-chip ESD protection relies on in-Si PN junction-based device structures for ESD. However, such in-Si PN-based ESD protection solutions pose significant challenges related to ESD protection design overhead, including parasitic capacitance, leakage current, and noises, as well as large chip area consumption and difficulty in IC layout floor planning. The design overhead effects of ESD protection devices are becoming unacceptable to modern ICs as IC technologies continuously advance, which is an emerging design-for-reliability challenge for advanced ICs. In this paper, we review the concept development of disruptive graphene-based on-chip ESD protection comprising a novel graphene nanoelectromechanical system (gNEMS) ESD switch and graphene ESD interconnects. This review discusses the simulation, design, and measurements of the gNEMS ESD protection structures and graphene ESD protection interconnects. The review aims to inspire non-traditional thinking for future on-chip ESD protection.
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Li, Hongyu, Victor Khilkevich, Tianqi Li, David Pommerenke, Seongtae Kwon y Wesley Hackenberger. "Nonlinear capacitors for ESD protection". IEEE Electromagnetic Compatibility Magazine 1, n.º 4 (2012): 38–46. http://dx.doi.org/10.1109/memc.2012.6397056.

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Lin, Lin, Lijie Zhang, Xin Wang, Jian Liu, Hui Zhao, He Tang, Qiang Fang et al. "Novel Nanophase-Switching ESD Protection". IEEE Electron Device Letters 32, n.º 3 (marzo de 2011): 378–80. http://dx.doi.org/10.1109/led.2010.2099100.

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Chen, Shen Li, Min Hua Lee y Tzung Shian Wu. "Source-End Layout Influences on MOSFET ESD Protection Devices in a 0.35um 5V Process". Advanced Materials Research 694-697 (mayo de 2013): 1454–58. http://dx.doi.org/10.4028/www.scientific.net/amr.694-697.1454.

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An nMOS transistor in input/output pad as the ESD protection element is usually in the form of multi-finger layout. This paper will show simple but effective ways to improve an nMOSFET’s ESD robustness or LU immunity for use in I/O pads, i.e., the source-end layout influences on the protection components in ESD/LU capabilities of the input/output pads will be investigated. In other words, they are used to increase the effective ESD or LU capability of the ESD protection elements. Here, the different source-end layout types will be carried out the important snapback parameters. We focus on exploring the secondary breakdown current (It2) and holding voltage (Vh) for the ESD discharge capability and the latch-up immunity, hopefully, it does effectively enhance ESD/LU robustness.
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7

Soldner, W., M. Streibl, U. Hodel, M. Tiebout, H. Gossner, D. Schmitt-Landsiedel, J. H. Chun, C. Ito y R. W. Dutton. "RF ESD protection strategies: Codesign vs. low-C protection". Microelectronics Reliability 47, n.º 7 (julio de 2007): 1008–15. http://dx.doi.org/10.1016/j.microrel.2006.11.007.

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Pan, Zijin, Xunyu Li, Weiquan Hao, Runyu Miao y Albert Wang. "On-chip ESD Protection Design Methodologies by CAD Simulation". ACM Transactions on Design Automation of Electronic Systems 29, n.º 1 (15 de noviembre de 2023): 1–41. http://dx.doi.org/10.1145/3593808.

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Electrostatic discharge (ESD) can cause malfunction or failure of integrated circuits (ICs) . On-chip ESD protection design is a major IC design-for-reliability (DfR) challenge, particularly for complex chips made in advanced technology nodes. Traditional trial-and-error approaches become unacceptable to practical ESD protection designs for advanced ICs. Full-chip ESD protection circuit design optimization, prediction, and verification become essential to advanced chip designs, which highly depends on CAD algorithm and simulation that has been a constant research topic for decades. This paper reviews recent advances in CAD-enabled on-chip ESD protection circuit simulation design technologies and ESD-IC co-design methodologies. Key challenges of ESD CAD design practices are outlined. Practical ESD protection simulation design examples are discussed.
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9

Kwon, Sang-Wook, Seung-Gu Jeong, Jeong-Min Lee y Yong-Seo Koo. "Design of Destruction Protection and Sustainability Low-Dropout Regulator Using an Electrostatic Discharge Protection Circuit". Sustainability 15, n.º 13 (26 de junio de 2023): 10126. http://dx.doi.org/10.3390/su151310126.

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In terms of sustainable power semiconductors, the embedding of an electrostatic discharge (ESD) protection circuit in an integrated circuit (IC) is an important aspect. In order for the semiconductor circuit to operate continuously or stably, a sufficient protection circuit against external surges must be configured. The purpose of this thesis is not only to effectively operate the low-dropout (LDO) regulator according to the load current, but to also secure high reliability against ESD situations by embedding an ESD protection circuit at the IC level. Moreover, the existence and nonexistence of an ESD protection circuit at the IC level is directly related to reliability. The proposed LDO regulator has high reliability against ESD situations using an embedded silicon controlled rectifier (SCR)-based ESD protection circuit in the I/O clamp and power clamp. The results revealed that the LDO regulator can not only effectively control the output voltage according to the load current, but it can also stably maintain the output voltage against the ESD surge. Moreover, the proposed LDO regulator with an embedded ESD protection circuit implemented in a 0.13 μm BCD process maintained an undershoot voltage of 21 mV and overshoot voltage of 19 mV for a load current of 300 mA.
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10

Chang, Chun-Rong, Zih-Jyun Dai y Chun-Yu Lin. "π-Shape ESD Protection Design for Multi-Gbps High-Speed Circuits in CMOS Technology". Materials 16, n.º 7 (23 de marzo de 2023): 2562. http://dx.doi.org/10.3390/ma16072562.

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CMOS integrated circuits are vulnerable to electrostatic discharge (ESD); therefore, ESD protection circuits are needed. On-chip ESD protection is important for both component-level and system-level ESD protection. In this work, on-chip ESD protection circuits for multi-Gbps high-speed applications are studied. π-shaped ESD protection circuit structures realized by staked diodes with an embedded silicon-controlled rectifier (SCR) and resistor-triggered SCR are proposed. These test circuits are fabricated in CMOS technology, and the proposed designs have been proven to have better ESD robustness and performance in high-speed applications.
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Tesis sobre el tema "Protection ESD"

1

Glaser, Ulrich. "Complex ESD protection elements and issues in decananometre CMOS technologies /". Zürich : ETH, 2007. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=16960.

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Pan, Zhihao [Verfasser]. "Modeling and optimization of discrete ESD protection devices / Zhihao Pan". München : Verlag Dr. Hut, 2015. http://d-nb.info/1074063724/34.

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Cao, Yiqun [Verfasser], Stephan [Akademischer Betreuer] Frei y Bernd [Gutachter] Deutschmann. "High-voltage ESD structures and ESD protection concepts in smart power technologies / Yiqun Cao ; Gutachter: Bernd Deutschmann ; Betreuer: Stephan Frei". Dortmund : Universitätsbibliothek Dortmund, 2019. http://d-nb.info/1200209605/34.

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4

Cui, Qiang. "On-Chip Electro-Static Discharge (ESD) Protection for Radio-Frequency Integrated Circuits". Doctoral diss., University of Central Florida, 2013. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/5620.

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Electrostatic Discharge (ESD) phenomenon is a common phenomenon in daily life and it could damage the integrated circuit throughout the whole cycle of product from the manufacturing. Several ESD stress models and test methods have been used to reproduce ESD events and characterize ESD protection device's performance. The basic ESD stress models are: Human Body Model (HBM), Machine Model (MM), and Charged Device Model (CDM). On-chip ESD protection devices are widely used to discharge ESD current and limit the overstress voltage under different ESD events. Some effective ESD protection devices were reported for low speed circuit applications such as analog ICs or digital ICs in CMOS process. On the contrast, only a few ESD protection devices available for radio frequency integrated circuits (RF ICs). ESD protection for RF ICs is more challenging than traditional low speed CMOS ESD protection design because of the facts that: (1) Process limitation: High-performance RF ICs are typically fabricated in compound semiconductor process such as GaAs pHEMT and SiGe HBT process. And some proved effective ESD devices (e.g. SCR) are not able to be fabricated in those processes due to process limitation. Moreover, compound semiconductor process has lower thermal conductivity which will worsen its ESD damage immunity. (2) Parasitic capacitance limitation: Even for RF CMOS process, the inherent parasitic capacitance of ESD protection devices is a big concern. Therefore, this dissertation will contribute on ESD protection designs for RF ICs in all the major processes including GaAs pHEMT, SiGe BiCMOS and standard CMOS. The ESD protection for RF ICs in GaAs pHEMT process is very difficult, and the typical HBM protection level is below 1-kV HBM level. The first part of our work is to analyze pHEMT's snapback, post-snapback saturation and thermal failure under ESD stress using TLP-like Sentaurus TCAD simulation. The snapback is caused by virtual bipolar transistor due to large electron-hole pairs impacted near drain region. Post-snapback saturation is caused by temperature-induced mobility degradation due to III-V compound semiconductor materials' poor thermal conductivity. And thermal failure is found to be caused by hot spot located in pHEMT's InGaAs layer. Understanding of these physical mechanisms is critical to design effective ESD protection device in GaAs pHEMT process. Several novel ESD protection devices were designed in 0.5um GaAs pHEMT process. The multi-gate pHEMT based ESD protection devices in both enhancement-mode and depletion-mode were reported and characterized then. Due to the multiple current paths available in the multi-gate pHEMT, the new ESD protection clamp showed significantly improved ESD performances over the conventional single-gate pHEMT ESD clamp, including higher current discharge capability, lower on-state resistance, and smaller voltage transient. We proposed another further enhanced ESD protection clamp based on a novel drain-less, multi-gate pHEMT in a 0.5um GaAs pHEMT technology. Based on Barth 4002 TLP measurement results, the ESD protection devices proposed in this chapter can improve the ESD level from 1-kV (0.6 A It2) to up to 8-kV (> 5.2 A It2) under HBM. Then we optimized SiGe-based silicon controlled rectifiers (SiGe SCR) in SiGe BiCMOS process. SiGe SCR is considered a good candidate ESD protection device in this process. But the possible slow turn-on issue under CDM ESD events is the major concern. In order to optimize the turn-on performance of SiGe SCR against CDM ESD, the Barth 4012 very fast TLP (vfTLP) and vfTLP-like TCAD simulation were used for characterization and analysis. It was demonstrated that a SiGe SCR implemented with a P PLUG layer and minimal PNP base width can supply the smallest peak voltage and fastest response time which is resulted from the fact that the impact ionization region and effective base width in the SiGe SCR were reduced due to the presence of the P PLUG layer. This work demonstrated a practical approach for designing optimum ESD protection solutions for the low-voltage/radio frequency integrated circuits in SiGe BiCMOS process. In the end, we optimized SCRs in standard silicon-based CMOS process to supply protection for high speed/radio-frequency ICs. SCR is again considered the best for its excellent current handling ability. But the parasitic capacitance of SCRs needs to be reduced to limit SCR's impact to RF performance. We proposed a novel SCR-based ESD structure and characterize it experimentally for the design of effective ESD protection in high-frequency CMOS based integrated circuits. The proposed SCR-based ESD protection device showed a much lower parasitic capacitance and better ESD performance than the conventional SCR and a low-capacitance SCR reported in the literature. The physics underlying the low capacitance was explained by measurements using HP 4284 capacitance meter. Throughout the dissertation work, all the measurements are mainly conducted using Barth 4002 transimission line pulsing (TLP) and Barth 4012 very fast transmission line pulsing (vfTLP) testers. All the simulation was performed using Sentaurus TCAD tool from Synopsys.
Ph.D.
Doctorate
Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering
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5

Diatta, Marianne Amemagne. "Fiabilité des diodes de protection ESD soumises à des décharges électrostatiques répétitives". Toulouse 3, 2012. http://thesesups.ups-tlse.fr/4126/.

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La sensibilité des composants vis-à-vis des décharges électrostatiques (ESD) reste d'actualité avec la réduction des dimensions technologiques. En effet, les développements industriels et la sévérité de l'environnement subi par les applications électroniques qui sont devenues de plus en plus portatives mènent aujourd'hui au durcissement des conditions de fiabilité requises par les clients. Des spécifications initialement limitées aux systèmes électroniques se voient désormais étendues aux circuits intégrés pour atteindre les composants discrets. Afin de garantir d'excellents niveaux de fiabilité ESD notamment en répétitif, la méthodologie qui a été mise en œuvre consiste à comprendre des mécanismes de dégradation en ESD répétitives à travers les moyens de caractérisation physique, électrique et de simulation électrothermique. En effet, une nouvelle spécification client exige non seulement une immunité ESD de 15 kV pour une norme de type IEC 61000-4-2 mais aussi réclame une garantie de la non dégradation de ses fonctionnalités suite à la répétition de 1000 décharges de 15 kV sur le circuit intégré. Ainsi, la diode bidirectionnelle très souvent localisée en entrée et en sortie des circuits intégrés et permettant ainsi d'assurer leur protection vis-à-vis des décharges électrostatiques (ESD) pouvant surgir durant la durée de vie du système constitue le composant à la base de notre étude. Les investigations physiques de la défaillance ont permis de redessiner le scénario de dégradation en définissant la nature du défaut et sa génération, d'origine structurale pour ainsi décrire son évolution jusqu'à la défaillance. Associer la simulation électrothermique aux résultats expérimentaux permet de confirmer des phénomènes physiques tels que les phénomènes d'électro-thermo-migration surgissant durant une ESD. A l'issue de ces analyses, l'optimisation de la fiabilité de la diode en endurance est confirmée grâce à la suppression du défaut initial par l'amélioration du processus de fabrication
The sensitiveness of components towards electrostatic discharges (ESD) remains a key point in the frame of shrinked technologies. Indeed, industrial developments associated to a harsh environment for more and more smart electronic applications lead to aggressive reliability requirements by customer. Hence, specifications initially dedicated to electronic systems extends to integrated circuits then discrete components. In fact, customers require, in addition to the 15kV robustness for IEC 61000-4-2 norm, to withstand ESD reliability level by specifying immunity of the integrated circuit after applying 1000 discharges of 15kV level. To guarantee this ESD reliability level, especially in a repetitive mode, the methodology developed in this study consists in the understanding of failure mechanisms through physical and electrical characterizations associated to electro-thermal simulations. In integrated circuits, bidirectional diodes often localized at the input and output ensure a protection towards ESD that could occurs during system lifetime. In this context, the study particularly focuses on this discrete protection diode. Physical investigations on repetitive ESD failures describe the failure mechanism from structural defect creation to destruction. Moreover, gathering electro-thermal simulations to experimental results confirms appearance of electro-thermo-migration physical phenomenon during repetitive ESD. As a conclusion, removing the structural defects through a metal barrier considerably improves the ESD endurance and fully satisfy customer requirements while preserving intrinsic performances
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6

Lim, Tek Fouy. "Dispositifs de protection contre les décharges électrostatiques pour les applications radio fréquences et millimétriques". Thesis, Grenoble, 2013. http://www.theses.fr/2013GRENT033/document.

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Ces travaux s'inscrivent dans un contexte où les contraintes vis-à-vis des décharges électrostatiques sont de plus en plus fortes, les circuits de protection sont un problème récurrent pour les circuits fonctionnant à hautes fréquences. La capacité parasite des composants de protection limite fortement la transmission du signal et peut perturber fortement le fonctionnement normal d'un circuit. Les travaux présentés dans ce mémoire font suite à une volonté de fournir aux concepteurs de circuits fonctionnant aux fréquences millimétriques un circuit de protection robuste présentant de faibles pertes en transmission, avec des dimensions très petites et fonctionnant sur une très large bande de fréquences, allant du courant continu à 100 GHz. Pour cela, une étude approfondie des lignes de transmission et des composants de protection a été réalisée à l'aide de simulations électromagnétiques et de circuits. Placés et fragmentées le long de ces lignes de transmission, les composants de protection ont été optimisés afin de perturber le moins possible la transmission du signal, tout en gardant une forte robustesse face aux décharges électrostatiques. Cette stratégie de protection a été réalisée et validée en technologies CMOS avancées par des mesures fréquentielles, électriques et de courant de fuite
Advanced CMOS technologies provide an easier way to realize radio-frequency integrated circuits (RFICs). However, the lithography dimension shrink make electrostatic discharges (ESD) issues become more significant. Specific ESD protection devices are embedded in RFICs to avoid any damage. Unfortunately, ESD protections parasitic capacitance limits the operating bandwidth of RFICs. ESD protection size dimensions are also an issue for the protection of RFICs, in order to avoid a significant increase in production costs. This work focuses on a broadband ESD solution (DC-100 GHz) able to be implemented in an I/O pad to protect RFICs in advanced CMOS technologies. Thanks to the signal transmission properties of coplanar / microstrip lines, a broadband ESD solution is achieved by implementing ESD components under a transmission line. The silicon proved structure is broadband; it can be used in any RF circuits and fulfill ESD target. The physical dimensions also enable easy on-chip integration
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7

SALCEDO, Javier. "DESIGN AND CHARACTERIZATION OF NOVELDEVICES FOR NEW GENERATION OF ELECTROSTATICDISCHARGE (ESD) PROTECTION STRUCTURES". Doctoral diss., University of Central Florida, 2006. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/2812.

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The technology evolution and complexity of new circuit applications involve emerging reliability problems and even more sensitivity of integrated circuits (ICs) to electrostatic discharge (ESD)-induced damage. Regardless of the aggressive evolution in downscaling and subsequent improvement in applications' performance, ICs still should comply with minimum standards of ESD robustness in order to be commercially viable. Although the topic of ESD has received attention industry-wide, the design of robust protection structures and circuits remains challenging because ESD failure mechanisms continue to become more acute and design windows less flexible. The sensitivity of smaller devices, along with a limited understanding of the ESD phenomena and the resulting empirical approach to solving the problem have yielded time consuming, costly and unpredictable design procedures. As turnaround design cycles in new technologies continue to decrease, the traditional trial-and-error design strategy is no longer acceptable, and better analysis capabilities and a systematic design approach are essential to accomplish the increasingly difficult task of adequate ESD protection-circuit design. This dissertation presents a comprehensive design methodology for implementing custom on-chip ESD protection structures in different commercial technologies. First, the ESD topic in the semiconductor industry is revised, as well as ESD standards and commonly used schemes to provide ESD protection in ICs. The general ESD protection approaches are illustrated and discussed using different types of protection components and the concept of the ESD design window. The problem of implementing and assessing ESD protection structures is addressed next, starting from the general discussion of two design methods. The first ESD design method follows an experimental approach, in which design requirements are obtained via fabrication, testing and failure analysis. The second method consists of the technology computer aided design (TCAD)-assisted ESD protection design. This method incorporates numerical simulations in different stages of the ESD design process, and thus results in a more predictable and systematic ESD development strategy. Physical models considered in the device simulation are discussed and subsequently utilized in different ESD designs along this study. The implementation of new custom ESD protection devices and a further integration strategy based on the concept of the high-holding, low-voltage-trigger, silicon controlled rectifier (SCR) (HH-LVTSCR) is demonstrated for implementing ESD solutions in commercial low-voltage digital and mixed-signal applications developed using complementary metal oxide semiconductor (CMOS) and bipolar CMOS (BiCMOS) technologies. This ESD protection concept proposed in this study is also successfully incorporated for implementing a tailored ESD protection solution for an emerging CMOS-based embedded MicroElectroMechanical (MEMS) sensor system-on-a-chip (SoC) technology. Circuit applications that are required to operate at relatively large input/output (I/O) voltage, above/below the VDD/VSS core circuit power supply, introduce further complications in the development and integration of ESD protection solutions. In these applications, the I/O operating voltage can extend over one order of magnitude larger than the safe operating voltage established in advanced technologies, while the IC is also required to comply with stringent ESD robustness requirements. A practical TCAD methodology based on a process- and device- simulation is demonstrated for assessment of the device physics, and subsequent design and implementation of custom P1N1-P2N2 and coupled P1N1-P2N2//N2P3-N3P1 silicon controlled rectifier (SCR)-type devices for ESD protection in different circuit applications, including those applications operating at I/O voltage considerably above/below the VDD/VSS. Results from the TCAD simulations are compared with measurements and used for developing technology- and circuit-adapted protection structures, capable of blocking large voltages and providing versatile dual-polarity symmetric/asymmetric S-type current-voltage characteristics for high ESD protection. The design guidelines introduced in this dissertation are used to optimize and extend the ESD protection capability in existing CMOS/BiCMOS technologies, by implementing smaller and more robust single- or dual-polarity ESD protection structures within the flexibility provided in the specific fabrication process. The ESD design methodologies and characteristics of the developed protection devices are demonstrated via ESD measurements obtained from fabricated stand-alone devices and on-chip ESD protections. The superior ESD protection performance of the devices developed in this study is also successfully verified in IC applications where the standard ESD protection approaches are not suitable to meet the stringent area constraint and performance requirement.
Ph.D.
School of Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering
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8

Courivaud, Bertrand. "Développement et réalisation de nouvelles structures de protection contre les décharges électrostatiques". Thesis, Toulouse 3, 2015. http://www.theses.fr/2015TOU30273/document.

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Le cadre de cette étude se focalise sur le développement de protections contre les décharges électrostatiques (ESD) externes aux composants électroniques à protéger. Pour des raisons applicatives, ou l'encombrement devient une préoccupation majeure, ces protections ESD doivent répondre à des contraintes de taille toujours plus difficiles à satisfaire tout en gardant les mêmes performances en robustesse. Ce travail présente un nouveau concept de structure de protection ESD bidirectionnel basé sur une technologie industrielle originellement dédié à la réalisation de capacités à haute densité d'intégration. Le procédé technologique possède une étape de fabrication de tranchées profonde qui est mise à profit dans cette étude pour la réalisation de diodes tridimensionnelles. L'optimisation de la configuration de ces structure a été menée par une étude théorique à l'aide des outils de simulation TCAD afin de mieux appréhender le fonctionnement physique et d'apporter des règles de conception. De nombreux résultats expérimentaux sont présentés et des comparaisons seront également menées afin de quantifier l'apport de cette nouvelle technologie. La meilleure configuration permet de garantir une réduction de 25% de la taille des structures tout en garantissant un niveau de robustesse élevé
As part of this study focuses on the development of external protection against electrostatic discharge (ESD) to the electronic components to protect. For many applicative reasons where taken area becomes a major concern, the ESD protection must meet size constraints increasingly difficult to satisfy while keeping the same performance in robustness. This work presents a new concept of bi-directional ESD protection structure based on industrial technology originally dedicated to achieving high-density integration capabilities. The technological process has a deep trench production step which is used in this study for the realization of three-dimensional diodes. Optimizing configuration of the structure was conducted by a theoretical study using TCAD simulation tools to better understand the physical functioning and provide design rules. Many experimental results are presented and comparisons will also be conducted to quantify the contribution of this new technology. The best configuration ensures a 25% reduction in the size of structures while ensuring a high level of robustness
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9

Solaro, Yohann. "Conception, fabrication et caractérisation de dispositifs innovants de protection contre les décharges électrostatiques en technologie FDSOI". Thesis, Grenoble, 2014. http://www.theses.fr/2014GRENT098/document.

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L’architecture FDSOI (silicium sur isolant totalement déserté) permet une amélioration significative du comportement électrostatique des transistors MOSFETs pour les technologies avancées et est employée industriellement à partir du noeud 28 nm.L’implémentation de protections contre les décharges électrostatiques (ESD pour« Electro Static Discharge ») dans ces technologies reste un défi. Alors que l’approche standard repose sur l’hybridation du substrat SOI (gravure de l’oxyde enterré : BOX)permettant de fabriquer des dispositifs de puissance verticaux, nous nous intéressons ici à des structures dans lesquelles la conduction s’effectue latéralement, dans le film de silicium. Dans ces travaux, des approches alternatives utilisant des dispositifs innovants(Z²-FET et BBC-T) sont proposées. Leurs caractéristiques statiques, quasi-statiques et transitoires sont étudiées, par le biais de simulations TCAD et de caractérisations électriques
FDSOI architecture (Fully Depleted Silicon On Insulator) allows a significantimprovement of the electrostatic behavior of the MOSFETs transistors for the advancedtechnologies. It is industrially employed from the 28 nm node. However, theimplementation of ESD (Electrostatic Discharges) protections in these technologies isstill a challenge. While the standard approach relies on SOI substrate hybridization (byetching the BOX (buried oxide)), allowing to fabricate vertical power devices, we focushere on structures where the current flows laterally, in the silicon film. In this work,alternative approaches using innovative devices (Z²-FET and BBC-T) are proposed. Theirstatic, quasi-static and transient characteristics are studied in detail, with TCADsimulations and electrical characterizations
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10

Lu, Hsueh-Meng y 呂學銘. "New ESD Protection Circuits". Thesis, 2004. http://ndltd.ncl.edu.tw/handle/22693499839469841539.

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碩士
國立臺灣科技大學
電子工程系
92
Due to the area-efficient, the SCR has become the best choice for ESD protection circuits. However, the behaviors of latchup and higher trigger voltage are the limitations for SCR’s application. Therefore, it is needed to pay much attention to design better ESD protection circuits in deep-submicron CMOS IC. In this thesis, we have proposed two new ESD protection circuits based on SCR structure. The performance of these protection circuits is really excellent when ESD event happened. One of the protection circuits is a highly latchup-immune stacked-MOSFET with silicon controlled rectifier (SM-SCR) device. The latchup effect could be avoided by using the stacked-MOSFET to turn on/off the SCR. Meanwhile, a zener diode and gate-coupled transistor can lower SM-SCR trigger voltage. The other protection circuit is a highly latchup-free ESD protection circuit with silicon controlled rectifier (LFSCR) device to demonstrate the effective ESD protection effect. The mechanism is to turn on/off the SCR by two MOSFETs during an ESD event. During the ESD event, the PMOS transistor is utilized to turn on SCR and the NMOS transistor to turn off SCR. Therefore the latchup effect can be easily eliminated by this device. Besides, the purpose of the zener diode and gate-coupled transistor could lower the trigger voltage. The implementation of these two on-chip protection circuits has been fabricated through National Science Council Chip-Implementation-Center (CIC). These two ESD protection circuits have been applied for patents in R.O.C. and U.S.A.
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Libros sobre el tema "Protection ESD"

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Vashchenko, Vladislav y Mirko Scholz. System Level ESD Protection. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-03221-4.

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Esmark, Kai. Device simulation of ESD protection elements. Konstanz: Hartung-Gorre, 2002.

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Harald, Gossner y Stadler Wolfgang, eds. Advanced simulation methods for ESD protection development. Amsterdam: Elsevier, 2003.

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Voldman, Steven H. ESD. New York: John Wiley & Sons, Ltd., 2006.

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Voldman, Steven H. ESD. New York: John Wiley & Sons, Ltd., 2006.

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Voldman, Steven Howard. ESD Physics and Devices. New York: John Wiley & Sons, Ltd., 2005.

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Stricker, Andreas D. Technology computer aided design of ESD protection devices. Konstanz: Hartung-Gorre Verlag, 2001.

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1944-, Duvvury Charvaka, ed. ESD in silicon integrated circuits. 2a ed. Chichester: J. Wiley, 2002.

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Amerasekera, E. A. ESD in silicon integrated circuits. Chichester: J. Wiley, 1995.

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Hellström, Sten. ESD: The scourge of electronics. Berlin: Springer, 1998.

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Capítulos de libros sobre el tema "Protection ESD"

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Vinson, James E., Joseph C. Bernier, Gregg D. Croft y Juin J. Liou. "Environmental Protection". En ESD Design and Analysis Handbook, 85–109. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4615-0321-7_3.

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Vashchenko, Vladislav y Mirko Scholz. "System Level ESD Design". En System Level ESD Protection, 1–49. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-03221-4_1.

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Dangelmayer, G. Theodore. "Designed-In Protection and Product Testing". En ESD Program Management, 77–92. Boston, MA: Springer US, 1990. http://dx.doi.org/10.1007/978-1-4615-6933-6_5.

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Dangelmayer, G. Theodore. "Designed-In Protection and Product Testing". En ESD Program Management, 77–92. Boston, MA: Springer US, 1990. http://dx.doi.org/10.1007/978-1-4613-1179-9_5.

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Vinson, James E., Joseph C. Bernier, Gregg D. Croft y Juin J. Liou. "Chip Level Protection". En ESD Design and Analysis Handbook, 111–55. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4615-0321-7_4.

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Vashchenko, Vladislav y Mirko Scholz. "System Level Test Methods". En System Level ESD Protection, 51–109. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-03221-4_2.

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Vashchenko, Vladislav y Mirko Scholz. "On-Chip System Level ESD Devices and Clamps". En System Level ESD Protection, 111–98. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-03221-4_3.

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Vashchenko, Vladislav y Mirko Scholz. "Latch-up at System-Level Stress". En System Level ESD Protection, 199–245. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-03221-4_4.

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Vashchenko, Vladislav y Mirko Scholz. "IC and System ESD Co-design". En System Level ESD Protection, 247–309. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-03221-4_5.

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Hellström, Sten. "Protection methods — Antistatic materials". En ESD — The Scourge of Electronics, 136–70. Berlin, Heidelberg: Springer Berlin Heidelberg, 1998. http://dx.doi.org/10.1007/978-3-642-80302-4_11.

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Actas de conferencias sobre el tema "Protection ESD"

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Huang, Shao-Chang, Jian-Hsing Lee, Li-Fan Chen, Chun-Chih Chen, Ting-You Lin, Kai-Chieh Hsu, Yeh-Ning Jou, Chih-Hsuan Lin, Yung-Chang Chen y Wei-Sung Chen. "ESD Protection for Poly Fuses". En 2019 41st Annual EOS/ESD Symposium (EOS/ESD). IEEE, 2019. http://dx.doi.org/10.23919/eos/esd.2019.8869968.

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Drallmeier, Matthew y Elyse Rosenbaum. "Distributed Protection for High-Speed Wireline Receivers". En 2023 45th Annual EOS/ESD Symposium (EOS/ESD). IEEE, 2023. http://dx.doi.org/10.23919/eos/esd58195.2023.10287739.

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Eichenseer, Christoph, Gernot Langguth, Reinhold Gaertner, Friedrich Zur Nieden, Lena Zeitlhoefler y Stefan Kokorovic. "Fast Transient ESD Protection at RF Pins". En 2023 45th Annual EOS/ESD Symposium (EOS/ESD). IEEE, 2023. http://dx.doi.org/10.23919/eos/esd58195.2023.10287754.

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Pan, Zijin, Weiquan Hao, Xunyu Li, Runyu Miao, Cheng Li y Albert Wang. "Think Nontraditionally for Future ESD Protection (Invited)". En 2022 44th Annual EOS/ESD Symposium (EOS/ESD). IEEE, 2022. http://dx.doi.org/10.23919/eos/esd54763.2022.9928475.

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Vashchenko, Vladislav. "HV Active Core Clamps with Over Voltage Protection". En 2022 44th Annual EOS/ESD Symposium (EOS/ESD). IEEE, 2022. http://dx.doi.org/10.23919/eos/esd54763.2022.9928467.

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Vashchenko, Vladislav y Slavica Malobabic. "EOS Protection of the Low Voltage Gate Oxide Devices". En 2019 41st Annual EOS/ESD Symposium (EOS/ESD). IEEE, 2019. http://dx.doi.org/10.23919/eos/esd.2019.8870009.

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Park, Myunghwan, Jermyn Tseng, Tzung-yin Lee y David Ripley. "Concurrent ESD and Surge Protection Clamps in RF Power Amplifier". En 2019 41st Annual EOS/ESD Symposium (EOS/ESD). IEEE, 2019. http://dx.doi.org/10.23919/eos/esd.2019.8869975.

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Malobabic, Slavica, David Marreiro y Vladislav Vashchenko. "Dual Injection Latchup Phenomenon in HV Rail Based ESD Protection Networks". En 2019 41st Annual EOS/ESD Symposium (EOS/ESD). IEEE, 2019. http://dx.doi.org/10.23919/eos/esd.2019.8869970.

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Zeng, Jie, Raunak Kumar, Kun Liu, Aloysius P. Herlambang, Kyong Jin Hwang y Robert Gauthier. "High Voltage PNP Device Using RESURF Structure for Above 40V ESD Protection". En 2021 43rd Annual EOS/ESD Symposium (EOS/ESD). IEEE, 2021. http://dx.doi.org/10.23919/eos/esd52038.2021.9574755.

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Zhou, Yuanzhong Paul, Guanghai Ding y Jean-Jacques Hajjar. "ESD Protection Impact and Modelling of Bias-Dependent Series Resistance in Diodes". En 2019 41st Annual EOS/ESD Symposium (EOS/ESD). IEEE, 2019. http://dx.doi.org/10.23919/eos/esd.2019.8869988.

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Informes sobre el tema "Protection ESD"

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SALAS, FREDERICK J., DANIEL H. SANCHEZ y JOHN HARVEY WEINLEIN. Electrostatic Discharge (ESD) Protection for a Laser Diode Ignited Actuator. Office of Scientific and Technical Information (OSTI), junio de 2003. http://dx.doi.org/10.2172/820898.

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Jager, Yetta, Brenna L. Elrod, Nicole M. Samu, Ryan A. McManamay y Brennan T. Smith. ESA Protection for the American Eel: Implications for US Hydropower. Office of Scientific and Technical Information (OSTI), noviembre de 2013. http://dx.doi.org/10.2172/1110872.

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Cervantes, Rachel. The Role of the Telomere End Protection Complex in Telomere Main. Fort Belvoir, VA: Defense Technical Information Center, junio de 2003. http://dx.doi.org/10.21236/ada437895.

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Cervantes, Rachel B. The Role of the Telomere End Protection Complex in Telomere Maintenance. Fort Belvoir, VA: Defense Technical Information Center, junio de 2003. http://dx.doi.org/10.21236/ada417832.

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Research Institute (IFPRI), International Food Policy. Boosting Growth to End Hunger by 2025: The Role of Social Protection. Washington, DC: International Food Policy Research Institute, 2018. http://dx.doi.org/10.2499/9780896295988.

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Research Institute (IFPRI), International Food Policy. Boosting Growth to End Hunger by 2025: The Role of Social Protection. Washington, DC: International Food Policy Research Institute, 2018. http://dx.doi.org/10.2499/97808962959888.

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Buckless, Genna, Trish Vargo, John Walther y Freeman Marvin. Technology Investment Strategy Annex Collective Protection Front End Analysis and Master Plan Report. Fort Belvoir, VA: Defense Technical Information Center, junio de 2004. http://dx.doi.org/10.21236/ada424916.

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Research Institute (IFPRI), International Food Policy. Introduction in Boosting Growth to End Hunger by 2025: The Role of Social Protection. Washington, DC: International Food Policy Research Institute, 2018. http://dx.doi.org/10.2499/9780896295988_01.

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Research Institute (IFPRI), International Food Policy. Conclusion in Boosting growth to end hunger by 2025: The role of social protection. Washington, DC: International Food Policy Research Institute, 2018. http://dx.doi.org/10.2499/9780896295988_13.

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Research Institute (IFPRI), International Food Policy. Executive summary in Boosting growth to end hunger by 2025: The role of social protection. Washington, DC: International Food Policy Research Institute, 2018. http://dx.doi.org/10.2499/9780896295988_exsum.

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