Bibliografías temáticas / Semiconductor wafers. Silicon Silicon Electrodiffusion

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Literatura académica sobre el tema "Semiconductor wafers. Silicon Silicon Electrodiffusion"

Autor: Grafiati
Publicado: 4 de junio de 2021
Última modificación: 10 de febrero de 2022

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Artículos de revistas sobre el tema "Semiconductor wafers. Silicon Silicon Electrodiffusion"

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Jennings, Michael R., Amador Pérez-Tomás, Owen J. Guy, Michal Lodzinski, Peter M. Gammon, Susan E. Burrows, James A. Covington y Philip A. Mawby. "Silicon-on-SiC, a Novel Semiconductor Structure for Power Devices". Materials Science Forum 645-648 (abril de 2010): 1243–46. http://dx.doi.org/10.4028/www.scientific.net/msf.645-648.1243.

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A physical and electrical analysis of Si/SiC heterojunctions formed by layer transfer based on the smartcut® process is presented in this paper. AFM and SEM have revealed a high bonding quality when Si wafers are transferred to SiC on-axis wafers. XRD points to the fact that the layers are monocrystalline in nature. A surface AFM analysis of the bonded wafers demonstrated a smooth surface (rms = 5.8 nm) suitable for semiconductor device fabrication. Capacitors have been fabricated from the Si/SiC heterojunctions, which have been totally oxidised. Oxidised Si/SiC structures yielded a lower density of interface states than conventional thermal oxidation techniques.
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Oliver, James D., Russ Kremer, Arnd Dietrich Weber, Kevin Nguyen y James Amano. "SEMI Standards for SiC Wafers". Materials Science Forum 924 (junio de 2018): 5–10. http://dx.doi.org/10.4028/www.scientific.net/msf.924.5.

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SEMI Standards charter is to develop standards that benefit the semiconductor industry. The SEMI organization has evolved over the last 40 years into an international organization with covering all aspects of semiconductor and flat panel materials and devices. SEMI Standards provides the framework for the development of consensus based standards documents. At present there are two published standards specific to silicon carbide, the first dealing with dimensions, properties and ordering information for SiC wafers, and the second defining a nomenclature for defects found on SiC: SEMI M55-0817 Specification for Polished Monocrystalline Silicon Carbide Wafers SEMI M81-0611 Guide to Defects Found on Monocrystalline Silicon Carbide Substrates Additional standards applicable to various semiconductor wafers also are available and new SiC related standards are being developed based on industry needs and volunteer participation.
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FUKUDA, Tetsuo, Atsunobu UNE, Akira FUKUDA y Yasuhide NAKAI. "1601 Mechanical Issues of Silicon Wafers for Semiconductor Devices". Proceedings of The Computational Mechanics Conference 2009.22 (2009): 534–35. http://dx.doi.org/10.1299/jsmecmd.2009.22.534.

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Sianko, S. F. y V. A. Zelenin. "ESTIMATION OF TOPOGRAPHIC DEFECTS DIMENSIONS OF SEMICONDUCTOR SILICON STRUCTURES". Devices and Methods of Measurements 9, n.º 1 (20 de marzo de 2018): 74–84. http://dx.doi.org/10.21122/2220-9506-2018-9-1-74-84.

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The effect of non-flatness of semiconductor wafers on characteristics of manufactured devices is shown through defocusing of an image of a topological layout of a structure being formed and through reduction of resolution at photolithographic processing. For quality control of non-flatness the Makyoh method is widely used. However, it does not allow obtaining quantitative characteristics of observed defects, which essentially restricts its application. The objective of this work has been developing of a calculation method for dimensions of topographic defects of wafers having semiconductor structures formed on them, which has allowed determining acceptability criteria for wafers, depending on defects dimensions and conducting their timely penalization.A calculation method under development is based on deduction of relationships linking distortion of image elements to curvature of local sections of a semiconductor wafer that has formed structures. These structures have been considered to be image finite elements and within this range the curvature radius has been assumed to be constant. Sequential calculation of deviation of element ends from ideal plane based on determining their curvature radius has allowed obtaining geometry of a target surface in a set range of elements. Conditions of image formation and requirements to structures have been determined.Analytical expressions relating a deviation value of elements of a light-to-dark image with surface geometry have been obtained. This allows conducting effective quantitative control of observed topographic defects both under production and research conditions. Examples of calculation of topographic defects of semiconductor silicon wafers have been provided. Comparison of the obtained results with the data obtained by conventional methods has shown their complete conformity.
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Solodukha, V. A., G. G. Chigir, V. A. Pilipenko, V. A. Filipenya y V. A. Gorushko. "Reliability Express Control of the Gate Dielectric of Semiconductor Devices". Devices and Methods of Measurements 9, n.º 4 (17 de diciembre de 2018): 308–13. http://dx.doi.org/10.21122/2220-9506-2018-9-4-308-313.

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The key element determining stability of the semiconductor devices is a gate dielectric. As its thickness reduces in the process of scaling the combined volume of factors determining its electrophysical properties increases. The purpose of this paper is development of the control express method of the error-free running time of the gate dielectric and study the influence of the rapid thermal treatment of the initial silicon wafers and gate dielectric on its reliability.The paper proposes a model for evaluation of the reliability indicators of the gate dielectrics as per the trial results of the test MDS-structures by means of applying of the ramp-increasing voltage on the gate up to the moment of the structure breakdown at various velocities of the voltage sweep with measurement of the IV-parameters. The proposed model makes it possible to realize the express method of the reliability evaluation of the thin dielectrics right in the production process of the integrated circuits.On the basis of this method study of the influence of the rapid thermal treatment of the initial silicon wafers of the KEF 4.5, KDB 12 wafers and formed on them by means of the pyrogenic oxidation of the gate dielectric for the error-free running time were performed. It is shown, that rapid thermal treatment of the initial silicon wafers with their subsequent oxidation results in increase of the error-free running time of the gate dielectric on average from 12.9 to 15.9 years (1.23 times greater). Thermal treatment of the initial silicon wafers and gate dielectric makes it possible to expand the error-free running time up to 25.2 years, i.e.1.89 times more, than in the standard process of the pyrogenic oxidation and 1.5 times more, than under application of the rapid thermal treatment of the initial silicon wafers only.
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Couey, Jeremiah A., Eric R. Marsh, Byron R. Knapp y R. Ryan Vallance. "In-process force monitoring for precision grinding semiconductor silicon wafers". International Journal of Manufacturing Technology and Management 7, n.º 5/6 (2005): 430. http://dx.doi.org/10.1504/ijmtm.2005.007695.

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Sreejith, P. S., G. Udupa, Y. B. M. Noor y B. K. A. Ngoi. "Recent Advances in Machining of Silicon Wafers for Semiconductor Applications". International Journal of Advanced Manufacturing Technology 17, n.º 3 (1 de enero de 2001): 157–62. http://dx.doi.org/10.1007/s001700170185.

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Kurita, Kazunari, Takeshi Kadono, Satoshi Shigematsu, Ryo Hirose, Ryosuke Okuyama, Ayumi Onaka-Masada, Hidehiko Okuda y Yoshihiro Koga. "Proximity Gettering Design of Hydrocarbon–Molecular–Ion–Implanted Silicon Wafers Using Dark Current Spectroscopy for CMOS Image Sensors". Sensors 19, n.º 9 (4 de mayo de 2019): 2073. http://dx.doi.org/10.3390/s19092073.

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We developed silicon epitaxial wafers with high gettering capability by using hydrocarbon–molecular–ion implantation. These wafers also have the effect of hydrogen passivation on process-induced defects and a barrier to out-diffusion of oxygen of the Czochralski silicon (CZ) substrate bulk during Complementary metal-oxide-semiconductor (CMOS) device fabrication processes. We evaluated the electrical device performance of CMOS image sensor fabricated on this type of wafer by using dark current spectroscopy. We found fewer white spot defects compared with those of intrinsic gettering (IG) silicon wafers. We believe that these hydrocarbon–molecular–ion–implanted silicon epitaxial wafers will improve the device performance of CMOS image sensors.
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Кукушкин, С. А., И. П. Калинкин y А. В. Осипов. "Влияние химической подготовки поверхности кремния на качество и структуру эпитаксиальных пленок карбида кремния, синтезированных методом замещения атомов". Физика и техника полупроводников 52, n.º 6 (2018): 656. http://dx.doi.org/10.21883/ftp.2018.06.45932.8758.

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AbstractThe fundamentals of a new technique for the cleaning and passivation of (111), (110), and (100) silicon wafer surfaces by hydride groups, which ensure a high surface purity and smoothness at the nanoscale upon long-term storage of the wafers at room temperature in air, are discussed. A new composition of the passivation solution for the long-term antioxidation protection of silicon surfaces is developed. The proposed solution is suitable for the long-term storage and repeated passivation of silicon wafers. The composition of the passivation solution and the conditions of passivation of the silicon wafers in it are described. Silicon wafers treated using the proposed technique can be used for growing epitaxial semiconductor films and different nanostructures. It is shown that only silicon surfaces prepared in this way allow SiC epitaxial films on silicon to be grown by atom substitution. The experimental dependences of the SiC and GaN film structures grown on silicon on the silicon-surface etching conditions are presented. The developed technique for silicon cleaning and passivation can both be used under laboratory conditions and easily adapted for the industrial production of silicon wafers with an oxidation-resistant surface coating.
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Haring, Fred, Syed Sajid Ahmad, Nathan Schneck, Kaycie Gerstner, Nicole Dallman, Chris Hoffarth y Aaron Reinholz. "Spin Coating of Dielectrics on Thin Silicon To Enhance Strength Characteristics". International Symposium on Microelectronics 2010, n.º 1 (1 de enero de 2010): 000339–43. http://dx.doi.org/10.4071/isom-2010-tp5-paper3.

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Use of very thin wafers in the semiconductor industry poses handling challenges during manufacturing. The goal of this study was to determine whether applying thin coatings could create stronger, easy to handle wafers. Standard three-point bend testing of coated and uncoated thin wafer samples was used to determine whether the coating strengthened the wafers to improve their handling properties. Data indicated that only the thinnest coating on the thinner silicon increased the peak break strength in three-point bend testing.
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Tesis sobre el tema "Semiconductor wafers. Silicon Silicon Electrodiffusion"

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Gibbons, Brian J. "Electromigration induced step instabilities on silicon surfaces". Columbus, Ohio : Ohio State University, 2006. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1143235175.

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Wang, Hongyun. "Advanced processing methods for microelectronics industry silicon wafer handling components /". Full text (PDF) from UMI/Dissertation Abstracts International, 1999. http://wwwlib.umi.com/cr/utexas/fullcit?p3004411.

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Garcia, Victoria. "Effect of dislocation density on residual stress in polycrystalline silicon wafers". Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/22621.

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Brun, Xavier F. "Analysis of handling stresses and breakage of thin crystalline silicon wafers". Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/26538.

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Thesis (Ph.D)--Mechanical Engineering, Georgia Institute of Technology, 2009.
Committee Chair: Melkote, Shreyes; Committee Member: Danyluk, Steven; Committee Member: Griffin, Paul; Committee Member: Johnson, Steven; Committee Member: Kalejs, Juris; Committee Member: Sitaraman, Suresh. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Lopez, Parra Marcelo. "The design, manufacture and testing of a low-cost cleanroom robot for handling silicon wafers". Thesis, Cranfield University, 1994. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.260098.

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Vedantham, Vikram. "In-situ temperature and thickness characterization for silicon wafers undergoing thermal annealing". Thesis, Texas A&M University, 2003. http://hdl.handle.net/1969.1/1181.

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Nano scale processing of IC chips has become the prime production technique as the microelectronic industry aims towards scaling down product dimensions while increasing accuracy and performance. Accurate control of temperature and a good monitoring mechanism for thickness of the deposition layers during epitaxial growth are critical parameters influencing a good yield. The two-fold objective of this thesis is to establish the feasibility of an alternative to the current pyrometric and ellipsometric techniques to simultaneously measure temperature and thickness during wafer processing. TAP-NDE is a non-contact, non-invasive, laser-based ultrasound technique that is employed in this study to contemporarily profile the thermal and spatial characteristics of the wafer. The Gabor wavelet transform allows the wave dispersion to be unraveled and the group velocity of individual frequency components to be extracted from the experimentally acquired time waveform. The thesis illustrates the formulation of a theoretical model that is used to identify the frequencies sensitive to temperature and thickness changes. The group velocity of the corresponding frequency components is determined and their corresponding changes with respect to temperature for different thickness are analytically modeled. TAP-NDE is then used to perform an experimental analysis on Silicon wafers of different thickness to determine the maximum possible resolution of TAP-NDE towards temperature sensitivity, and to demonstrate the ability to differentiate between wafers of different deposition layer thickness at temperatures up to 600?C. Temperature resolution is demonstrated for ?10?C resolution and for ?5?C resolution; while thickness differentiation is carried out with wafers carrying 4000? and 8000? of aluminum deposition layer. The experimental group velocities of a set of selected frequency components extracted using the Gabor Wavelet time-frequency analysis as compared to their corresponding theoretical group velocities show satisfactory agreement. As a result of this work, it is seen that TAP-NDE is a suitable tool to identify and characterize thickness and temperature changes simultaneously during thermal annealing that can replace the current need for separate characterization of these two important parameters in semiconductor manufacturing.
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Syed, Ahmed Rashid. "Non-invasive thermal profiling of silicon wafer surface during RTP using acoustic and signal processing techniques /". Digital version accessible at:, 2000. http://wwwlib.umi.com/cr/utexas/main.

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Chien, Hsu-Yueh. "Investigation of Copper Out-Plating Mechanism on Silicon Wafer Surface". Thesis, University of North Texas, 1995. https://digital.library.unt.edu/ark:/67531/metadc278367/.

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As the miniaturization keeps decreasing in semiconductor device fabrication, metal contamination on silicon surfaces becomes critical. An investigation of the fundamental mechanism of metal contamination process on silicon surface is therefore important. Kinetics and thermodynamics of the copper out-plating process on silicon surfaces in diluted HF solutions are both evaluated by several analytical methods.
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Dukic, Megan Marie. "Vibrating Kelvin Probe Measurements of a Silicon Surface with the Underside Exposed to Light". Thesis, Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/19862.

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This thesis addresses the use of a vibrating Kelvin probe to monitor the change in the front surface potential of a silicon wafer while the rear surface is illuminated with monochromatic, visible light. Two tests were run to verify the change in surface potential. One test increased the intensity of the light and the other increased the wavelength while recording the front surface potential. The change in the surface potential for a range of intensities of incident light was recorded and analyzed. The results show that the change in surface potential increased with increasing intensity. For each wafer, the smallest change in surface potential occurred at the lowest intensity, 3.77 mW. In the same respect, the largest change in surface potential occurred at the highest intensity, 17.8 mW. For all wafers, the change in surface potential ranged from approximately 8 mV at 3.77 mW to approximately 80 mV at 17.8 mW. The change in the surface potential for a range of wavelengths of incident light was also recorded and analyzed. The results showed that the change in surface potential formed a skewed bell curve with increasing wavelength of incident light. For each wafer, the largest change in surface potential occurred at mid-range wavelengths, between 600 nm and 700 nm. The smallest change in surface potential occurred at 450 nm, the shortest wavelength, and 800 nm, the longest wavelength. For all wafers, the change in surface potential ranged from approximately 8 mV at 800 nm to approximately 165 mV at 700 nm. A model based on excess electron diffusion within the silicon wafer was used to predict material properties. After curve fitting the model with experimental results, an excess electron lifetime of ôN = 17 µs and surface recombination rates of sFRONT = sREAR = 18,000cm/s were predicted. These values suggest poor silicon wafer quality relative to commercial silicon devices. Regardless of the quality, the results show that the front surface potential of a silicon wafer is affected by incident light on the rear surface. The quantitative effect of the light is dependent on the properties of the light and the material properties of the silicon wafer.
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Yoder, Karl J. "Influence of design and coatings on the mechanical reliability of semiconductor wafers". Thesis, University of North Texas, 2002. https://digital.library.unt.edu/ark:/67531/metadc3190/.

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We investigate some of the mechanical design factors of wafers and the effect on strength. Thin, solid, pre-stressed films are proposed as a means to improve the bulk mechanical properties of a wafer. Three-point bending was used to evaluate the laser scribe density and chemical processing effect on wafer strength. Drop and strike tests were employed to investigate the edge bevel profile effect on the mechanical properties of the wafer. To characterize the effect of thin films on strength, one-micron ceramic films were deposited on wafers using PECVD. Coated samples were prepared by cleaving and were tested using four-point bending. Film adhesion was characterized by notched four-point bending. RBS and FTIR were used to obtain film chemistry, and nanoindentation was used to investigate thin film mechanical properties. A stress measurement gauge characterized residual film stress. Mechanical properties of the wafers correlated to the residual stress in the film.
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Libros sobre el tema "Semiconductor wafers. Silicon Silicon Electrodiffusion"

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International Symposium on High Purity Silicon (9th 2006 Cancún, Mexico). High purity silicon 9. Editado por Claeys Cor L, Electrochemical Society. Electronics and Photonics Division. y Electrochemical Society Meeting. Pennington, NJ: Electrochemical Society, 2006.

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International, Symposium on High Purity Silicon (9th 2006 Cancún Mexico). High purity silicon 9. Pennington, NJ: Electrochemical Society, 2006.

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L, Claeys Cor, Electrochemical Society Electronics Division, Society of Photo-optical Instrumentation Engineers. y Electrochemical Society Meeting, eds. High purity silicon VII. Pennington, NJ: Electrochemical Society, 2002.

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Bullis, W. Murray. Evolution of silicon materials characterization: Lessons learned for improved manufacturing. Gaithersburg, MD: U.S. Dept. of Commerce, National Institute of Standards and Technology, 1993.

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International Symposium on High Purity Silicon (8th 2004 Honolulu, Hawaii). High purity silicon VIII: Proceedings of the international symposium. Editado por Claeys Cor L, Electrochemical Society Electronics Division y Electrochemical Society Meeting. Pennington, NJ: Electrochemical Society, 2004.

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L, Claeys Cor, Electrochemical Society Electronics Division, Electrochemical Society Meeting y Society of Photo-optical Instrumentation Engineers., eds. High purity silicon VI: Proceedings of the Sixth International Symposium. Pennington, New Jersey: Electrochemical Society, 2000.

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International Symposium on High Purity Silicon (4th 1996 San Antonio, Tex.). Proceedings of the Fourth International Symposium on High Purity Silicon. Editado por Claeys Cor L y Electrochemical Society Electronics Division. Pennington, NJ: Electrochemical Society, 1996.

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Symposium F on Techniques and Challenges for 300 mm Silicon (1998 Strasbourg, France). Techniques and challenges for 300 mm silicon: Processing, characterization, modelling and equipment : proceedings of Symposium F on Techniques and Challenges for 300 mm Silicon of the E-MRS 1998 Spring Conference, Strasbourg, France, 16-19 June 1998. Amsterdam: Elsevier, 1999.

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IEEE SOS/SOI Technology Conference. (1988 St. Simons Island, Ga.). 1988 IEEE SOS/SOI Technology Workshop, October 3-5, 1988, Sea Palms Resort, St. Simons Island, Georgia, proceedings. [United States: s.n., 1988.

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Bullis, W. Murray. Semiconductor measurement technology: Evolution of silicon materials characterization : lessons learned for improved manufacturing. Gaithersburg, MD: U.S. Dept. of Commerce, National Institute of Standards and Technology, 1993.

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Capítulos de libros sobre el tema "Semiconductor wafers. Silicon Silicon Electrodiffusion"

1

Forget, B. C., D. Fournier y V. E. Gusev. "Nonlinear recombinations in photoreflectance characterization of silicon wafers". En Semiconductor Materials Analysis and Fabrication Process Control, 255–59. Elsevier, 1993. http://dx.doi.org/10.1016/b978-0-444-89908-8.50053-2.

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Beyer, M., K. Budde y W. Holzapfel. "Organic contamination of silicon wafers by buffered oxide etching". En Semiconductor Materials Analysis and Fabrication Process Control, 88–92. Elsevier, 1993. http://dx.doi.org/10.1016/b978-0-444-89908-8.50021-0.

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Garrido, B., J. A. Moreno, J. Samitier y J. R. Morante. "Accurate infrared spectroscopy analysis in back-side damaged silicon wafers". En Semiconductor Materials Analysis and Fabrication Process Control, 236–39. Elsevier, 1993. http://dx.doi.org/10.1016/b978-0-444-89908-8.50049-0.

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Stemmer, Michael. "Mapping of the local minority carrier diffusion length in silicon wafers". En Semiconductor Materials Analysis and Fabrication Process Control, 213–17. Elsevier, 1993. http://dx.doi.org/10.1016/b978-0-444-89908-8.50044-1.

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Mitani, K., S. Saisu y M. Katayama. "Influence of Surface Charges on Four-Point-Probe Resistivity Measurement for N-Type Silicon Epitaxial Wafers". En Control of Semiconductor Interfaces, 435–40. Elsevier, 1994. http://dx.doi.org/10.1016/b978-0-444-81889-8.50080-8.

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Suzuki, Eiichi y Yutaka Hayashi. "Evaluation of the minority carrier lifetime and diffusion coefficient of cast polycrystalline silicon wafers by the dual mercury probe method". En Semiconductor Materials Analysis and Fabrication Process Control, 218–21. Elsevier, 1993. http://dx.doi.org/10.1016/b978-0-444-89908-8.50045-3.

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Akhtar, Imtisal, Malik Abdul Rehman y Yongho Seo. "Measuring the Blind Holes: Three-Dimensional Imaging of through Silicon via Using High Aspect Ratio AFM Probe". En 21st Century Surface Science - a Handbook. IntechOpen, 2020. http://dx.doi.org/10.5772/intechopen.92739.

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Three-dimensional integration and stacking of semiconductor devices with high density, its compactness, miniaturization and vertical 3D stacking of nanoscale devices highlighted many challenging problems in the 3D parameter’s such as CD (critical dimension) measurement, depth measurement of via holes, internal morphology of through silicon via (TSV), etc. Current challenge in the high-density 3D semiconductor devices is to measure the depth of through silicon via (TSV) without destructing the sample; TSVs are used in 3D stacking devices to connect the wafers stacked vertically to reduce the wiring delay, power dissipation, and of course, the form factor in the integration system. Special probes and algorithms have been designed to measure 3D parameters like wall roughness, sidewall angle, but these are only limited to deep trench-like structures and cannot be applied to structures like via holes and protrusions. To address these problems, we have proposed an algorithm based nondestructive 3D Atomic Force Microscopy (AFM). Using the high aspect ratio (5, 10, 20, 25) multiwall carbon nanotubes (MWCNTs) AFM probe, the depth of holes up to 1 micron is faithfully obtained. In addition to this, internal topography, side walls, and location of via holes are obtained faithfully. This atomic force microscopy technique enables to 3D scan the features (of any shape) present above and below the surface.
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"7. Cleaning thresholds and process efficiency A systematic determination of cleaning thresholds in both DLC and SLC should provide key information for the application of laser cleaning, as it allows to predict the minimum particle size that ca n be removed and to judge which of the two processes DLC or SLC is more efficient. On the basis of our measurements this comparison ca n be done for the first time and for a large size interval of particles. Perhaps the most striking differenc e in the two laser cleaning methods is the dependence of the cleaning threshold fluence on particl e size. Whereas in SLC this threshold appeared to be universal, i.e. size- and material-independent for the investigated particles, in DLC we found in agreement with other authors a size dependent threshold, with smaller particles being harder to remove than larger ones. Fro m this it is obvious that SLC is a more efficient method for small particles, i.e. for particles smaller than about 400 nm in diameter (for particles larger than 400 nm see below ) which is the most interesting size regarding the cleaning of bare silicon wafers in the semiconductor industry. In addition, SLC is superior to DLC in the minimum particle size that could be cleaned from silicon wafers. Recalling that the current minimum line width in ICs is 13 0 nm, which means that particles of about 60-70 nm in size have to be removed, this is a key information on the quality of a cleaning method. The lower size limit of particles that could be remove d by DLC was found to be 110 nm, compared to 60 nm and an efficiency above 90% in SLC. Summarizing the above, SL C is superior to DLC due to three crucial characteristics: its universal cleaning threshold, its lower threshold fluences for the relevant particle sizes, and its capability of removing sub 100 nm-particles. 5.2. Consequences of cleaning mechanisms involved Although in DLC no particles smaller than 100 nm could be removed, at a first glance it seems to be the more appropriate method for larger particles as its cleaning thresholds are distinctly lower than th e universal SLC threshold. However, for a judgement of the perspectives of SLC and DLC it is not sufficient to solely determine and compare cleaning efficiency and laser cleaning threshold fluence. On the contrary, as our studies above show very clearly, this comparison must be put into perspective by taking a closer look at the cleaning mechanisms involved. The most important physical process not taken into account in traditional investigations and only recently [34, 35, 38-40] studied is the local substrate ablation due to the enhancement of the laser intensity in the near field of the particles. The first, and most obvious, consequence of field enhancement is a locally increased laser fluence underneath the particle, and hence a decrease in the incident laser fluence necessary for particle removal. At a first sight this looks like a positive effect, but obviously a locally enhanced laser intensity drastically lowers the threshold for surface damage, and indeed we did observe surface damage caused either by melting (small particles) or local substrate ablation (large particles)". En Surface Contamination and Cleaning, 338–39. CRC Press, 2003. http://dx.doi.org/10.1201/9789047403289-50.

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Actas de conferencias sobre el tema "Semiconductor wafers. Silicon Silicon Electrodiffusion"

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Pei, Z. J. y Alan Strasbaugh. "Fine Grinding of Silicon Wafers: Grinding Marks". En ASME 2002 International Mechanical Engineering Congress and Exposition. ASMEDC, 2002. http://dx.doi.org/10.1115/imece2002-33458.

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In order to ensure high quality chips with high yield, the base material, semiconductor wafers (over 90% are silicon), must have superior quality. It is critically important to develop new manufacturing processes that allow silicon wafer manufacturers to produce high quality wafers at a reasonably low cost. A newly patented technology—fine grinding of etched silicon wafers—has great potential to manufacture very flat silicon wafers more cost-effectively. This paper presents an investigation of grinding marks in fine grinding. The investigation covers (1) nature of grinding marks, (2) factors that have effects on grinding marks, and (3) approaches to reduce grinding marks. Varying chuck speed during grinding operation is shown to be a very effective approach to reduce grinding marks. Conclusions from this study have direct impacts to the silicon wafer industry.
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Darchuk, Sergey D. y Fiodor F. Sizov. "Oxygen concentration distribution determination in silicon wafers by semiconductor IR laser spectroscopy". En International Conference on Optical Diagnostics of Materials and Devices for Opto-, Micro-, and Quantum Electronics, editado por Sergey V. Svechnikov y Mikhail Y. Valakh. SPIE, 1998. http://dx.doi.org/10.1117/12.306260.

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Tricard, Marc, Paul R. Dumas, Don Golini y James T. Mooney. "Prime Silicon and Silicon-on-Insulator (SOI) Wafer Polishing With Magnetorheological Finishing (MRF)". En ASME 2003 International Mechanical Engineering Congress and Exposition. ASMEDC, 2003. http://dx.doi.org/10.1115/imece2003-42149.

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The December 2001 [1, 2] edition of the International Technology Roadmap for Semiconductors [3] (ITRS-2001) identifies several challenges for the manufacturing of silicon and silicon-on-insulator (SOI) wafers. For silicon, edge exclusion, site flatness and nanotopography1 requirements will become extremely challenging. For SOI, requirements for the control of the top silicon layer and its associated uniformity are pushing the limits of metrology. Keeping ± 5% tolerances on thicknesses, gradually decreasing from more than 100nm to less than 20nm for partially depleted devices (let alone from 30 to 3nm for fully depleted devices) is exceeding the capabilities of traditional chemo-mechanical-polishing (CMP) processes [5]. This paper will briefly describe magnetorheological finishing (MRF) and its suitability for prime silicon and SOI wafer polishing. Particular emphasis will be placed on MRF’s ability to improve the global flatness and the total thickness variation (TTV) on prime silicon wafers, and to reduce the nominal thickness of the top silicon layer, while improving thickness uniformity on SOI wafers. The paper will also touch upon the process qualification issues associated with the tight requirements of the semiconductor industry.
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Trujillo-Sevilla, J. M., J. M. Ramos-Rodriguez y J. Gaudestad. "High Speed Wafer Geometry on Silicon Wafers Using Wave Front Phase Imaging for Inline Metrology". En 2020 China Semiconductor Technology International Conference (CSTIC). IEEE, 2020. http://dx.doi.org/10.1109/cstic49141.2020.9282496.

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Violette, Lamoureux, Figarols Francois, Pic Nicolas y Vitrani Thomas. "Complementary metrology techniques to detect low levels of metallic contaminations on bare silicon wafers". En 2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC). IEEE, 2019. http://dx.doi.org/10.1109/asmc.2019.8791747.

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Koitzsch, M., D. Lewke, M. Schellenberger, L. Pfitzner, H. Ryssel y H. U. Zuhlke. "Enhancements in resizing single crystalline silicon wafers up to 450 mm by using thermal laser separation". En 2012 23rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC). IEEE, 2012. http://dx.doi.org/10.1109/asmc.2012.6212923.

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Zhang, J. M., J. G. Sun y Z. J. Pei. "Application of Laser Scattering on Detection of Subsurface Damage in Silicon Wafers". En ASME 2003 International Mechanical Engineering Congress and Exposition. ASMEDC, 2003. http://dx.doi.org/10.1115/imece2003-41105.

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Silicon is widely used in semiconductor industry. Over 90% of all semiconductor devices are manufactured upon silicon substrates (wafers). Many manufacturing processes are needed for the wafer preparation. In order to ensure high quality silicon wafers, the damaged layer induced by each manufacturing process must be reduced or eliminated by its subsequent processes. So, it is critical to assess subsurface damage (SSD). As a nondestructive measurement method, laser scattering is preliminarily applied to measure SSD in silicon wafers. Optical transmission properties of silicon wafer are measured first to make sure that silicon wafers have the appropriate optical transmission properties for laser scattering. Photomicrographs and scatter images are obtained on sample wafers with different depth of subsurface damage. The correlation between photomicrographs and scatter images is discussed. The results from this study show that laser scattering can potentially be applied to measure subsurface damage across whole silicon wafers.
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Biscarrat, J., R. Gwoziecki, Y. Baines, J. Buckley, C. Gillot, W. Vandendaele, G. Garnier, M. Charles y M. Plissonnier. "Performance enhancement of CMOS compatible 600V rated AlGaN/GaN Schottky diodes on 200mm silicon wafers". En 2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD). IEEE, 2018. http://dx.doi.org/10.1109/ispsd.2018.8393637.

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Zhang, X. H., Z. J. Pei y Graham R. Fisher. "Chemical Mechanical Polishing of Silicon Wafers: Finite Element Analysis of Wafer Flatness". En ASME 2005 International Mechanical Engineering Congress and Exposition. ASMEDC, 2005. http://dx.doi.org/10.1115/imece2005-80271.

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Silicon is the primary semiconductor material used to fabricate integrated circuits. The quality of microchips depends directly on the quality of silicon wafers. A series of processes are required to manufacture the high-quality silicon wafers. Chemical mechanical polishing is a necessary step to achieve the required wafer flatness. In this paper, a finite element analysis has been conducted to study the effects of influencing factors (including Young’s modulus and Poisson’s ratio of the polishing pad, thickness of the pad, and polishing pressure) on the wafer flatness.
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Koldyaev, V., M. C. Kryger, J. P. Changala, M. L. Alles, D. M. Fleetwood, R. D. Schrimpf y N. Tolk. "Rapid non-destructive detection of sub-surface Cu in silicon-on-insulator wafers by optical second harmonic generation". En 2015 26th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC). IEEE, 2015. http://dx.doi.org/10.1109/asmc.2015.7164473.

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