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Bibliografías temáticas / The Viterbi algorithm

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Literatura académica sobre el tema "The Viterbi algorithm"

Autor: Grafiati

Publicado: 4 de junio de 2021

Última modificación: 1 de febrero de 2022

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Tesis sobre el tema "The Viterbi algorithm"

1

Dobson, Jonathan M. "ASIC implementations of the Viterbi Algorithm." Thesis, University of Edinburgh, 1999. http://hdl.handle.net/1842/13669.

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The Viterbi Algorithm is a popular method for decoding convolutional codes, receiving signals in the presence of intersymbol-interference, and channel equalization. In 1981 the European Telecommunications Administration (CEPT) created the Groupe Special Mobile (GSM) Committee to devise a unified pan-European digital mobile telephone standard. The proposed GSM receiver structure brings together Viterbi decoding and equilization. This thesis presents three VLSI designs of the Viterbi Algorithm with specific attention paid to the use of such modules within a GSM receiver. The first design uses a technique known as redundant number systems to produce a high speed decoder. The second design uses complementary pass-transistor logic to produce a low-power channel equalizer. The third design is a low area serial equalizer. In describing the three designs, redundant number systems and complementary pass-transistor logic are examined. It is shown that while redundant number systems can offer significant speed advantages over twos complement binary, there are other representations that can perform equally well, if not better. It will also be shown that complementary pass-transistor logic can offer a small improvement for VLSI circuits in terms of power consumption.

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2

Dujari, Rajeev. "Parallel Viterbi search algorithm for speech recognition." Thesis, Massachusetts Institute of Technology, 1992. http://hdl.handle.net/1721.1/13111.

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3

Ju, Zilong. "Fast Viterbi Decoder Algorithms for Multi-Core System." Thesis, KTH, Signalbehandling, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-98779.

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In this thesis, fast Viterbi Decoder algorithms for a multi-core system are studied. New parallel Viterbi algorithms for decoding convolutional codes are proposed based on tail biting trellises. The performances of the new algorithms are first evaluated by MATLAB and then Eagle (E-UTRA algorithms for LTE) link level simulations where the optimal parameter settings are obtained based on various simulations. One of the algorithms is proposed for implementation in the product due to its good BLER performance and low implementation complexity. The new parallel algorithm is then implemented on target DSPs for Ericsson internal multi-core system to decode the PUSCH (Physical Uplink Shared Channel) CQI (Channel Quality Indicator) in LTE (Long Term Evolution). And the performance of the new algorithm in the real multi-core system is compared against the current implementation regarding both cycle and memory consumption. As a fast decoder, the proposed parallel Viterbi decoder is computationally efficient which reduces significantly the decoding latency and solves memory limitation problems on DSP.

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4

Yamazato, Takaya, Iwao Sasase, and Shinsaku Mori. "A New Viterbi Algorithm with Adaptive Path Reduction Method." IEICE, 1993. http://hdl.handle.net/2237/7839.

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5

Cui, Xiaoxiao. "MODIFIED VITERBI DECODING ALGORITHM FOR CIRCULAR TRELLIS-CODED MODULATION." Ohio University / OhioLINK, 2000. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1171649965.

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6

Werling, Brett W. "A VHDL Implementation of the Soft Output Viterbi Algorithm." International Foundation for Telemetering, 2010. http://hdl.handle.net/10150/604276.

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ITC/USA 2010 Conference Proceedings / The Forty-Sixth Annual International Telemetering Conference and Technical Exhibition / October 25-28, 2010 / Town and Country Resort & Convention Center, San Diego, California<br>In this paper we present a VHDL implementation of the soft output Viterbi algorithm (SOVA). We discuss the usefulness of the SOVA in a serially concatenated convolutional code (SCCC) system. We explore various hardware design decisions along with their implications. Finally, we compare the simulated performance of the hardware implementation to a software reference model over an additive white Gaussian noise (AWGN) channel for several bit widths and traceback window lengths.

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7

Bull, Tristan. "Implementation of the Viterbi Algorithm Using Functional Programming Languages." International Foundation for Telemetering, 2009. http://hdl.handle.net/10150/606012.

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ITC/USA 2009 Conference Proceedings / The Forty-Fifth Annual International Telemetering Conference and Technical Exhibition / October 26-29, 2009 / Riviera Hotel & Convention Center, Las Vegas, Nevada<br>In this paper, we present an implementation of the Viterbi algorithm using the functional programming language Haskell. We begin with a description of the functional implementation of the algorithm. Included are aspects of functional programming that must be considered when implementing the Viterbi algorithm as well as properties of Haskell that can be used to simplify or optimize the algorithm. Finally, we evaluate the performance of the Viterbi algorithm implemented in Haskell.

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8

Alam, Daniel. "Coded SOQPSK-TG Using the Soft Output Viterbi Algorithm." International Foundation for Telemetering, 2009. http://hdl.handle.net/10150/606121.

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ITC/USA 2009 Conference Proceedings / The Forty-Fifth Annual International Telemetering Conference and Technical Exhibition / October 26-29, 2009 / Riviera Hotel & Convention Center, Las Vegas, Nevada<br>In this paper we present a system-level description of a serially concatenated convolutional coding scheme for shaped offset quadrature phase shift keying, telemetry group (SOQPSK-TG). Our paper describes the operation of various system modules. In addition, implementation details and references for each module in the system are provided. The modified Soft Output Viterbi Algorithm (SOVA) is employed for decoding inner and outer convolutional codes. The modified SOVA possess strong performance and low-complexity cost. The comparison of the modified (SOVA) and Max-Log-maximum a posteriori (MAP) decoding algorithm is presented. The SOVA after a simple modification displays the same performance as Max-Log-MAP algorithm, which is demonstrated by the simulation results. The advantage of the simple implementation of the modified SOVA makes it superior to Max-Log-MAP for our purposes.

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9

Lavin, Christopher. "THE IMPLEMENTATION OF AN IRREGULAR VITERBI TRELLIS DECODER." International Foundation for Telemetering, 2007. http://hdl.handle.net/10150/604495.

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ITC/USA 2007 Conference Proceedings / The Forty-Third Annual International Telemetering Conference and Technical Exhibition / October 22-25, 2007 / Riviera Hotel & Convention Center, Las Vegas, Nevada<br>The Viterbi algorithm has uses for both the decoding of convolutional codes and the detection of signals distorted by intersymbol interference (ISI). The operation of these processes is characterized by a trellis. An ARTM Tier-1 space-time coded telemetry receiver required the use of an irregular Viterbi trellis decoder to solve the dual antenna problem. The nature of the solution requires the trellis to deviate from conventional trellis structure and become time-varying. This paper explores the architectural challenges of such a trellis and presents a solution using a modified systolic array allowing the trellis to be realized in hardware.

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10

Shanker, M. Ravi. "A parallel implementation of the A*-Viterbi Algorithm for speech recognition /." Thesis, McGill University, 1993. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=69682.

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The problem of speech recognition is one that lends itself to parallelization. A common method used for speech recognition is the Viterbi algorithm. Unfortunately, this method is computationally expensive for large vocabularies. A new two pass method has been proposed, using the Viterbi algorithm as the first pass and the A$ sp *$ algorithm as the second, making use of the results of the Viterbi algorithm. Both these algorithms can be made faster by parallelizing them.<br>This thesis report describes the design and implementation of a parallel version of these algorithms on a BBN Butterfly multi-processor machine, and it also presents the outcome of the parallelization. It was observed that the parallel version of the Viterbi algorithm ran 8 times faster than the sequential version. This was observed for the recognition of both short words and long words. The A$ sp *$ algorithm, however, displayed different behaviour for short words as compared to long words. With a short word, the parallel version of the A$ sp *$ algorithm ran slightly slower than the sequential version; for a long word, it ran considerably faster than the sequential version--it was observed to run as much as 150 times faster.<br>This thesis comments on the results thus obtained, and attempts to explain the behaviour of the different parallel implementations.

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