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Literatura académica sobre el tema "Threshold voltage monitor circuit"

Autor: Grafiati
Publicado: 4 de junio de 2021
Última modificación: 15 de febrero de 2022

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Artículos de revistas sobre el tema "Threshold voltage monitor circuit"

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Bai, Fan Gyan y Ming San Ouyang. "Based on LPC2388 Mine Microseismic Monitor". Advanced Materials Research 846-847 (noviembre de 2013): 531–34. http://dx.doi.org/10.4028/www.scientific.net/amr.846-847.531.

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A new type of mine microseismic monitoring is introduced. The microseismic signal by these downhole sensors collecting, through the differential amplification circuit and filter processing circuit, enhance the potential to voltage A/D conversion chip required. The conversion result is read by ARM controller. The controller processes those data using wavelet denoising, and uses the Ethernet control circuit using TCP/IP protocol transmitte themto the PC. On the trap circuit, Butterworth low-pass filter circuit, wavelet threshold denoising have been simulated, the experimental results basically reached the design requirements.
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Olmos, Alfredo, Fabricio Ferreira, Fernando Paixão Cortes, Fernando Chavez y Marcelo Soares Lubaszewski. "A 2-Transistor Sub-1V Low Power Temperature Compensated CMOS Voltage Reference: Design and Application". Journal of Integrated Circuits and Systems 10, n.º 2 (28 de diciembre de 2015): 74–80. http://dx.doi.org/10.29292/jics.v10i2.408.

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This paper presents the design and application of a CMOS sub-1V voltage reference using a 2-transistor Self-Cascode MOSFET (SCM) structure able to get low power consumption, temperature compensation, and small area. An efficient design procedure applied to this simple topology relying on NMOS transistors with different threshold voltages allows attaining large immunity against bias current and supply voltage variations. The two transistors can operate in weak, moderate, or strong inversion making the design flexible in terms of area and power consumption. Implemented in a > 0.18mm standard CMOS technology, the circuit provides a 400mV voltage reference with a variation of ±0.18% from -20°C to 75°C (or less than 15ppm/°C), operates from 3.6V down to 800mV while biased with a 5nA resistor-less PTAT current source that varies ±30% over PVT, and consumes less than 20nA with an area of 0.01mm2. The same concept was used to create a temperature compensated voltage drop with regard to a monitored power supply voltage but using a 2-PMOS SCM structure with transistors of different threshold voltages. These two circuits were adopted as part of a Power Management (PM) system for RFID tag applications. The PM includes a LDO voltage regulator and a low voltage detector that require both the voltage reference and the low voltage monitor. The LDO regulated output voltage and the trip-point of the voltage detector vary +/-5.5% and +/-3.3%, respectively, over temperature, without trimming.
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Zhang, Xi, Tianshi Wang y Bocheng Bao. "A Detection Circuit for Improving the Unloading Transient Performance of the COT Controller". Electronics 10, n.º 19 (23 de septiembre de 2021): 2333. http://dx.doi.org/10.3390/electronics10192333.

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Fast load transient response and high light-load efficiency are two key features of the constant on-time (COT) control technique that has been widely used in numerous applications, such as for voltage regulators and point-of-load converters. However, when load step-down occurs during an on-time interval, the COT controller cannot respond until the COT interval expires. This delay causes an additional output voltage overshoot, resulting in unloading transient performance limitation. To eliminate the delay and improve the unloading transient response of the COT controller, a load step-down detection circuit is proposed based on capacitor current COT (CC-COT) control. In the detection circuit, the load step-down is monitored by comparing the measured capacitor current with the preset threshold voltage. Once the load step-down is monitored, the on-time is promptly truncated and the switch is turned off. With the proposed detection circuit, the CC-COT-controlled buck converter can monitor the load step-down without any delay and obtain less output voltage overshoot when the load step-down occurs during the on-time interval. PSIM circuit simulations are employed to demonstrate the feasibility of the detection circuit.
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Mehta, Nandish y Bharadwaj Amrutur. "Dynamic Supply and Threshold Voltage Scaling for CMOS Digital Circuits Using In-Situ Power Monitor". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20, n.º 5 (mayo de 2012): 892–901. http://dx.doi.org/10.1109/tvlsi.2011.2132765.

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Pejovic, Milic. "The gamma-ray irradiation sensitivity and dosimetric information instability of RADFET dosimeter". Nuclear Technology and Radiation Protection 28, n.º 4 (2013): 415–21. http://dx.doi.org/10.2298/ntrp1304415p.

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The gamma-ray irradiation sensitivity to radiation dose range from 0.5 Gy to 5 Gy and post-irradiation annealing at room and elevated temperatures have been studied for p-channel metal-oxide-semiconductor field effect transistors (also known as radiation sensitive field effect transistors or pMOS dosimeters) with gate oxide thicknesses of 400 nm and 1 mm. The gate biases during the irradiation were 0 and 5 V and 5 V during the annealing. The radiation and the post-irradiation sensitivity were followed by measuring the threshold voltage shift, which was determined by using transfer characteristics in saturation and reader circuit characteristics. The dependence of threshold voltage shift DVT on absorbed radiation dose D and annealing time was assessed. The results show that there is a linear dependence between DVT and D during irradiation, so that the sensitivity can be defined as DVT/D for the investigated dose interval. The annealing of irradiated metal-oxide-semiconductor field effect transistors at different temperatures ranging from room temperature up to 150?C was performed to monitor the dosimetric information loss. The results indicated that the dosimeters information is saved up to 600 hours at room temperature, whereas the annealing at 150?C leads to the complete loss of dosimetric information in the same period of time. The mechanisms responsible for the threshold voltage shift during the irradiation and the later annealing have been discussed also.
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Wang, Xiaoli, Haonan Zhou y Yong Song. "Infrared Infusion Monitor Based on Data Dimensionality Reduction and Logistics Classifier". Processes 8, n.º 4 (7 de abril de 2020): 437. http://dx.doi.org/10.3390/pr8040437.

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This paper presents an infrared infusion monitoring method based on data dimensionality reduction and a logistics classifier. In today’s social environment, nurses with hospital infusion work are under excessive pressure. In order to improve the information level of the traditional medical process, hospitals have introduced a variety of infusion monitoring devices. The current infusion monitoring equipment mainly adopts the detection method of infrared liquid drop detection to realize non-contact measurements. However, a large number of experiments have found that the traditional infrared detection method has the problems of low voltage signal amplitude variation and low signal-to-noise ratio (SNR). Conventional threshold judgment or signal shaping cannot accurately judge whether droplets exist or not, and complex signal processing circuits can greatly increase the cost and power consumption of equipment. In order to solve these problems, this paper proposes a method for the accurate measurement of droplets without increasing the cost, that is, a method combining data drop and a logistics classifier. The dimensionalized data and time information are input into the logistics classifier to judge the drop landing. The test results show that this method can significantly improve the accuracy of droplet judgment without increasing the hardware cost.
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Burghard, R. A. y Y. A. El-Mansy. "Depletion transistor threshold voltage as a process monitor". IEEE Transactions on Electron Devices 34, n.º 4 (abril de 1987): 940–42. http://dx.doi.org/10.1109/t-ed.1987.23023.

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Sahafi, A., J. Sobhi y Z. D. Koozekanani. "Pico Watt sub-threshold CMOS voltage reference circuit". IEICE Electronics Express 10, n.º 4 (2013): 20120945. http://dx.doi.org/10.1587/elex.10.20120945.

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Hu, Zhi Cheng, Zhi Hua Ning y Le Nian He. "A Low Temperature Coefficient, High Voltage Detection Circuit Used in Power over Ethernet". Advanced Materials Research 588-589 (noviembre de 2012): 839–42. http://dx.doi.org/10.4028/www.scientific.net/amr.588-589.839.

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A low temperature coefficient, high voltage detection circuit used in Power over Ethernet is proposed. This circuit realizes the detection comparison without utilizing an extra voltage reference circuit and comparator while the temperature coefficient of the threshold voltage is as low as that of a regular bandgap reference. The proposed detection circuit is implemented in CSMC 0.5μm 60V BCD process, Cadence Spectre simulation results show that the temperature coefficient of the threshold voltage is 66.5 ppm/°C over the temperature range of -40°C to 125°C, and the maximum variation of the threshold voltage is 2.7% under all corners.
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MANHAS, PARSHOTAM S. y K. PAL. "REALIZATION OF LOW-VOLTAGE DIFFERENTIAL VOLTAGE CURRENT CONVEYOR". Journal of Circuits, Systems and Computers 21, n.º 04 (junio de 2012): 1250031. http://dx.doi.org/10.1142/s0218126612500314.

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This paper presents floating gate MOSFET (FGMOS)-based second generation differential voltage current conveyor (DVCCII) at low voltage levels. In analog circuit design, the FGMOS transistors are very often used in low voltage circuits, where the reduction obtained in the transistor apparent threshold voltage is of great importance. The given circuit provides very high input impedance at its Y-terminals, low output impedance at X-terminal and high impedance at Z-terminals and consumes less power. This circuit is a powerful building block, especially for applications demanding differential or floating inputs. The circuit behavior has been verified using PSpice simulations for 0.5 μm technology and indicates the excellent performance.
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Tesis sobre el tema "Threshold voltage monitor circuit"

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Caicedo, Jhon Alexander Gomez. "CMOS low-power threshold voltage monitors circuits and applications". reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2016. http://hdl.handle.net/10183/144080.

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Um monitor de tensão de limiar (VT0) é um circuito que, idealmente, entrega o valor do VT0 como uma tensão na saída, para uma determinada faixa de temperatura, sem a necessidade de polarização externa, configurações paramétricas, ajuste de curvas ou qualquer cálculo subsequente. Estes circuitos podem ser usados em sensores de temperatura, referências de tensão e corrente, dosímetros de radiação e outras aplicações, uma vez que a dependência do VT0 nas condições de operação é um aspecto bem modelado. Além disso, estes circuitos podem ser utilizados para monitoramento de processos de fabricação e para compensação da variabilidade do processo, uma vez que o VT0 é um parâmetro chave para o comportamento do transistor e sua modelagem. Nesta tese, são apresentadas três novas topologias de circuitos, duas são monitores de VT0 NMOS e a terceira é um monitor de VT0 PMOS. As três estruturas são topologias de circuito auto-polarizadas que não utilizam resistências, e apresentam alta rejeição a variações na alimentação, baixa sensibilidade de Linea, e permitem a extração direta da tensão de limiar para grandes intervalos de temperatura e de tensão de alimentação, com pequeno erro. Sua metodologia de projeto é baseada no modelo unificado controlado por corrente (UICM), um modelo MOSFET que é contínuo, desde o nível de inversão fraca a forte e para as regiões de operação de triodo e saturação. Os circuitos ocupam uma pequena área de silício, consomem apenas dezenas de nanowatts, e podem ser implementados em qualquer processo padrão CMOS digital, uma vez que só utilizam transistores MOS (não precisa de nenhum resistor). Os monitores de VT0 são utilizados em diferentes aplicações, a fim de investigar a sua funcionalidade e comportamento como parte de um sistema. As aplicações variam de uma tensão de referência, que apresenta um desempenho comparável ao estado da arte, para uma configuração que permite obter uma menor variabilidade com processo na saída de um circuito auto-polarizado que gera um tensão CTAT. Além disso, explorando a capacidade de funcionar como um gerador de corrente específica (ISQ) que os monitores de VT0 aqui apresentados oferecem, introduz-se um novo circuito auto-polarizado que gera um tensão CTAT, que é menos sensível a variações de processo, e pode ser usado em referências de tensão band-gap.
A threshold voltage (VT0) monitor is a circuit that ideally delivers the estimated VT0 value as a voltage at its output, for a given temperature range, without external biases, parametric setups, curve fitting or any subsequent calculation. It can be used in temperature sensors, voltage and current references, radiation dosimeters and other applications since the MOSFET VT0 dependence on the operation conditions is a very well modeled aspect. Also, it can be used for fabrication process monitoring and process variability compensation, since VT0 is a key parameter for the transistor behavior and modeling. In this thesis, we present three novel circuit topologies, two of them being NMOS VT0 monitors and the last one being a PMOS VT0 monitor. The three structures are resistorless self-biased circuit topologies that present high power supply rejection, low line sensitivity, and allow the direct extraction of the threshold voltage for wide temperature and power supply voltage ranges, with small error. Its design methodology is based on the Unified Current Control Model (UICM), a MOSFET model that is continuous from weak to strong inversion and from triode to saturation regions. The circuits occupy small silicon area, consume just tens of nanoWatts, and can be implemented in any standard digital CMOS process, since they only use MOS transistors (does not need any resistor). The VT0 monitors are used in different applications in order to prove their functionality, and behavior as part of a system. The applications vary from a reference voltage, that presents performance comparable with state-of-the-art works, to a configuration that allows to obtain a lower process variability, in the output of a self-biased circuit that generates a complementary to the absolute temperature (CTAT) voltage. In addition, exploiting the ability to operate as an specific current (ISQ) generator, that the VT0 monitors presented here offer, we introduced a new self-biased circuit that produces a CTAT voltage and is less sensitive to process variations, and can be used in band-gap voltage references.
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Gomez, gomez Ricardo. "Design of innovative solutions to improve the variability and reliability of CMOS circuits on thin film technologies". Thesis, Université Grenoble Alpes, 2020. http://www.theses.fr/2020GRALT023.

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La sensibilité accrue aux variations des procedés de fabrication, de tension, de température et de vieillissement (PVTA) dans les nœuds technologiques avancés d'integration est responsable d'une dégradation significative des spécifications des circuits integrés lors de la fabrication à grand volume. Celle-ci est devenue une préoccupation croissante dans la conception de circuits numériques, qui doit faire face aux exigences de plus en plus strictes des applications modernes en termes d'efficacité énergétique, de fiabilité et de sécurité. Dans ce travail de thèse, les techniques de surveillance de timing intégrée et de compensation sont explorées pour répondre efficacement à ces exigences contradictoires. Dans ce travail de thèse, les techniques proposées ont été étudiés séparément puis combinées dans 3 démonstrateurs SoC numériques fabriqués en technologie 28nm FD-SOI CMOS, dont l'un a été mesuré au moment de la rédaction de ce manuscrit.La surveillance de timing intégrée est proposée comme solution de conception pour permettre la compensation des variations PVTA, la surveillance de la sécurité en operation et la protection contre les attaques hardware en timing. Les moniteurs de timing de l'état de l'art ont été évalués dans la perspective d'une intégration dans des produits industriels, ce qui privilégie des caractéristiques telles que la reusabilité et les faibles coûts d'intégration. Les avantages identifiés de la surveillance de timing de registre à registre ont conduit à la mise en œuvre d'un circuit témoin reconfigurable (Tunable Replica Circuit en langue anglaise) avec une sensibilité de 3 mV/bit en 28nm FD-SOI CMOS, qui démontre un suivi rapide et précis des variations PVTA d'un SoC basé sur un ARM Cortex-R4F à travers des corners lent / typique / rapide, une plage de tension 0.5/1.2 V, une gamme de temperature -40/150°C, et de vieillissement jusqu'a fin de vie. Enfin, ce travail propose un nouveau moniteur de timing qui permet de surmonter les faiblesses des solutions existantes, en obtenant simultanément la reutilisabilité élevée et la large plage de surveillance des oscillateurs en anneau et l'acquisition rapide et précise des circuits témoins reconfigurables.L'exploration des techniques d'adaptation et de compensation commence par la détermination de leur champ d'application dans les produits industriels: l'amélioration des pires cas qui définissent les limites de spécifications du produit lors de la fabrication à grand volume. Dans cette perspective, la région d'application optimale des techniques de voltage scaling et de body biasing a été déterminée et leur impact sur les pires cas des SoC numériques a été évalué. Enfin, ces travaux montrent comment la surconsommation induite par l'application séparée de voltage scaling ou body biasing peut être atténuée par la combinaison des deux, en particulier dans les circuits avec une variété de points de performance opérationnelle (OPPs).Les avantages des techniques proposées ont été démontrés dans un SoC numérique qui optimise son énergie à travers d'une largeur de fréquence de 11X en combinant le voltage scaling adaptatif, body biasing adaptatif et le bias-in-memory-array avec un tunable replica circuit pour la sécurité, la régulation de puissance intégrée et la compensation. Grâce à l'application de ces techniques, le circuit proposé permet de surmonter les limites précédemment signalées et démontre une amélioration des performances de 21X, une Vmin inférieure de 120 mV et une durée de vie de 8X, pour les OPP de faible puissance, de moyenne et de haute performance respectivement.Les études présentées ici ont été incluses dans plusieurs chapitres d'un livre scientifique qui sera publié cette année. En outre, elles ont contribué à une nouvelle plateforme de technologie et de conception. Enfin, 3 publications dans des conférences de l'IEEE et 3 demandes de brevet ont résulté de ce travail de thèse
The increased sensitivity to Process, Voltage, Temperature, and Aging (PVTA) variations in scaled integrated circuits' technology nodes is responsible for a significant degradation in the products' specifications during high volume manufacturing. This has become a growing concern in digital circuit design, which has to cope with the increasingly stringent requirements of modern applications in terms of energy efficiency, reliability, and safety. In this thesis work, embedded timing monitoring and compensation techniques are explored to efficiently address these conflicting requirements. The proposed techniques are studied separately and then combined in 3 digital SoC demonstrators manufactured in 28nm FD-SOI CMOS technology, one of which has been measured at the time of this manuscript's writing.Embedded timing monitoring is proposed as a design solution to enable PVTA compensation, in-field safety monitoring and security protection against hardware timing attacks. The state-of-the-art timing monitors are evaluated from the perspective of an integration into industrial products, emphasizing features such as high reusability and low integration costs. The identified advantages of register-to-register timing monitoring have led to the implementation of a 3mV/bit tunable replica circuit in 28nm FD-SOI CMOS, which demonstrates a fast and accurate PVTA tracking of an ARM Cortex-R4F based SoC across slow/typical/fast process, 0.5/1.2V, -40/150ºC, and End Of Life (EOL) aging. Finally, this work proposes a novel timing monitor that overcomes the weaknesses of existing solutions, simultaneously achieving the high reusability and wide monitoring range of ring oscillators and the fast and accurate timing acquisition of tunable replica circuits.The exploration of adaptive and compensation techniques begins with the determination of their application scope in industrial designs: the improvement of the worst-case limiting corners that set the product's specifications during high volume manufacturing. Following this perspective, the optimal region of application of voltage scaling and body biasing techniques has been determined and their impact on the worst-case specifications of digital SoCs has been assessed. Finally, this work demonstrates how the power overhead induced by the separate application of voltage scaling or body biasing can be mitigated through the combination of both, specially in circuits with a variety of Operational Performance Points (OPPs).The benefits of the proposed techniques have been demonstrated in a digital SoC that optimizes its energy across 11X frequency-wide OPPs by combining adaptive voltage scaling, adaptive body biasing, and bias-in-memory-array with a tunable replica circuit for safety, embedded power regulation and compensation. Through the application of these techniques the proposed design overcomes previously reported limitations and demonstrates an improvement by 21X performance, 120mV lower Vmin, and 8X lifetime, the low-power, mid-, and high-performance OPPs respectively.The studies reported here have been included in several chapters of a scientific book to be published this year. Furthermore, they have contributed to a new technology and design platform. Finally, 3 IEEE conference publications and 3 patent applications have resulted from this thesis' work
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3

Arpin, Louis. "Conception et intégration d'une architecture numérique pour l'ASIC LabPET[indice supérieur TM] II, un circuit de lecture d'une matrice de détection TEP de 64 pixels". Mémoire, Université de Sherbrooke, 2012. http://hdl.handle.net/11143/6148.

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Des développements technologiques récents concernant les photodiodes à effet avalanche (PDA) ont mené à la conception et la fabrication d'un tout nouveau module de détection de radiation TEP (tomographie d'émission par positrons) destiné à l'imagerie moléculaire préclinique. Il est basé sur une matrice de 8 par 8 scintillateurs LYSO (ortho-silicate de lutétium dopé au cérium, cerium-doped lutetium yttrium orthosilicate ) individuellement couplés aux pixels de deux matrices monolithiques de 4 par 8 PDA. Cette avancée, pouvant amener la résolution spatiale d'un scanner à passer sous la barrière du mm, exige la conception d'un tout nouveau système d'acquisition de données. En effet, il faut adapter le système de lecture individuelle de chacun des pixels du bloc de détection de façon à satisfaire la multiplication par ~8, relativement à une version antérieure (le LabPET[indice supérieur TM] I), de la densité de pixels du futur scanner LabPET[indice supérieur TM] II. Conséquemment, le traitement de signal numérique ne peut être exclusivement embarqué dans les matrices de portes logiques programmable (field-programmable gate array , FPGA) du système d'acquisition, en considérant les aspects monétaires, d'espace occupé et de puissance consommée de l'ensemble du projet LabPET[indice supérieur TM] II. De façon à s'adapter à cette nouvelle réalité, un nouveau circuit intégré à application spécifique (application specific integrated circuit, ASIC) à signaux mixtes avec 64 canaux d'acquisition, fabriqué avec la technologie TSMC CMOS 0,18 [micromètre], a été conçu. L'ASIC utilise la méthode de temps au-dessus d'un seuil (time over threshold , ToT), déjà implantée dans des applications de physique des hautes-énergies, de manière à extraire numériquement l'information relative à un rayonnement interagissant avec la matrice de détection (l'énergie, le temps et le numéro de pixel de l'événement). Dans le cadre de ce projet, une architecture complexe de machines à états-finis, cadencée par une horloge de 100 MHz, a été implantée et elle permet à l'ASIC d'identifier le taux anticipé de 3 000 événements par seconde par canal. Ceci est réalisé en calculant en temps réel le paramètre ToT tout en assurant la calibration adéquate de chacune des chaînes d'acquisition. Le circuit intégré peut caractériser jusqu'à 2 Mévénements/s malgré son unique lien différentiel à bas voltage (low-voltage differential signaling, LVDS) de transfert de données et consomme environ 600 mW. L'ASIC a été développé en suivant un processus de conception de circuits intégrés à signaux mixtes. Il permet notamment de minimiser et de vérifier l'impact des indésirables effets parasites sur la circuiterie analogique et numérique de l'ensemble avant que les dessins de masques ne soient envoyés vers la fonderie pour fabriquer le circuit désiré.
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Gillardin, Gérard. "Mise au point d'un appareillage de photoluminescence a haute resolution spatiale : application a l'etude des semiconducteurs et dispositifs electroniques iii-v". Clermont-Ferrand 2, 1988. http://www.theses.fr/1988CLF2D216.

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Description du dispositif permettant d'analyser des plaques de 2**(") de diametre a 1ok, avec de hautes resolutions laterales (20 et 1mu m), eventuellement a diverses energies. Realisation de cartographies a 300 et 10k: tres bonne correlation entre intensite de photoluminescence et defauts cristallins et chimiques; correspondance avec des mesures de resistivite electrique. Mise au point d'une procedure de qualification de l'homogeneite microscopique de gaas semi-isolant. Possibilite de prevoir la dispersion des tensions de seuil de transistors fet d'apres l'analyse du support de defaut, donc de classer et choisir les supports pour la realisation de circuits integres
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5

Lin, Po Jen y 林柏仁. "High Energy Efficiency Near-Threshold Voltage Arithmetic Circuit Design". Thesis, 2015. http://ndltd.ncl.edu.tw/handle/djfgc2.

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Liu, Sheng-Che y 劉聖哲. "Low-Voltage Circuit Design Using PD SOI Dynamic-Threshold Voltage MOS (DTMOS) Techniques". Thesis, 2000. http://ndltd.ncl.edu.tw/handle/54800027175988214419.

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碩士
國立臺灣大學
電機工程學研究所
88
This thesis reports two low-voltage low-power circuits which are designed by using PD SOI DTMOS techniques. In chapter 2, this thesis introduced a novel 0.7V two-port 6T SRAM memory cell structure with single-bit-line simultaneous read-and-write access (SBLSRWA) capability using partially-depleted SOI CMOS dynamic-threshold techniques. With an innovative approach by connecting the body terminal for an NMOS device in the latch and the write access pass transistor to write word line, this 6T memory cell can be used to provides SBLSRWA capability for 0.7V two-port SOI CMOS cache memory. In chapter 3, this thesis introduced a novel low-voltage content addressable memory (CAM) cell structure using partially-depleted SOI CMOS dynamic-threshold techniques. With a unique structure by dynamically controlling the bodies of transistors that compose XOR portion of CAM cell via two auxiliary transistors, this CAM cell can be used to provide faster compare capability for low voltage range SOI CMOS CAM applications.
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Liu, Yi-Ting y 劉怡婷. "Voltage Scalable Switched Capacitor DC-DC Converter for Near-Threshold Voltage Integrated Circuit". Thesis, 2014. http://ndltd.ncl.edu.tw/handle/cn5c3d.

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碩士
國立交通大學
電機工程學系
102
This thesis proposes a DC-DC converter operation at 0.5 V. The circuit consists of four parts: a comparator, a digital control circuit, a switched capacitor and a digital circuit under test (DUT). The digital control circuit take the comparator output to control the switched capacitor operation to achieve the target voltage according to the reference voltage. It’s 2-phase interleaved converter can be configured into three topologies, which supports the output voltages of 0.25-0.45 V from the 0.5 V input supply, it has an efficiency between 59-79% for the load current of 100 µA. This converter is designed with all digital control without any static power consumption. At the load of 0.45 V and 100 µA, the switched capacitor consumes 57 µW. Among them, 45 µW is for the DUT with an efficiency of 79 %. The comparator and the digital control consume only 2 µW under lowest load power. It can be applied to implantable biomedical chip with low power consumption circuits. This chip is fabricated in TSMC GUTM 90 nm CMOS process, with high efficiency. The chip area is 1mm × 1mm.
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"Novel dual-threshold voltage FinFETs for circuit design and optimization". Thesis, 2011. http://hdl.handle.net/1911/70416.

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A great research effort has been invested on finding alternatives to CMOS that have better process variation and subthreshold leakage. From possible candidates, FinFET is the most compatible with respect to CMOS and it has shown promising leakage and speed performance. This thesis introduces basic characteristics of FinFETs and the effects of FinFET physical parameters on their performance are explained quantitatively. I show how dual- V th independent-gate FinFETs can be fabricated by optimizing their physical parameters. Optimum values for these physical parameters are derived using the physics-based University of Florida SPICE model for double-gate devices, and the optimized FinFETs are simulated and validated using Sentaurus TCAD simulations. Dual-14, FinFETs with independent gates enable series and parallel merge transformations in logic gates, realizing compact low power alternative gates with competitive performance and reduced input capacitance in comparison to conventional FinFET gates. Furthermore, they also enable the design of a new class of compact logic gates with higher expressive power and flexibility than CMOS gates. Synthesis results for 16 benchmark circuits from the ISCAS and OpenSPARC suites indicate that on average at 2GHz and 75°C, the library that contains the novel gates reduces total power and the number of fins by 36% and 37% respectively, over a conventional library that does not have novel gates in the 32nm technology.
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Lin, Geng-Cing y 林耕慶. "Device Threshold Voltage Measurement Circuit of Nano-scale CMOS SRAM". Thesis, 2011. http://ndltd.ncl.edu.tw/handle/60550065200696051283.

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碩士
國立交通大學
電子研究所
100
Variation issue is one of the key design factors for robust current VLSI systems, and this kind of issue will affect the device threshold voltage (VTH) value. However, the VTH value is still associated with the device performance, stability and reliability, then when we talk about the variation issue that the VTH is the important indicator to reflect this phenomenon. So we want to create a measurement structure that can measure the device threshold voltage, then we can collect the voltage data to realize how the variation issue will affect this testing chip. We present an all-digital bit transistor characterization scheme for CMOS 6T SRAM array. The scheme employs an on-chip operational amplifier feedback loop to measure the individual threshold voltage (VTH) of 6T SRAM bit cell transistors (holding PMOS, pull-down NMOS, and access NMOS) in SRAM cell array environment. The measured voltage is converted to frequency with dual VCO and counter based digital read-out to facilitate data extraction, processing, and statistical analysis. A 512Kb test chip is implemented in 55nm 1P10M Standard Performance (SP) CMOS technology. Monte Carlo simulations indicate that the accuracy of the VTH measurement scheme is about 2-7mV at TT corner across temperature range from 85oC to -45oC, and post-layout simulations show the resolution of the digital read-out scheme is < 0.2mV per bit.
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Hsu, Chih Wei y 徐志維. "Hardware Sharing Near Threshold Voltage Carry Select Adder Circuit Design". Thesis, 2015. http://ndltd.ncl.edu.tw/handle/q78uyy.

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Libros sobre el tema "Threshold voltage monitor circuit"

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Discrete Circuit Optimization Library Based Gate Sizing And Threshold Voltage Assignment. Now Publishers, 2012.

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Capítulos de libros sobre el tema "Threshold voltage monitor circuit"

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Islam, Mahfuzul y Hidetoshi Onodera. "Monitor Circuits for Cross-Layer Resiliency". En Dependable Embedded Systems, 385–407. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-52017-5_16.

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AbstractCross-layer resiliency has become a critical deciding factor for any successful product. This chapter focuses on monitor circuits that are essential in realizing the cross-layer resiliency. The role of monitor circuits is to establish a bridge between the hardware and other layers by providing information about the devices and the operating environment in run-time. This chapter explores delay-based monitor circuits for design automation with the existing cell-based design methodology. The chapter discusses several design techniques to monitor parameters of threshold voltage, temperature, leakage current, critical delay, and aging. The chapter then demonstrates a reconfigurable architecture to monitor multiple parameters with small area footprint. Finally, an extraction methodology of physical parameters is discussed for model-hardware correlation. Utilizing the cell-based design flow, delay-based monitors can be placed inside the target digital circuit and thus a better correlation between monitor and target circuit behavior can be realized.
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Gebregiorgis, Anteneh, Rajendra Bishnoi y Mehdi B. Tahoori. "Reliability Analysis and Mitigation of Near-Threshold Voltage (NTC) Caches". En Dependable Embedded Systems, 303–34. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-52017-5_13.

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AbstractNear-threshold computing (NTC) has significant role in reducing the energy consumption of modern very large-scale integrated circuits designs. However, NTC designs suffer from functional failures and performance loss. Understanding the characteristics of the functional failures and variability effects is of decisive importance in order to mitigate them, and get the utmost NTC benefits. This chapter presents a comprehensive cross-layer reliability analysis framework to assess the effect of soft error, aging, and process variation in the operation of near-threshold voltage caches. The objective is to quantify the reliability of different SRAM designs, evaluate voltage scaling potential of caches, and to find a reliability-performance optimal cache organization for an NTC microprocessor. In this chapter, the soft error rate (SER) and static noise margin (SNM) of 6T and 8T SRAM cells and their dependencies on aging and process variation are investigated by considering device, circuit, and architecture-level analysis.
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Dasgupta, Rituparna, Dipankar Saha, Jagannath Samanta, Sayan Chatterjee y Chandan Kumar Sarkar. "Implementation of a New Offset Generator Block for the Low-Voltage, Low-Power Self Biased Threshold Voltage Extractor Circuit". En Progress in VLSI Design and Test, 156–65. Berlin, Heidelberg: Springer Berlin Heidelberg, 2012. http://dx.doi.org/10.1007/978-3-642-31494-0_18.

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"Supply and Threshold Voltage Scaling Techniques". En Multi-Voltage CMOS Circuit Design, 45–84. Chichester, UK: John Wiley & Sons, Ltd, 2006. http://dx.doi.org/10.1002/0470033371.ch3.

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"Sleep Switch Dual Threshold Voltage Domino Logic". En Multi-Voltage CMOS Circuit Design, 187–204. Chichester, UK: John Wiley & Sons, Ltd, 2006. http://dx.doi.org/10.1002/0470033371.ch11.

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"Domino Logic with Variable Threshold Voltage Keeper". En Multi-Voltage CMOS Circuit Design, 147–70. Chichester, UK: John Wiley & Sons, Ltd, 2006. http://dx.doi.org/10.1002/0470033371.ch9.

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"Self Compensation of Threshold Voltage Shift". En Circuit Design Techniques for Non-Crystalline Semiconductors, 165–94. CRC Press, 2012. http://dx.doi.org/10.1201/b12683-16.

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"Modeling Threshold Voltage Shift for Circuit Design". En Circuit Design Techniques for Non-Crystalline Semiconductors, 93–100. CRC Press, 2012. http://dx.doi.org/10.1201/b12683-9.

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"Appendix — Derivation of the Threshold Voltage Shift Model". En Circuit Design Techniques for Non-Crystalline Semiconductors, 217–19. CRC Press, 2012. http://dx.doi.org/10.1201/b12683-19.

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Daoud, Houda, Dalila Laouej, Jihene Mallek y Mourad Loulou. "Analog Integrated Circuit Optimization". En Advances in Systems Analysis, Software Engineering, and High Performance Computing, 95–130. IGI Global, 2020. http://dx.doi.org/10.4018/978-1-7998-1718-5.ch003.

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This chapter presents a novel telescopic operational transconductance amplifier (OTA) using the bulk-driven MOS technique. This circuit is optimized for ultra-low power applications such as biomedical devices. The proposed the bulk-driven fully differential telescopic OTA with very low threshold voltages is designed under ±0.9V supply voltage. Thanks to the particle swarm optimization (PSO) algorithm, the circuit achieves high performances. The OTA simulation results present a DC gain of 63.6dB, a GBW of 2.8MHz, a phase margin (PM) of 55.8degrees and an input referred noise of 265.3nV/√Hz for a low bias current of 52nA.
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Actas de conferencias sobre el tema "Threshold voltage monitor circuit"

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C., Jhon A. Gomez, Hamilton Klimach, Eric Fabris y Oscar E. Mattia. "High PSRR Nano-Watt MOS-Only Threshold Voltage Monitor Circuit". En SBCCI '15: 28th Symposium on Integrated Circuits and Systems Design. New York, NY, USA: ACM, 2015. http://dx.doi.org/10.1145/2800986.2801009.

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Mattia, Oscar E., Hamilton Klimach, Sergio Bampi y Marcio Schneider. "0.7 V supply self-biased nanoWatt MOS-only threshold voltage monitor". En 2015 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2015. http://dx.doi.org/10.1109/iscas.2015.7168679.

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Wilcox, Bryan y Harry Dankowicz. "Design of Limit-Switch Sensors Based on Discontinuity-Induced Nonlinearities". En ASME 2009 International Design Engineering Technical Conferences and Computers and Information in Engineering Conference. ASMEDC, 2009. http://dx.doi.org/10.1115/detc2009-86560.

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Limit-switch sensors are input-output devices that switch operating state in reaction to the crossing of a threshold value of their input. These are used to monitor and control critical values of temperature, voltage, pressure, etc. in both consumer and industrial settings. This paper argues for exploiting nonsmooth fold bifurcations in the design of ultrafast and robust, resettable, electromechanical limit switches. Specifically, the discussion emphasizes the dramatic changes in system response associated with the onset of near-grazing, low-velocity contact in vibro-impacting systems. These include rapid transient dynamics away from a pre-grazing, periodic, steady-state trajectory following the onset of impacts and post-grazing steady-state trajectories with distinctly different amplitude and frequency content. The results reported here include an experimental and computational verification of the ultrafast transient growth rates that show a significant potential for dramatic improvement in sensor performance. Moreover, two novel candidate sensor designs are discussed that rely on the post-grazing response characteristics for device function. In the first instance, transduction of a change in the response periodicity following grazing in a mechanical device is detected in a coupled electromagnetic circuit. In the second instance, a snap-through post-grazing response forms the operating principle of a capacitively-driven circuit protection device.
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Feldengut, Tobias, Rainer Kokozinski y Stephan Kolnsberg. "A UHF voltage multiplier circuit using a threshold-voltage cancellation technique". En 2009 Ph.D. Research in Microelectronics and Electronics (PRIME). IEEE, 2009. http://dx.doi.org/10.1109/rme.2009.5201303.

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Nirmala, Ithihasa Reddy, Deepak Vontela, Swaroop Ghosh y Anirudh Iyengar. "A novel threshold voltage defined switch for circuit camouflaging". En 2016 IEEE European Test Symposium (ETS). IEEE, 2016. http://dx.doi.org/10.1109/ets.2016.7519286.

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Pham, Cong-Kha. "CMOS Schmitt Trigger Circuit with Controllable Hysteresis Using Logical Threshold Voltage Control Circuit". En 6th IEEE/ACIS International Conference on Computer and Information Science (ICIS 2007). IEEE, 2007. http://dx.doi.org/10.1109/icis.2007.76.

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Gao, Shan, Junning Chen, Daoming Ke y Qi Liu. "Temperature Characteristics for Threshold Voltage of HV LDMOS". En 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings. IEEE, 2006. http://dx.doi.org/10.1109/icsict.2006.306115.

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Guan, Xiaofei, Yong Huang, Liwen Zhang, Yuehua Li, Xinlin Wang y Hongyu He. "A Pixel Circuit with Compensation for Threshold Voltage and Current-Resistance Voltage Drop". En 2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC). IEEE, 2019. http://dx.doi.org/10.1109/edssc.2019.8754441.

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I-Chyn Wey, Po-Jen Lin, Bing-Chen Wu, Chien-Chang Peng y Pin-Hsi Lin. "Near-threshold-voltage circuit design: The design challenges and chances". En 2014 International SoC Design Conference (ISOCC). IEEE, 2014. http://dx.doi.org/10.1109/isocc.2014.7087666.

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Toledo, Luis Eduardo, Pablo Antonio Petrashin, Walter Jose Lancioni y Carlos Daniel Vazquez. "Threshold voltage extraction circuit for low voltage CMOS design using basic long-channel MOSFET". En 2015 IEEE 6th Latin American Symposium on Circuits & Systems (LASCAS 2015). IEEE, 2015. http://dx.doi.org/10.1109/lascas.2015.7250467.

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