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Tesi sul tema "Application specific instruction-set processor (ASIP)"

Autore: Grafiati
Pubblicato: 4 giugno 2021
Ultima modifica: 25 luglio 2025

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1

Radhakrishnan, Swarnalatha Computer Science &amp Engineering Faculty of Engineering UNSW. "Heterogeneous multi-pipeline application specific instruction-set processor design and implementation." Awarded by:University of New South Wales. Computer Science and Engineering, 2006. http://handle.unsw.edu.au/1959.4/29161.

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Abstract (sommario):
Embedded systems are becoming ubiquitous, primarily due to the fast evolution of digital electronic devices. The design of modern embedded systems requires systems to exhibit, high performance and reliability, yet have short design time and low cost. Application Specific Instruction set processors (ASIPs) are widely used in embedded system since they are economical to use, flexible, and reusable (thus saves design time). During the last decade research work on ASIPs have been carried out in mainly for single pipelined processors. Improving performance in processors is possible by exploring
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2

Packiaraj, Vivek. "Study, Design and Implementation of an Application Specific Instruction Set Processor for a Specific DSP Task." Thesis, Linköping University, Electronics System, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-52314.

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Abstract (sommario):
<p>There is a lot of literature already available describing well-structured approach for embeddeddesign and implementation of Application Specific Integrated Processor (ASIP) micro processorcore.</p><p>This concept features hardware structured approach for implementation of processor core fromminimal instruction set, encoding standards, hardware mapping, and micro architecture design,coding conventions, RTL,verification and burning into a FPGA. The goal is to design an ASIPprocessor core (Micro architecture design and RTL) which can perform DSP task, e.g., FIR. Thereport is a well structured
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3

Cheung, Newton Computer Science &amp Engineering Faculty of Engineering UNSW. "Design automation methodologies for extensible processor platform." Awarded by:University of New South Wales. School of Computer Science and Engineering, 2005. http://handle.unsw.edu.au/1959.4/26118.

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Abstract (sommario):
This thesis addresses two ubiquitous trends in the embedded system world - the increasing importance of design turnaround time as a design metric, and the move towards closing the design productivity gap. Adopting the right choice of design approach has been recognised as an integral part of the design flow in order to meet desired characteristics such as increasing software content, satisfying the growing complexities of an application, reusing off-the-shelf components, and exploring design metrics tradeoff, which closes the design productivity gap. The importance of design turnaround time is
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4

Mikó, Albert. "Akcelerace aplikací pomocí specializovaných instrukcí." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2016. http://www.nusl.cz/ntk/nusl-255444.

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Abstract (sommario):
The design of specialized instructions for application specific processors is a challenging task. This thesis describes the issues of effective specification and use of specialized instructions for optimization of applications. It focuses on improvements of the outputs and usability of the semiatomatic method of selection of specialized instructions to allow the optimization of complicated applications. This method combines manual selection of instructions by marking a section of source code in the application and automatic generation of the instruction description in the modelling language.
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5

Šulek, Jakub. "Verifikace ASIP založena na formálních tvrzeních." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2015. http://www.nusl.cz/ntk/nusl-264941.

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Abstract (sommario):
This thesis introduces the concept of assertion-based verifi cation of application-specifi c instruction set processors (ASIPs). The proposed design is implemented in SystemVerilog Assertions language as a part of veri fication environment created using Codasip Framework. The implemented concept is simulated in QuestaSim tool using model of Codix RISC processor. Main outcome of this thesis is the verifi cation concept usable not only on other processors, but as a part of system that automates the processor design as well.
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6

Vogt, Timo. "A reconfigurable application-specific instruction-set processor for trellis-based channel decoding /." Kaiserslautern : Techn. Univ. Kaiserslautern, 2008. http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&doc_number=016537958&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA.

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7

Shee, Seng Lin Computer Science &amp Engineering Faculty of Engineering UNSW. "ADAPT : architectural and design exploration for application specific instruction-set processor technologies." Awarded by:University of New South Wales, 2007. http://handle.unsw.edu.au/1959.4/35404.

Testo completo
Abstract (sommario):
This thesis presents design automation methodologies for extensible processor platforms in application specific domains. The work presents first a single processor approach for customization; a methodology that can rapidly create different processor configurations by the removal of unused instructions sets from the architecture. A profile directed approach is used to identify frequently used instructions and to eliminate unused opcodes from the available instruction pool. A coprocessor approach is next explored to create an SoC (System-on-Chip) to speedup the application while reducing energy
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8

Yassin, Yahya H. "ULTRA LOW POWER APPLICATION SPECIFIC INSTRUCTION-SET PROCESSOR DESIGN : for a cardiac beat detector algorithm." Thesis, Norwegian University of Science and Technology, Department of Electronics and Telecommunications, 2009. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-9914.

Testo completo
Abstract (sommario):
<p>High efficiency and low power consumption are among the main topics in embedded systems today. For complex applications, off-the-shelf processor cores might not provide the desired goals in terms of power consumption. By optimizing the processor for the application, or a set of applications, one could improve the computing power by introducing special purpose hardware units. The execution cycle count of the application would in this case be reduced significantly, and the resulting processor would consume less power. In this thesis, some research is done in how to optimize a software and h
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9

Husár, Adam. "Implementace obecného assembleru." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2007. http://www.nusl.cz/ntk/nusl-412779.

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Abstract (sommario):
This thesis describes the design of the universal assembler that represents a part of the Lissom project. You will be provided with the description of the assembler architectures and their usual tasks. Special attention is paid to GNU assembler. Designed assembler consists of the fixed and the generated part. The generated part is created automatically from the description of instruction set, that is defined using architecture and instructions set description language ISAC. Using this approach, it is possible to change assembler target architecture automatically. The second part of thesis desc
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10

Bytyn, Andreas [Verfasser], Gerd [Akademischer Betreuer] Ascheid, and Rainer [Akademischer Betreuer] Leupers. "Efficiency and scalability exploration of an application-specific instruction-set processor for deep convolutional neural networks / Andreas Bytyn ; Gerd Ascheid, Rainer Leupers." Aachen : Universitätsbibliothek der RWTH Aachen, 2020. http://d-nb.info/1230325506/34.

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11

Kreutz, Marcio Eduardo. "Geração de processador para aplicacao especifica." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 1997. http://hdl.handle.net/10183/17752.

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Abstract (sommario):
Este trabalho propõe a geração de uma arquitetura dedicada a aplicações específicas, baseadas no microcontrolador MCS8051. Por ser utilizado na solução de problemas em indústrias locais, este processador foi escolhido para servir como base em um sistema dedicado. O 8051 dedicado gerado deverá permitir a integração completa do sistema, proporcionando um aumento do valor agregado e, conseqüentemente, a diminuição do custo. Busca-se com a otimização da arquitetura obter um conjunto de instruções reduzido, construído com as instruções mais utilizadas em cada aplicação. O objetivo principal da otim
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12

Tell, Eric. "Design of Programmable Baseband Processors." Doctoral thesis, Linköping : Univ, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-4377.

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13

Jain, Manoj Kumar. "Exploring register file and memory organization in ASIP synthesis." Thesis, 2003. http://localhost:8080/iit/handle/2074/2197.

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14

Κάργας, Χρήστος. "Energy efficient instruction decoding in application: Specific instruction - set processors." Thesis, 2012. http://hdl.handle.net/10889/6295.

Testo completo
Abstract (sommario):
With commercial processor design tools, a designer can quickly design a C- programmable ASIP for a specific application domain. There are several such ASIPs available for both wireless (UWB baseband processing), encryption, and biomedical processing (particularly for ECG beat detection). In traditional CPUs and DSPs the impact of the instruction-set definition and the complexity of the instruction decoder can be substantial, especially in terms of power consumption. Fully orthogonal VLIW processors, do not incur the cost of an instruction decoder that severely. Instead the instruction w
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15

Τσεκούρα, Ιωάννα. "Design exploration of application specific instruction set cryptographic processors for resources constrained systems." Thesis, 2010. http://nemertes.lis.upatras.gr/jspui/handle/10889/3905.

Testo completo
Abstract (sommario):
The battery driven nature of wireless sensor networks, combined with the need of extended lifetime mandates that energy efficiency is a metric with high priority. In the current thesis we explore and compare the energy dissipation of di fferent processor architectures and how it is associated with performance and area requirements. The processor architectures are di erentiated based on the datapath length (16-bit, 32-bit, 64-bit and 128-bit) and the corresponding size of the data memories. Our study focuses on AES algorithm, and the indicated processor architectures support AES forward e
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16

"Application-specific instruction set processor for speech recognition." 2005. http://library.cuhk.edu.hk/record=b5892381.

Testo completo
Abstract (sommario):
Cheung Man Ting.<br>Thesis (M.Phil.)--Chinese University of Hong Kong, 2005.<br>Includes bibliographical references (leaves 69-71).<br>Abstracts in English and Chinese.<br>Chapter 1 --- Introduction --- p.1<br>Chapter 1.1 --- The Emergence of ASIP --- p.1<br>Chapter 1.1.1 --- Related Work --- p.3<br>Chapter 1.2 --- Motivation --- p.6<br>Chapter 1.3 --- ASIP Design Methodologies --- p.7<br>Chapter 1.4 --- Fundamentals of Speech Recognition --- p.8<br>Chapter 1.5 --- Thesis outline --- p.10<br>Chapter 2 --- Automatic Speech Recognition --- p.11<br>Chapter 2.1 --- Overview of ASR system -
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17

Chao, Chie-Min, and 趙至敏. "Development of Software Tools for Application-Specific Instruction-set Processors (ASIPs)." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/10553662144219920236.

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Abstract (sommario):
碩士<br>國立交通大學<br>電子工程系所<br>93<br>Programmable processors are dramatically attractive to amortize manufacturing costs and design efforts, as the system complexity grows. Besides, in order to satisfy the tight design constraints such as performance and power of today’s embedded systems, processor architectures are getting more specialized to some application domains (e.g. an application-specific instruction-set processor; ASIP). This thesis discusses the acceleration of system prototyping of new processor cores by reducing the software development time. Firstly, we propose a simple and effective
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18

Wu, Ji-Ying, and 吳季穎. "Application-Specific Instruction-set Processor for Memory Access Reduction." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/28927896519309109410.

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Abstract (sommario):
碩士<br>逢甲大學<br>資訊工程所<br>95<br>Embedded system designers sometimes need to optimize some specific time consuming application programs to speed up the system. Optimizing embedded processor for specific application is studied in recently years. To re-design whole processor makes a long design time, so the idea of changing instruction set of processor only is proposed. As some tool providers adding such a idea into their system design tool, ASIP is beginning to be discussed. In past days, ASIP researches almost focus on instructions only. There is a few researches which are considering instruction
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19

Nanda, Umakanta. "Design of an Application Specific Instruction Set Processor Using LISA." Thesis, 2010. http://ethesis.nitrkl.ac.in/1976/1/my_thesis_(2).pdf.

Testo completo
Abstract (sommario):
A Digital Signal Processor with specific instruction sets and meant for a specific application is called as Application Specific Instruction set Processor(ASIP). To design an ASIP many approaches are available. However optimization of an ASIP becomes handy if it is designed in a higher level of abstraction that is higher than Register Transfer Level (RTL). Application Description Languages (ADLs) are becoming popular recently because of its quick and optimal design convergence achievement capability during the design of ASIPs. Several stages are required to design a processor which are archite
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20

Samal, Lopamudra. "Application specific instruction set processor design for embedded application using the coware tool." Thesis, 2012. http://ethesis.nitrkl.ac.in/4058/1/e_thesis.pdf.

Testo completo
Abstract (sommario):
An Application Specific Instruction Set Processor (ASIP) is widely used as a System on a Chip(SoC) Component. ASIPs possess an instruction set which is tai-lored to benefit a specific application. Such specialization allows ASIPs to serve as an intermediate between two dominant processor design styles- ASICs which has high processing abilities at the cost of limited programmability and Programmable solu-tions such as FPGAs that provide programming exibility at the cost of less energy eficiency. In this dissertation the goal is to design ASIP, keeping in mind a temper-ature sensor system. The p
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21

Sutar, Soubhagya, and Anup Sarma. "Design and Implementation of Application Specific Instruction Set Processor using LISATek Design Methodology." Thesis, 2011. http://ethesis.nitrkl.ac.in/2607/1/ASIP.pdf.

Testo completo
Abstract (sommario):
An Application Specific Instruction Set Processor (ASIP) is widely used as a System on a Chip Component. ASIPs possess an instruction set which is tailored to benefit a specific application. Such specialization allows ASIPs to serve as an intermediate between two dominant processor design styles- ASICs which has high processing abilities at the cost of limited programmability and Programmable solutions such as FPGAs that provide programming flexibility at the cost of less energy efficiency. In this project our goal is to design ASIP, keeping in mind Digital Image and Signal Processing Applicat
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