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Articoli di riviste sul tema "Application specific instruction-set processor (ASIP)"

Autore: Grafiati

Pubblicato: 4 giugno 2021

Ultima modifica: 25 luglio 2025

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1

Imai, Masaharu, Yoshinori Takeuchi, Keishi Sakanushi, and Nagisa Ishiura. "Advantage and Possibility of Application-domain Specific Instruction-set Processor (ASIP)." IPSJ Transactions on System LSI Design Methodology 3 (2010): 161–78. http://dx.doi.org/10.2197/ipsjtsldm.3.161.

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Sharma, Poonam, Ashwani Kumar Dubey, and Ayush Goyal. "Efficient Computing in Image Processing and DSPs with ASIP Based Multiplier." Recent Patents on Engineering 13, no. 2 (2019): 174–80. http://dx.doi.org/10.2174/1872212112666180810150357.

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Background: With the growing demand of image processing and the use of Digital Signal Processors (DSP), the efficiency of the Multipliers and Accumulators has become a bottleneck to get through. We revised a few patents on an Application Specific Instruction Set Processor (ASIP), where the design considerations are proposed for application-specific computing in an efficient way to enhance the throughput. Objective: The study aims to develop and analyze a computationally efficient method to optimize the speed performance of MAC. Methods: The work presented here proposes the design of an Applica

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3

Mukherji, Rana, and Manishita Das. "System Level Modeling Methodology of Application Specific Instruction Set Processor (Asip) Using Systemc." DIU Journal of Science & Technology 7, no. 1 (2024): 44–49. https://doi.org/10.5281/zenodo.13733703.

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In recent years, the development of application specific instruction set processors (ASIP) is the exclusive domain of the semiconductor houses and core vendors. This is due to the fact that constructing such architecture is a difficult assignment that needs skilled knowledge in distinct domains: application software development tools, processor hardware implementation, and system integration and verification. To specify the design and implementation of such systems and incorporate the functionality implemented in both hardware and software forms, we are compelled to move on from traditional Ha

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4

Xin, Yao, Will X. Y. Li, Zhaorui Zhang, Ray C. C. Cheung, Dong Song, and Theodore W. Berger. "An Application Specific Instruction Set Processor (ASIP) for Adaptive Filters in Neural Prosthetics." IEEE/ACM Transactions on Computational Biology and Bioinformatics 12, no. 5 (2015): 1034–47. http://dx.doi.org/10.1109/tcbb.2015.2440248.

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5

Safaei Mehrabani, Yavar. "Synthesis of an Application Specific Instruction Set Processor (ASIP) for RIPEMD-160 Hash Algorithm." International Journal of Electronics Letters 7, no. 2 (2018): 154–65. http://dx.doi.org/10.1080/21681724.2018.1477182.

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Andorno, M., M. Andersen, G. Borghello, et al. "Rad-hard RISC-V SoC and ASIP ecosystems studies for high-energy physics applications." Journal of Instrumentation 18, no. 01 (2023): C01018. http://dx.doi.org/10.1088/1748-0221/18/01/c01018.

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Abstract The increase in complexity and size of modern ASIC designs in the HEP community and the use of advanced semiconductor fabrication processes raises the need for a shift toward a more abstract design methodology, that takes advantage of modularity and programmability to achieve a faster turnaround time both for design and verification. This contribution will present two complementary approaches, one using a RISC-V based System-on-Chip (SoC) and the other based on Application-Specific Instruction set Processors (ASIP). The SoC uses the PicoRV32 open-source RISC-V core and a rad-hard vers

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Zhang, Diandian, Li Lu, Jeronimo Castrillon, et al. "Efficient Implementation of Application-Aware Spinlock Control in MPSoCs." International Journal of Embedded and Real-Time Communication Systems 4, no. 1 (2013): 64–84. http://dx.doi.org/10.4018/jertcs.2013010104.

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Spinlocks are a common technique in Multi-Processor Systems-on-Chip (MPSoCs) to protect shared resources and prevent data corruption. Without a priori application knowledge, the control of spinlocks is often highly random which can degrade the system performance significantly. To improve this, a centralized control mechanism for spinlocks is proposed in this paper, which utilizes application-specific information during spinlock control. The complete control flow is presented, which starts from integrating high-level user-defined information down to a low-level realization of the control. An Ap

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8

Zhou, Xinbing, Yi Man, Peng Hao, et al. "ASIP Performance Enhancement by Hazard Control through Scoreboard." Micromachines 15, no. 11 (2024): 1287. http://dx.doi.org/10.3390/mi15111287.

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The application-specific instruction set processor (ASIP) has been gradually accepted in AI, communication, media, game and industry control. The digital signal processor (DSP) is a typical ASIP, whose benefits include high performance in specific domains, low power consumption, high flexibility and low silicon consumption. One of the challenges for DSP design is to handle problems induced by datapath acceleration. The datapath acceleration (instruction fusion, black box instructions) induces control complexities. To most efficiently utilize hardware, control challenges can be summarized as RA

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9

Engroff, Alian, Marcelo Romanssini, Lucas Compassi-Severo, Paulo C. C. de Aguirre, and Alessandro Girardi. "ASIPAMPIUM: An Efficient ASIP Generator for Low Power Applications." Electronics 12, no. 2 (2023): 401. http://dx.doi.org/10.3390/electronics12020401.

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The adoption of customized ASIPs (Application Specific Instruction Set Processors) in embedded circuits is an important alternative for optimizing power consumption, silicon area, or processing performance according to the design requirements. The processor is implemented specifically for the target application, which allows the hardware customization in terms of instruction set architecture, data word length, memory size, and parallelism. This work describes an EDA tool for the semi-automatic development of ASIPs named ASIPAMPIUM. The strategy is to provide a set of integrated tools to interp

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10

Iwaizumi, Hiroki, Shingo Yoshizawa, and Yoshikazu Miyanaga. "A High-Speed and Low-Energy-Consumption Processor for SVD-MIMO-OFDM Systems." VLSI Design 2013 (March 18, 2013): 1–10. http://dx.doi.org/10.1155/2013/625019.

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A processor design for singular value decomposition (SVD) and compression/decompression of feedback matrices, which are mandatory operations for SVD multiple-input multiple-output orthogonal frequency-division multiplexing (MIMO-OFDM) systems, is proposed and evaluated. SVD-MIMO is a transmission method for suppressing multistream interference and improving communication quality by beamforming. An application specific instruction-set processor (ASIP) architecture is adopted to achieve flexibility in terms of operations and matrix size. The proposed processor realizes a high-speed/low-power des

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11

Qiao, Wan, and Dake Liu. "A scalable ASIP for BP Polar decoding with multiple code lengths." MATEC Web of Conferences 232 (2018): 01046. http://dx.doi.org/10.1051/matecconf/201823201046.

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In this paper, we propose a flexible scalable BP Polar decoding application-specific instruction set processor (PASIP) that supports multiple code lengths (64 to 4096) and any code rates. High throughputs and sufficient programmability are achieved by the single-instruction-multiple-data (SIMD) based architecture and specially designed Polar decoding acceleration instructions. The synthesis result using 65 nm CMOS technology shows that the total area of PASIP is 2.71 mm2. PASIP provides the maximum throughput of 1563 Mbps (for N = 1024) at the work frequency of 400MHz. The comparison with stat

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12

Wong, Tingh Wee, Bryan Ng, and Chee Onn Wong. "Encoding Custom Instruction Generation as Satisfiability Problem." Advanced Materials Research 403-408 (November 2011): 502–10. http://dx.doi.org/10.4028/www.scientific.net/amr.403-408.502.

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The emergence of Application-specific Instruction-set Processor (ASIP) has encouraged the proliferation of tool-chains used to streamline its design flow. One of the features much sought-after in these tool-chains is notably the automatic generation of Application-specific Functional Units (AFUs) which, in turn, involves the custom instruction generation as a crucial step. Whereupon an additional step is assumed to pipeline the patterns identified for fulfilling the I/O constraint, custom instructions that correspond to maximal valid subgraphs are mostly beneficial to the speedup gain. Therefo

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Fischer, Dirk, Jürgen Teich, Ralph Weper, and Michael Thies. "BUILDABONG: A Framework for Architecture/Compiler Co-Exploration for ASIPs." Journal of Circuits, Systems and Computers 12, no. 03 (2003): 353–75. http://dx.doi.org/10.1142/s0218126603000799.

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With the term Architecture/Compiler Co-exploration, we denote the problem of simultaneously optimizing an application-specific instruction set processor (ASIP) architecture as well as its generated compiler. In this paper, we characterize the design space of both compiler frontend (intermediate code optimization) and backend (changes of the machine model) and present the workflow of our framework BUILDABONG. The project consists of four phases: (a) architecture entry and composition, (b) automatic simulator generation, (c) compiler generation (in particular, retargeting), and (d) automatic arc

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14

Gao, Muxuan, He Chen, and Dake Liu. "An ASIP for Neural Network Inference on Embedded Devices with 99% PE Utilization and 100% Memory Hidden under Low Silicon Cost." Sensors 22, no. 10 (2022): 3841. http://dx.doi.org/10.3390/s22103841.

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The computation efficiency and flexibility of the accelerator hinder deep neural network (DNN) implementation in embedded applications. Although there are many publications on deep neural network (DNN) processors, there is still much room for deep optimization to further improve results. Multiple dimensions must be simultaneously considered when designing a DNN processor to reach the performance limit of the architecture, including architecture decision, flexibility, energy efficiency, and silicon cost minimization. Flexibility is defined as the ability to support as many multiple networks as

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15

Hamed, Ahmed, M. Watheq El-Kharashi, Ashraf Salem, and Mona Safar. "Two-Layer Bus-Independent Instruction Set Architecture for Securing Long Protocol Data Units in Automotive Open System Architecture-Based Automotive Electronic Control Units." Electronics 11, no. 6 (2022): 952. http://dx.doi.org/10.3390/electronics11060952.

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In this paper, we propose a bus-independent hardware (HW)-based approach to secure long protocol data units (PDUs) in Automotive Open System Architecture (AUTOSAR)-based automotive electronic control units (ECUs). Our approach is based on extending previous works that implemented two AUTOSAR communication (COM) application-specific instruction set processors (ASIPs). COM ASIP V1 introduced two instructions to handle the transmission and reception of PDUs no larger than 8 bytes and signals no larger than 32 bits individually through send signal and receive signal instructions. COM ASIP V2 intro

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16

Ahmed, O., S. Areibi, and G. Grewal. "Hardware Accelerators Targeting a Novel Group Based Packet Classification Algorithm." International Journal of Reconfigurable Computing 2013 (2013): 1–33. http://dx.doi.org/10.1155/2013/681894.

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Packet classification is a ubiquitous and key building block for many critical network devices. However, it remains as one of the main bottlenecks faced when designing fast network devices. In this paper, we propose a novel Group Based Search packet classification Algorithm (GBSA) that is scalable, fast, and efficient. GBSA consumes an average of 0.4 megabytes of memory for a 10 k rule set. The worst-case classification time per packet is 2 microseconds, and the preprocessing speed is 3 M rules/second based on an Xeon processor operating at 3.4 GHz. When compared with other state-of-the-art cl

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17

Shinde, Vaishnavi, Zeba Karpude, Pooja Kolhe, and Alpesh Wadte. "Design and Simulation of 32-Bit RISC Architecture Based on MIPS using Verilog." International Scientific Journal of Engineering and Management 04, no. 03 (2025): 1–7. https://doi.org/10.55041/isjem02553.

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VERILOG Very High-Speed Integrated Circuits Hardware Description Language) is widely used for ASIC (Application Specific Integrated Circuits) emulation, as well as a solution for applications with high volatility. FPGA (Field Programmable Gate Array) give quick time to market, and its feature of re-programmability often makes them the main part of the system. This paper presents the design of a RISC (Reduced Instruction Set Computer) CPU architecture based on MIPS (Microprocessor Interlock Pipeline Stages) using Verilog. It also describes the instruction set, architecture and timing diagram of

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18

Salmela, Perttu, Adrian Burian, Tuomas Järvinen, Aki Happonen, and Jarmo Henrik Takala. "Low-Complexity Inverse Square Root Approximation for Baseband Matrix Operations." ISRN Signal Processing 2011 (February 16, 2011): 1–8. http://dx.doi.org/10.5402/2011/615934.

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Baseband functions like channel estimation and symbol detection of sophisticated telecommunications systems require matrix operations, which apply highly nonlinear operations like division or square root. In this paper, a scalable low-complexity approximation method of the inverse square root is developed and applied in Cholesky and QR decompositions. Computation is derived by exploiting the binary representation of the fixedpoint numbers and by substituting the highly nonlinear inverse square root operation with a more implementation appropriate function. Low complexity is obtained since the

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19

CATANIA, VINCENZO, MAURIZIO PALESI, and DAVIDE PATTI. "ANALYSIS AND TOOLS FOR THE DESIGN OF VLIW EMBEDDED SYSTEMS IN A MULTI-OBJECTIVE SCENARIO." Journal of Circuits, Systems and Computers 16, no. 05 (2007): 819–46. http://dx.doi.org/10.1142/s0218126607003915.

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The use of Application-Specific Instruction-set Processors (ASIP) in embedded systems is a solution to the problem of increasing complexity in the functions these systems have to implement. Architectures based on Very Long Instruction Word (VLIW) have found fertile ground in multimedia electronic appliances thanks to their ability to exploit high degrees of Instruction Level Parallelism (ILP) with a reasonable trade-off in complexity and silicon costs. In this case the ASIP specialization involves a complex interaction between hardware- and software-related issues. In this paper we propose too

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20

Urban, Roberto, Heinrich T. Vierhaus, Mario Schölzel, Enrico Altmann, and Horst Seelig. "Non-Cyclic Design Space Exploration for ASIPs — Compiler-Centered Microprocessor Design (CoMet)." Journal of Circuits, Systems and Computers 25, no. 03 (2015): 1640012. http://dx.doi.org/10.1142/s0218126616400120.

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The CoMet approach on designing application specific instruction set processors (ASIPs) is targeting a non-cyclic design space exploration (DSE). The design process is driven by a step by step refinement of intermediate codes, known from compiler backends. In every step, the intermediate code can be simulated and profiled. Based on that profiling information, it can be further transformed to an optimized or refined intermediate code. The whole transformation process is implemented in a GUI-based design tool, whose main component is a configurable simulator for intermediate codes. It will be sh

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21

Kammler, David, Ernst Martin Witte, Anupam Chattopadhyay, et al. "Automatic Generation of Memory Interfaces for ASIPs." International Journal of Embedded and Real-Time Communication Systems 1, no. 3 (2010): 1–23. http://dx.doi.org/10.4018/jertcs.2010070101.

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With the growing market for multi-processor system-on-chip (MPSoC) solutions, application-specific instruction-set processors (ASIPs) gain importance as they allow for a wide tradeoff between flexibility and efficiency in such a system. Their development is aided by architecture description languages (ADLs) supporting the automatic generation of architecture-specific tool sets as well as synthesizable register transfer level (RTL) implementations from a single architecture model. However, these generated implementations have to be manually adapted to the interfaces of dedicated memories or mem

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22

Meloni, Paolo, Sebastiano Pomata, Giuseppe Tuveri, Simone Secchi, Luigi Raffo, and Menno Lindwer. "Enabling Fast ASIP Design Space Exploration: An FPGA-Based Runtime Reconfigurable Prototyper." VLSI Design 2012 (March 29, 2012): 1–16. http://dx.doi.org/10.1155/2012/580584.

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Application Specific Instruction-set Processors (ASIPs) expose to the designer a large number of degrees of freedom. Accurate and rapid simulation tools are needed to explore the design space. To this aim, FPGA-based emulators have recently been proposed as an alternative to pure software cycle-accurate simulator. However, the advantages of on-hardware emulation are reduced by the overhead of the RTL synthesis process that needs to be run for each configuration to be emulated. The work presented in this paper aims at mitigating this overhead, exploiting a form of software-driven platform runti

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V., Surega. "A Review on Fast FPGA Development of RSD based ECC Processor." International Journal of Trend in Scientific Research and Development 2, no. 3 (2018): 583–86. https://doi.org/10.31142/ijtsrd7166.

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Elliptic curve Cryptography ECC is an asymmetric cryptographic system such as Lenstra elliptic curve factorization. This provides higher security than the Rivest, Shamir and Adleman system RSA system. The processor employs extensive pipelining techniques for Karatsuba-Ofman method to achieve high throughput multiplication. Furthermore, an pwerfull smodular adder without comparison and a highthroughput modular divider, which results in a short datapath for maximized frequency, are implemented. The processor supports the recommended NIST curve P256 and is based on an extended NIST reduction sche

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Yoshitomi, Hiroyuki. "OrientalHydrocyphon(Coleoptera: Scirtidae: Scirtinae): Seven New Species from Indonesia, Thailand, Malaysia, and India." Psyche: A Journal of Entomology 2012 (2012): 1–16. http://dx.doi.org/10.1155/2012/603875.

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Application Specific Instruction-set Processors (ASIPs) expose to the designer a large number of degrees of freedom. Accurate and rapid simulation tools are needed to explore the design space. To this aim, FPGA-based emulators have recently been proposed as an alternative to pure software cycle-accurate simulator. However, the advantages of on-hardware emulation are reduced by the overhead of the RTL synthesis process that needs to be run for each configuration to be emulated. The work presented in this paper aims at mitigating this overhead, exploiting a form of software-driven platform runti

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Radhakrishnan, S., H. Guo, S. Parameswaran, and A. Ignjatovic. "HMP-ASIPs: heterogeneous multi-pipeline application-specific instruction-set processors." IET Computers & Digital Techniques 3, no. 1 (2009): 94. http://dx.doi.org/10.1049/iet-cdt:20080005.

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Shen, Zheng, Hu He, Yanjun Zhang, and Yihe Sun. "A Video Specific Instruction Set Architecture for ASIP design." VLSI Design 2007 (November 15, 2007): 1–7. http://dx.doi.org/10.1155/2007/58431.

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This paper describes a novel video specific instruction set architecture for ASIP design. With single instruction multiple data (SIMD) instructions, two destination modes, and video specific instructions, an instruction set architecture is introduced to enhance the performance for video applications. Furthermore, we quantify the improvement on H.263 encoding. In this paper, we evaluate and compare the performance of VS-ISA, other DSPs (digital signal processors), and conventional SIMD media extensions in the context of video coding. Our evaluation results show that VS-ISA improves the processo

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Deole, Akshay, Vanita Agarwal, and Vaishali Ingale. "Implementation of Application Specific Instruction set Processor for Approximate Computing." WSEAS TRANSACTIONS ON COMPUTERS 23 (August 14, 2024): 204–10. http://dx.doi.org/10.37394/23205.2024.23.19.

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The performance, energy efficiency, power dissipation, and cost of the processors used in Internet of Things edge devices can be improved by introducing approximate computing. In this paper, the design and synthesis of an application-specific instruction set processor for approximate computing is proposed. Approximate computing can also be defined by using Artificial Intelligence-based technique like the Fractal theory and Inconsistent Information System. Application Specific Instruction Set Processor is a new processor design area and is used to design a new instruction set using existing pro

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Abderazek, Ben A., Sotaro Kawata, and Masahiro Sowa. "Design and architecture for an embedded 32-bit QueueCore." Journal of Embedded Computing 2, no. 2 (2006): 191–205. https://doi.org/10.3233/emc-2006-00028.

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Queue based instruction set architecture processor offers an attractive option in the design of embedded systems by providing high performance for a specific application. This work describes the design results and methodology of a queue processor core, named QueueCore, as a starting point for application-specific processor (ASP) design. By using simple and common base queue instruction set, the design space exploration is focused on the application-specific aspects of performance. In any new architecture, verification, which usually requires complicated and lengthy software simulation of an em

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Antikainen, Juho, Perttu Salmela, Olli Silvén, Markku Juntti, Jarmo Takala, and Markus Myllylä. "Application-Specific Instruction Set Processor Implementation of List Sphere Detector." EURASIP Journal on Embedded Systems 2007 (2007): 1–14. http://dx.doi.org/10.1155/2007/54173.

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Antikainen, Juho, Perttu Salmela, Olli Silvén, Markku Juntti, Jarmo Takala, and Markus Myllylä. "Application-Specific Instruction Set Processor Implementation of List Sphere Detector." EURASIP Journal on Embedded Systems 2007, no. 1 (2007): 054173. http://dx.doi.org/10.1186/1687-3963-2007-054173.

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Sisto, A., L. Pilato, R. Serventi, S. Saponara, and L. Fanucci. "Application specific instruction set processor for sensor conditioning in automotive applications." Microprocessors and Microsystems 47 (November 2016): 375–84. http://dx.doi.org/10.1016/j.micpro.2016.10.001.

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Rajveer Singh, Et al. "RISC-V Processor for IOT Applications." International Journal on Recent and Innovation Trends in Computing and Communication 11, no. 11 (2023): 701–5. http://dx.doi.org/10.17762/ijritcc.v11i11.10074.

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RISC-V is a recently introduced instruction-set architecture (ISA) that offers innovative advantages, including low power consumption, affordability, and scalability. Utilizing an open, non-proprietary Instruction Set Architecture (ISA) enables the creation of on-the-fly design of soft error countermeasures at the microarchitecture level. This may significantly enhance the resilience of Application Specific Standard Products (ASSP) and FPGA implementations. This paper offers a quick overview of the RISC-V architecture. This paper presents a plan to create and execute a 32-bit single-cycle RISC

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Hoffmann, A., T. Kogel, A. Nohl, et al. "A novel methodology for the design of application-specific instruction-set processors (ASIPs) using a machine description language." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 20, no. 11 (2001): 1338–54. http://dx.doi.org/10.1109/43.959863.

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Peters, H., R. Sethuraman, A. Beric, et al. "Application specific instruction-set processor template for motion estimation in video applications." IEEE Transactions on Circuits and Systems for Video Technology 15, no. 4 (2005): 508–27. http://dx.doi.org/10.1109/tcsvt.2005.844462.

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Saponara, Sergio, Luca Fanucci, Stefano Marsi, Giovanni Ramponi, David Kammler, and Ernst Martin Witte. "Application-Specific Instruction-Set Processor for Retinex-Like Image and Video Processing." IEEE Transactions on Circuits and Systems II: Express Briefs 54, no. 7 (2007): 596–600. http://dx.doi.org/10.1109/tcsii.2007.896778.

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Choi, Seung-Hyun, Tae-Moon Roh, Yong Ho Song, and Seong-Won Lee. "Design of an application specific instruction set processor for a universal bitstream codec." IEICE Electronics Express 11, no. 24 (2014): 20141047. http://dx.doi.org/10.1587/elex.11.20141047.

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Zhaohui Liu, K. Dickson, and J. V. McCanny. "Application-specific instruction set processor for SoC implementation of modern signal processing algorithms." IEEE Transactions on Circuits and Systems I: Regular Papers 52, no. 4 (2005): 755–65. http://dx.doi.org/10.1109/tcsi.2005.844109.

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Bytyn, Andreas, Rainer Leupers, and Gerd Ascheid. "ConvAix: An Application-Specific Instruction-Set Processor for the Efficient Acceleration of CNNs." IEEE Open Journal of Circuits and Systems 2 (2021): 3–15. http://dx.doi.org/10.1109/ojcas.2020.3037758.

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Mbaye, Mame Maria, Normand Bélanger, Yvon Savaria, and Samuel Pierre. "A Novel Application-specific Instruction-set Processor Design Approach for Video Processing Acceleration." Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology 47, no. 3 (2007): 297–315. http://dx.doi.org/10.1007/s11265-007-0050-0.

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Mooney, James, Abdulhussain E. Mahdi, and Mark Halton. "Application-Specific Instruction-Set Processor for Control of Multi-Rail DC-DC Converter Systems." IEEE Transactions on Circuits and Systems I: Regular Papers 60, no. 1 (2013): 243–54. http://dx.doi.org/10.1109/tcsi.2012.2215783.

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Heo, Ingoo, Minsu Kim, Yongje Lee, et al. "Implementing an Application-Specific Instruction-Set Processor for System-Level Dynamic Program Analysis Engines." ACM Transactions on Design Automation of Electronic Systems 20, no. 4 (2015): 1–32. http://dx.doi.org/10.1145/2746238.

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ZHANG, Yuli, Jun HAN, Xinqian WENG, Zhongzhu HE, and Xiaoyang ZENG. "Design Approach and Implementation of Application Specific Instruction Set Processor for SHA-3 BLAKE Algorithm." IEICE Transactions on Electronics E95.C, no. 8 (2012): 1415–26. http://dx.doi.org/10.1587/transele.e95.c.1415.

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Tamagnone, M., M. Martina, and G. Masera. "An application specific instruction set processor based implementation for signal detection in multiple antenna systems." Microprocessors and Microsystems 36, no. 3 (2012): 245–56. http://dx.doi.org/10.1016/j.micpro.2011.11.003.

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XIAO, Shanlin, Tsuyoshi ISSHIKI, Dongju LI, and Hiroaki KUNIEDA. "Design of an Application Specific Instruction Set Processor for Real-Time Object Detection Using AdaBoost Algorithm." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E100.A, no. 7 (2017): 1384–95. http://dx.doi.org/10.1587/transfun.e100.a.1384.

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Lin, Hai, and Yunsi Fei. "Resource Sharing of Pipelined Custom Hardware Extension for Energy-Efficient Application-Specific Instruction Set Processor Design." ACM Transactions on Design Automation of Electronic Systems 17, no. 4 (2012): 1–20. http://dx.doi.org/10.1145/2348839.2348843.

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Guan, Xuan, Yunsi Fei, and Hai Lin. "Hierarchical Design of an Application-Specific Instruction Set Processor for High-Throughput and Scalable FFT Processing." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20, no. 3 (2012): 551–63. http://dx.doi.org/10.1109/tvlsi.2011.2105512.

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Xie, Chunhu, Huachun Wu, and Jian Zhou. "Vectorization Programming Based on HR DSP Using SIMD." Electronics 12, no. 13 (2023): 2922. http://dx.doi.org/10.3390/electronics12132922.

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Abstract (sommario):

Single instruction multiple data (SIMD) vector extension has become an essential feature of high-performance processors. Architectures such as x86, ARM, MIPS, and PowerPC have specific vector extension instruction sets and SIMD micro-architectures. Using SIMD vectorization programming can significantly improve the performance of application algorithms while keeping the hardware overhead low. In addition, other methods can enhance algorithm performance, such as selecting the best SIMD vectorization model for algorithms, ensuring sufficient instruction streams, implementing reasonable and effect

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Salmela, Perttu, Harri Sorokin, and Jarmo Takala. "A Programmable Max-Log-MAP Turbo Decoder Implementation." VLSI Design 2008 (December 22, 2008): 1–17. http://dx.doi.org/10.1155/2008/319095.

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In the advent of very high data rates of the upcoming 3G long-term evolution telecommunication systems, there is a crucial need for efficient and flexible turbo decoder implementations. In this study, a max-log-MAP turbo decoder is implemented as an application-specific instruction-set processor. The processor is accompanied with accelerating computing units, which can be controlled in detail. With a novel memory interface, the dual-port memory for extrinsic information is avoided. As a result, processing one trellis stage with max-log-MAP algorithm takes only 1.02 clock cycles on average, whi

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Abdel All, Mahmoud, Hanan M. Hassan, Medhat Hamdy, Omar A. Nasr, Karim Mohamed, and Ahmed F. Shalash. "Design and implementation of application‐specific instruction‐set processor design for high‐throughput multi‐standard wireless orthogonal frequency division multiplexing baseband processor." IET Circuits, Devices & Systems 9, no. 3 (2015): 191–203. http://dx.doi.org/10.1049/iet-cds.2014.0046.

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Zhang, Diandian, Han Zhang, Jeronimo Castrillon, et al. "Optimized Communication Architecture of MPSoCs with a Hardware Scheduler." International Journal of Embedded and Real-Time Communication Systems 2, no. 3 (2011): 1–20. http://dx.doi.org/10.4018/jertcs.2011070101.

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Abstract (sommario):

Efficient runtime resource management in multi-processor systems-on-chip (MPSoCs) for achieving high performance and low energy consumption is one of the key challenges for system designers. OSIP, an operating system application-specific instruction-set processor, together with its well-defined programming model, provides a promising solution. It delivers high computational performance to deal with dynamic task scheduling and mapping. Being programmable, it can easily be adapted to different systems. However, the distributed computation among the different processing elements introduces comple

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