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Tesi sul tema "Field Programmable Gate Arrays"

Autore: Grafiati

Pubblicato: 4 giugno 2021

Ultima modifica: 25 luglio 2025

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1

Howard, Neil John. "Defect-tolerant Field-Programmable Gate Arrays." Thesis, University of York, 1994. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.359290.

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2

Hall, Tyson Stuart. "Field-Programmable Analog Arrays: A Floating-Gate Approach." Diss., Available online, Georgia Institute of Technology, 2004:, 2004. http://etd.gatech.edu/theses/available/etd-07122004-124607/unrestricted/hall%5Ftyson%5Fs%5F200407%5Fphd.pdf.

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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005. Directed by David Anderson.<br>Prvulovic, Milos, Committee Member ; Citrin, David, Committee Member ; Lanterman, Aaron, Committee Member ; Yalamanchili, Sudhakar, Committee Member ; Hasler, Paul, Committee Member ; Anderson, David, Committee Chair. Includes bibliographical references.

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3

Leong, David Chin Kuang. "Incremental placement for field-programmable gate arrays." Thesis, University of British Columbia, 2006. http://hdl.handle.net/2429/31671.

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As the logic capacity of FPGAs continues to increase with deep submicron technology, performing a full recompilation for small iterative changes in a large design is an extremely time-consuming and costly process. To address this issue, this thesis presents a new incremental placement algorithm for FPGAs named "iPlace" that significantly reduces the time required for recompilation. The iPlace algorithm is based on shifting, compaction, and annealing. Key ideas from the algorithm include a placement super-grid that is larger than the physical size of the FPGA. The super-grid allows insert

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4

Messa, Norman C. "Design implementation into field programmable gate arrays." Thesis, Monterey, California. Naval Postgraduate School, 1991. http://hdl.handle.net/10945/26451.

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5

Niu, Jianyong. "Digital control using field programmable gate arrays." Thesis, University of Sheffield, 2006. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.434507.

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6

Lu, Aiguo. "Logic synthesis for field programmable gate arrays." Thesis, University of Bristol, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.295061.

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7

Newalkar, Aditya. "Alternative techniques for Built-In Self-Test of Field Programmable Gate Arrays." Auburn, Ala., 2005. http://repo.lib.auburn.edu/2005%20Summer/master's/NEWALKAR_ADITYA_6.pdf.

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8

Карнаушенко, В. П., and А. В. Бородин. "Field Programmable Counter Arrays Integration with Field Programmable Gates Arrays." Thesis, NURE, MC&FPGA, 2019. https://mcfpga.nure.ua/conf/2019-mcfpga/10-35598-mcfpga-2019-004.

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Field Programmable Counter Arrays (FPCAs) have been recently introduced to close the gap between Field Programmable Gates Arrays (FPGA) and Application Specified Integrated Circuits (ASICs) for arithmetic dominated applications. FPCAs are reconfigurable lattices that can be embedded into FPGAs to efficiently compute the result of multi-operand additions.

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9

Vachranukunkiet, Petya Nagvajara Prawat Johnson Jeremy. "Power flow computation using field programmable gate arrays /." Philadelphia, Pa. : Drexel University, 2007. http://hdl.handle.net/1860/1789.

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10

Camus, Dominic Roger. "Improved logic optimisation for field programmable gate arrays." Thesis, University of Oxford, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.301840.

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11

James, Calvin L. "COMPLEX WAVEFORM GENERATION UTILIZING FIELD PROGRAMMABLE GATE ARRAYS." International Foundation for Telemetering, 1997. http://hdl.handle.net/10150/609692.

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International Telemetering Conference Proceedings / October 27-30, 1997 / Riviera Hotel and Convention Center, Las Vegas, Nevada<br>The basic building blocks for implementing complex waveform generators using a look-up table approach are random access memory (RAM) and read only memory (ROM) devices. Due to technological advancements in field programmable gate array (FPGA) development, these devices have the ability to allocate large amounts of memory elements within the same structure. The self containment property makes the FPGA a suitable topology for complex waveform generation applications

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12

Malik, Usama Computer Science &amp Engineering Faculty of Engineering UNSW. "Configuration encoding techniques for fast FPGA reconfiguration." Awarded by:University of New South Wales. School of Computer Science and Engineering, 2006. http://handle.unsw.edu.au/1959.4/26212.

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This thesis examines the problem of reducing reconfiguration time of an island-style FPGA at its configuration memory level. The approach followed is to examine configuration encoding techniques in order to reduce the size of the bitstream that must be loaded onto the device to perform a reconfiguration. A detailed analysis of a set of benchmark circuits on various island-style FPGAs shows that a typical circuit randomly changes a small number of bits in the {\it null} or default configuration state of the device. This feature is exploited by developing efficient encoding schemes for configur

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13

Koh, Shannon Computer Science &amp Engineering Faculty of Engineering UNSW. "Generating the communication infrastracture for module-based dynamic reconfiguration of FPGas." Publisher:University of New South Wales. Computer Science & Engineering, 2008. http://handle.unsw.edu.au/1959.4/41418.

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Current approaches to supporting module-based FPGA reconfiguration focus on various aspects and sub-problems in the area but do not combine to form a coherent, top-down methodology that factors low-level device parameters into every step of the design flow. This thesis proposes such a top-down methodology from application specification to low-level implementation, centered around examining the problem of generating a point-to-point communications infrastructure to support the changing interfaces of dynamically placed modules. Low-level implementation parameters are considered at every stage to

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14

Wood, Christopher Landon. "Runtime partial FPGA reconfiguration." Thesis, Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/15051.

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15

Galindo, Juan Manuel. "A novel partial reconfiguration methodology for FPGAs of multichip systems /." Online version of thesis, 2008. http://hdl.handle.net/1850/7784.

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16

Rajagopalan, Kamal. "An FPGA architecture for improved arithmetic performance /." St. Lucia, Qld, 2001. http://www.library.uq.edu.au/pdfserve.php?image=thesisabs/absthe16460.pdf.

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17

Gray, Jordan D. "Application of Floating-Gate Transistors in Field Programmable Analog Arrays." Thesis, Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7540.

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Floating-gate transistors similar to those used in FLASH and EEPROM can be used to build reconfigurable analog arrays. The charge on the floating gate can be modified to pass or block a signal in a cross-bar switch matrix, or it can be finely tuned to eliminate a threshold difference across a chip or set a bias. By using such a compact and versatile reconfigurable analog memory element, the number of analog circuit components included on an integrated circuit that is field-programmable is significantly higher. As a result, large-scale FPAAs can be built with the same impact on analog design

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18

Källström, Petter. "Direct Digital Frequency Synthesis in Field-Programmable Gate Arrays." Thesis, Linköping University, Department of Electrical Engineering, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-56550.

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<p>This thesis is about creation of a Matlab program that suggests and automatically generates a Phase to Sine Amplitude Converter (PSAC) in the hardware language VHDL, suitable for Direct Digital Frequency Synthesis (DDFS). Main hardware target is Field Programmable Gate Arrays (FPGAs).</p><p>Focus in this report is how an FPGA works, different methods for sine amplitude generation and their signal qualities vs the hardware resources they use.</p><br><p>Detta exjobb handlar om att skapa ett Matlab-program som föreslår och implementerar en sinusgenerator i hårdvaruspråket VHDL, avsedd för digi

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19

Mutlu, Baris Ragip. "Real-time Motion Control Using Field Programmable Gate Arrays." Master's thesis, METU, 2010. http://etd.lib.metu.edu.tr/upload/12612049/index.pdf.

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In this thesis, novel implementation methods for FPGA based real-time motion control systems are investigated. These methods are examined for conventional and modern controller topologies as well as peripheral device interfaces which are mutually essential pieces of a motion controller. The developed methods are initially tested one by one to assess the performance of the individual design<br>and finally an assembled solution is developed to test the overall design. Tests of the overall design are realized via hardware-in-the-loop simulation of a real-world control problem, selected as a CNC m

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20

Raina, Baljit Singh. "Delay-optimized placement in symmetrical field-programmable gate arrays." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp01/MQ31862.pdf.

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21

Tickle, Andrew Jason. "Applications of Morphological Operators on Field Programmable Gate Arrays." Thesis, University of Liverpool, 2009. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.507628.

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22

Ambat, Shadab Gopinath. "SINGLE EVENT UPSET DETECTION IN FIELD PROGRAMMABLE GATE ARRAYS." UKnowledge, 2008. http://uknowledge.uky.edu/gradschool_theses/511.

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The high-radiation environment in space can lead to anomalies in normal satellite operation. A major cause of concern to spacecraft-designers is the single event upset (SEU). SEUs can result in deviations from expected component behavior and are capable of causing irreversible damage to hardware. In particular, Field Programmable Gate Arrays (FPGAs) are known to be highly susceptible to SEUs. Radiation-hardened versions of such devices are associated with an increase in power consumption and cost in addition to being technologically inferior when compared to contemporary commercial-off-the-she

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23

Self, R. P. "Software-orientated system design for field programmable gate arrays." Thesis, University of Essex, 2004. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.397736.

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24

Sharma, Akshay. "Place and route techniques for FPGA architecture advancement /." Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/6108.

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25

Shen, Ying. "Compiling a synchronous programming language into field programmable gate arrays." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape8/PQDD_0029/MQ47476.pdf.

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26

Sareen, Aman. "Reconfigurable design for pattern recognition using field programmable gate arrays." Ohio : Ohio University, 1999. http://www.ohiolink.edu/etd/view.cgi?ohiou1175625525.

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27

Dixon, Bobby Earl Stroud Charles E. "Built-in self-test of the programmable interconnect in field programmable gate arrays." Auburn, Ala, 2008. http://repo.lib.auburn.edu/EtdRoot/2008/FALL/Electrical_and_Computer_Engineering/Thesis/Dixon_Bobby_16.pdf.

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28

Brown, Simon James. "Fault-tolerance of field-programmable gate arrays subjected to radiation." Thesis, University of Salford, 2010. http://usir.salford.ac.uk/26592/.

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This thesis describes a technology and methodology designed and developed for the study of certain aspects of reliability in digital electronics sub-systems, as implemented on field-programmable gate arrays (FPGAs), while being subjected to small-scale sources of radiation. The technology developed is in the form of a platform for the FPGA under investigation, and an associated configuration and test system. The platforms for the devices are exchangeable, so that a range of different generations, manufacturers and models of FPGA, or other processing element, can be investigated. The circuit bo

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29

MacQueen, Daniel Montgomery. "Total ionizing dose effects on Xilinx field-programmable gate arrays." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2000. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp01/MQ59840.pdf.

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30

Royal, Andrew Peter. "Globally asynchronous locally synchronous interconnect for field programmable gate arrays." Thesis, Imperial College London, 2005. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.415717.

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31

Gundam, Madhuri. "Implementation of Directional Median Filtering using Field Programmable Gate Arrays." ScholarWorks@UNO, 2010. http://scholarworks.uno.edu/td/111.

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Median filtering is a non-linear filtering technique which is effective in removing impulsive noise from data. In this thesis, directional median filtering has been implemented using cumulative histogram of samples in several directions. Different methods to implement directional median filtering have been proposed. The filtered images are smoothed along the direction of the filtering window. All implementations aimed to generate outputs in the least amount of time, while reducing the resource utilization on hardware. The implementation methods were designed for Xilinx Virtex 5 FPGA devices bu

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32

Davis, James. "Low-overhead fault-tolerant logic for field-programmable gate arrays." Thesis, Imperial College London, 2015. http://hdl.handle.net/10044/1/44382.

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While allowing for the fabrication of increasingly complex and efficient circuitry, transistor shrinkage and count-per-device expansion have major downsides: chiefly increased variation, degradation and fault susceptibility. For this reason, design-time consideration of faults will have to be given to increasing numbers of electronic systems in the future to ensure yields, reliabilities and lifetimes remain acceptably high. Many mathematical operators commonly accelerated in hardware are suited to modification resulting in datapath error detection and correction capabilities with far lower are

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33

Papadonikolakis, Markos. "Mapping of support vector machines on field programmable gate arrays." Thesis, Imperial College London, 2012. http://hdl.handle.net/10044/1/10004.

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Support Vector Machines (SVMs) are a powerful supervised learning method in the field of Machine Learning, which has drawn a lot of attention in the last two decades due to their high effectiveness and demonstrated prediction accuracy for a wide range of classification and regression tasks. Belonging to the class of supervised learning, this method comprises of two distinct phases, the SVM training and classification. When targeting large-scale problems, both SVM training and classification phases suffer from high execution times, due to their superlinear dependencies on the problem’s dimensio

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34

Potgieter, Juan-Pierre. "Single event upset testing of flash based field programmable gate arrays." Thesis, Nelson Mandela Metropolitan University, 2015. http://hdl.handle.net/10948/12520.

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In the last 50 years microelectronics have advanced at an exponential rate, causing microelectronic devices to shrink, have very low operating voltages and increased complexities; all this has made circuits more sensitive to various kinds of failures. These trends allowed soft errors, which up until recently was just a concern for space application, to become a major source of system failures of electronic products. The aim of this research paper was to investigate different mitigation techniques that prevent these soft errors in a Video Graphics Array (VGA) controller which is commonly used i

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35

Ortiz, Gual Fernando Enrique. "Novel reconfigurable computing architectures for embedded high performance signal processing and numerical applications." Access to citation, abstract and download form provided by ProQuest Information and Learning Company; downloadable PDF file 1.73 Mb., 102 p, 2006. http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&res_dat=xri:pqdiss&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&rft_dat=xri:pqdiss:3221141.

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36

Milton, Daniel. "Built-in self test of configurable memory resources in field programmable gate arrays." Auburn, Ala., 2007. http://repo.lib.auburn.edu/07M%20Theses/MILTON_DANIEL_9.pdf.

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37

Lin, Yu Colin, and 林郁. "ArchSyn: an energy-efficient FPGA high-level synthesizer." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2012. http://hub.hku.hk/bib/B49799599.

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Due to their high potential performance and reduced energy and power consumption, field-programmable gate arrays (FPGAs) are widely used as accelerators for today’s computationally intensive applications. These applications use advanced algorithms more sophisticated than ever before. The high design complexity along with fast development process challenges the traditional FPGA design methodology using hardware description languages. High-level synthesis accelerates design implementation by raising the level of design abstraction beyond register transfer level. This dissertation work develops

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38

Hauck, Scott. "Multi-FPGA systems /." Thesis, Connect to this title online; UW restricted, 1995. http://hdl.handle.net/1773/7008.

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39

Johnson, Steven A. "Implementation of a configurable fault tolerant processor (CFTP)." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2003. http://library.nps.navy.mil/uhtbin/hyperion-image/03Mar%5FJohnson.pdf.

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Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, March 2003.<br>Thesis advisor(s): Herschel H. Loomis, Alan A. Ross. Includes bibliographical references (p. 117). Also available online.

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40

Han, Yi. "Development of nonlinear reconfigurable control of reconfigurable plants using the FPGA technology." Thesis, [S.l. : s.n.], 2008. http://dk.cput.ac.za/cgi/viewcontent.cgi?article=1011&context=td_cput.

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41

Schlottmann, Craig Richard. "Analog signal processing on a reconfigurable platform." Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/29623.

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Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010.<br>Committee Chair: Hasler, Paul; Committee Member: Anderson, David; Committee Member: Ghovanloo, Maysam. Part of the SMARTech Electronic Thesis and Dissertation Collection.

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42

Mak, Wai-kei. "Partitioning and routing for multi-FPGA systems /." Digital version accessible at:, 1998. http://wwwlib.umi.com/cr/utexas/main.

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43

Chang, Mark L. "Variable precision analysis for FPGA synthesis /." Thesis, Connect to this title online; UW restricted, 2004. http://hdl.handle.net/1773/5901.

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44

Kumar, Akhilesh. "Leakage Power Modeling and Reduction Techniques for Field Programmable Gate Arrays." Thesis, University of Waterloo, 2006. http://hdl.handle.net/10012/766.

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FPGAs have become quite popular for implementing digital circuits and systems because of reduced costs and fast design cycles. This has led to increased complexity of FPGAs, and with technology scaling, many new challenges have come up for the FPGA industry, leakage power being one of the key challenges. The current generation FPGAs are being implemented in 90nm technology, therefore, managing leakage power in deep-submicron FPGAs has become critical for the FPGA industry to remain competitive in the semiconductor market and to enter the mobile applications domain. <br /><br /> I

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45

Wilton, Steven J. E. "Architectures and algorithms for field-programmable gate arrays with embedded memory." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1997. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp03/NQ28082.pdf.

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46

Li, Wei. "Routability prediction for field programmable gate arrays with hierarchical interconnection structures." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp01/MQ31846.pdf.

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47

Dai, Zhibin. "Routability prediction for Field Programmable Gate Arrays with a routing hierarchy." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2001. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp04/MQ56315.pdf.

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48

Lamoureux, Julien. "Modeling and reduction of dynamic power in field-programmable gate arrays." Thesis, University of British Columbia, 2007. http://hdl.handle.net/2429/414.

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Field-Programmable Gate Arrays (FPGAs) are one of the most popular platforms for implementing digital circuits. Their main advantages include the ability to be (re)programmed in the field, a shorter time-to-market, and lower non-recurring engineering costs. This programmability, however, is afforded through a significant amount of additional circuitry, which makes FPGAs significantly slower and less power-efficient compared to Application Specific Integrated Circuits (ASICs). This thesis investigates three aspects of low-power FPGA design: switching activity estimation, switching activity mini

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49

Campregher, Nicola. "Interconnect yield analysis and fault tolerance for field programmable gate arrays." Thesis, Imperial College London, 2007. http://hdl.handle.net/10044/1/11966.

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50

Inuani, Maurice Kilavuka. "Technology mapping of heterogeneous lookup table based field programmable gate arrays." Thesis, University of Oxford, 1998. http://ora.ox.ac.uk/objects/uuid:8ec8745f-c0b2-43c0-994f-bd949d9fdefa.

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A lot of work has been done over the last decade on the logic synthesis and technology mapping of field programmable gate arrays (FPGAs) based on a single size of lookup table (LUT). A significant part of the FPGA market is occupied by devices based on more than one type of lookup tables. Examples of these heterogeneous LUT-based FPGAs are the Xilinx 4000 series devices. The technology mapping for this class of FPGAs has hardly been considered. This thesis covers work on the synthesis for heterogeneous LUT-based FPGAs. The proposed scheme uses the typical steps of graph covering, decomposition

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