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Articoli di riviste sul tema "Field Programmable Gate Arrays"

Autore: Grafiati
Pubblicato: 4 giugno 2021
Ultima modifica: 25 luglio 2025

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1

Marchal, Pierre. "Field-programmable gate arrays." Communications of the ACM 42, no. 4 (1999): 57–59. http://dx.doi.org/10.1145/299157.299594.

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2

Verma, H. "Field programmable gate arrays." IEEE Potentials 18, no. 4 (1999): 34–36. http://dx.doi.org/10.1109/45.796099.

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3

Lombardi, F. "Field Programmable Gate-Arrays." IEEE Design & Test of Computers 15, no. 1 (1998): 8–9. http://dx.doi.org/10.1109/mdt.1998.655176.

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4

Bhatia, Dinesh. "Field-Programmable Gate Arrays." VLSI Design 4, no. 4 (1996): i—ii. http://dx.doi.org/10.1155/1996/87608.

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5

Hurst, S. L. "Field programmable gate arrays." Microelectronics Journal 28, no. 1 (1997): 102. http://dx.doi.org/10.1016/s0026-2692(97)87854-8.

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6

Hurst, S. L. "Field-programmable gate arrays." Microelectronics Journal 25, no. 1 (1994): 77–78. http://dx.doi.org/10.1016/0026-2692(94)90166-x.

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7

Jay, Christopher. "Field programmable gate arrays." Microprocessors and Microsystems 17, no. 7 (1993): 370. http://dx.doi.org/10.1016/0141-9331(93)90058-f.

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8

Greene, J., E. Hamdy, and S. Beal. "Antifuse field programmable gate arrays." Proceedings of the IEEE 81, no. 7 (1993): 1042–56. http://dx.doi.org/10.1109/5.231343.

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9

Leon, A. F. "Field programmable gate arrays in space." IEEE Instrumentation & Measurement Magazine 6, no. 4 (2003): 42–48. http://dx.doi.org/10.1109/mim.2003.1251482.

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10

Rose, J., A. El Gamal, and A. Sangiovanni-Vincentelli. "Architecture of field-programmable gate arrays." Proceedings of the IEEE 81, no. 7 (1993): 1013–29. http://dx.doi.org/10.1109/5.231340.

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11

Reena, Kulkarni, and Keerti Kulkarni Dr. "Cryptography with Field Programmable Gate Arrays." International Journal of Innovative Science and Research Technology (IJISRT) 10, no. 2 (2025): 356–59. https://doi.org/10.5281/zenodo.14910222.

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Abstract (sommario):
Cryptography is an important process of modern secure communication, and as the need for faster and more efficient encryption methods grows, hardware-based solutions have become significant. Field-Programmable Gate Arrays (FPGAs) offer flexible and efficient platform for implementing cryptographic systems and hence a promising solution for securing modern digital communications like, in Internet of Things and embedded system applications. This paper discusses the different cryptographic algorithms and how FPGAs are advantageous over other hardware-based security implementations.
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12

Sergienko, Anatolij M., Vitalij O. Romankevich, and Pavlo A. Serhiienko. "Image buffering in application specific processors." Applied Aspects of Information Technology 5, no. 3 (2022): 228–39. http://dx.doi.org/10.15276/aait.05.2022.16.

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Abstract (sommario):
In many digital image-processingapplications, which are implementedin field programmable gate arrays,the currently processed image's frames are stored in external dynamic memory.The performance of such an application dependson the dynamic memoryspeed and the necessaryrequests quantity during algorithm’sruntime. This performance is being optimized through field programmable gate arrays -implemented buffer memory usage.But there is no common method for the formal buffer memory synthesis with preset throughput, input and output data sequenceorderand minimizedhardwarecosts.In this article,the feat
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13

Leeser, Miriam, Scott Hauck, and Russell Tessier. "Field-Programmable Gate Arrays in Embedded Systems." EURASIP Journal on Embedded Systems 2006, no. 1 (2006): 051312. http://dx.doi.org/10.1186/1687-3963-2006-051312.

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14

Dettmer, R. "Onwards and upwards [field programmable gate arrays]." IEE Review 51, no. 12 (2005): 40–43. http://dx.doi.org/10.1049/ir:20051204.

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15

Ting-Ting Hwang, R. M. Owens, M. J. Irwin, and Kuo Hua Wang. "Logic synthesis for field-programmable gate arrays." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 13, no. 10 (1994): 1280–87. http://dx.doi.org/10.1109/43.317471.

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16

Dasgupta, S., and D. Cussans. "Field Programmable Gate Arrays—Detecting Cosmic Rays." Journal of Instrumentation 10, no. 07 (2015): C07006. http://dx.doi.org/10.1088/1748-0221/10/07/c07006.

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17

Erbagci, Burak, Nail Etkin Can Akkaya, Mudit Bhargava, Rachel Dondero, and Ken Mai. "Secure hardware-entangled field programmable gate arrays." Journal of Parallel and Distributed Computing 131 (September 2019): 81–96. http://dx.doi.org/10.1016/j.jpdc.2019.04.002.

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18

Mintzer, Les. "FIR filters with field-programmable gate arrays." Journal of VLSI signal processing systems for signal, image and video technology 6, no. 2 (1993): 119–27. http://dx.doi.org/10.1007/bf01607876.

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19

Hurst, S. L. "Logic synthesis for field-programmable gate arrays." Microelectronics Journal 27, no. 8 (1996): 803–4. http://dx.doi.org/10.1016/0026-2692(96)82780-7.

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20

Leeser, Miriam, Scott Hauck, and Russell Tessier. "Field-Programmable Gate Arrays in Embedded Systems." EURASIP Journal on Embedded Systems 2006 (2006): 1–2. http://dx.doi.org/10.1155/es/2006/51312.

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21

AHUJA, SUMIT, and S. K. BALASUBRAMANIAN. "Field Programmable Gate Arrays Based Overcurrent Relays." Electric Power Components and Systems 32, no. 3 (2004): 247–55. http://dx.doi.org/10.1080/15325000490207769.

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22

Sangiovanni-Vincentelli, A., A. El Gamal, and J. Rose. "Synthesis method for field programmable gate arrays." Proceedings of the IEEE 81, no. 7 (1993): 1057–83. http://dx.doi.org/10.1109/5.231344.

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23

Louie, Marianne E., and Milos D. Ercegovac. "Implementing division with field programmable gate arrays." Journal of VLSI signal processing systems for signal, image and video technology 7, no. 3 (1994): 271–85. http://dx.doi.org/10.1007/bf02409403.

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24

Iranian, Mohamad Esmaeil, Elyas Zamiri, and Angel de Castro. "Optimal Implementation of d-q Frame Finite Control Set Model Predictive Control with LabVIEW." Electronics 14, no. 1 (2024): 100. https://doi.org/10.3390/electronics14010100.

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Abstract (sommario):
Finite Control Set Model Predictive Control emerges as a promising method for controlling power electronics inverters, outperforming traditional linear techniques. However, implementing Finite Control Set Model Predictive Control on conventional processors faces a significant computational burden due to its repetitive nature. This paper presents a novel approach that utilizes LabVIEW & Field Programmable Gate Arrays to address this computational bottleneck. By capitalizing on the inherent parallelism and suitability of Field Programmable Gate Arrays for discrete control problems, substanti
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25

Jaafar, Anuar, Norhayati Soin, Sharifah F. Wan Muhamad Hatta, Sani Irwan Salim, and Zahriladha Zakaria. "Multipoint Detection Technique with the Best Clock Signal Closed-Loop Feedback to Prolong FPGA Performance." Applied Sciences 11, no. 14 (2021): 6417. http://dx.doi.org/10.3390/app11146417.

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Abstract (sommario):
The degradation effect of a field-programmable gate array becomes a significant issue due to the high density of logic circuits inside the field-programmable gate array. The degradation effect occurs because of the rapid technology scaling process of the field-programmable gate array while sustaining its performance. One parameter that causes the degradation effect is the delay occurrence caused by the hot carrier injection and negative bias temperature instability. As such, this research proposed a multipoint detection technique that detects the delay occurrence caused by the hot carrier inje
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26

Manasi, R. Mali* Dr. S.D Pable Prof R.S Khule. "PERFORMANCE OPTIMIZATION OF LUT IN FPGA USING CNFET." INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY 5, no. 8 (2016): 761–67. https://doi.org/10.5281/zenodo.60127.

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Abstract (sommario):
A Leakage power dissipation is becoming a concern in field-programmable gate arrays (FPGAs) due to scaling in FPGA technology. Field programmable gate arrays (FPGAs) are the implementation platform of choice when it comes to design flexibility. However, the high power consumption of FPGAs (which arises due to their flexible structure), make them less appealing for extreme low power applications hence it is important to investigate ways of reducing FPGA power consumption. This paper proposes an energy efficient dual-threshold CarbonNanotube Field Effect Transistor (CNFET) based architecture of
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27

Ogurtsov, A. A. "Conducting functional control of field-programmable gate arrays." VESTNIK of Samara University. Aerospace and Mechanical Engineering 16, no. 4 (2018): 137. http://dx.doi.org/10.18287/2541-7533-2017-16-4-137-146.

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28

Brown, S., J. Rose, and Z. G. Vranesic. "A detailed router for field-programmable gate arrays." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 11, no. 5 (1992): 620–28. http://dx.doi.org/10.1109/43.127623.

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29

Reiss, G., and D. Meyners. "Reliability of field programmable magnetic logic gate arrays." Applied Physics Letters 88, no. 4 (2006): 043505. http://dx.doi.org/10.1063/1.2167609.

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30

Lum, G. K., R. J. May, and L. E. Robinette. "Total dose hardness of field programmable gate arrays." IEEE Transactions on Nuclear Science 41, no. 6 (1994): 2487–93. http://dx.doi.org/10.1109/23.340606.

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31

Joginipelly, Arjun Kumar, and Dimitrios Charalampidis. "Efficient separable convolution using field programmable gate arrays." Microprocessors and Microsystems 71 (November 2019): 102852. http://dx.doi.org/10.1016/j.micpro.2019.102852.

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32

Bogdan, IstvÁn A., Daniel Coca, and Rob J. Beynon. "Peptide Mass Fingerprinting Using Field-Programmable Gate Arrays." IEEE Transactions on Biomedical Circuits and Systems 3, no. 3 (2009): 142–49. http://dx.doi.org/10.1109/tbcas.2008.2010945.

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33

Yazdanshenas, Sadegh, and Vaughn Betz. "Interconnect Solutions for Virtualized Field-Programmable Gate Arrays." IEEE Access 6 (2018): 10497–507. http://dx.doi.org/10.1109/access.2018.2806618.

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34

Howard, N. J., A. M. Tyrrell, and N. M. Allinson. "The yield enhancement of field-programmable gate arrays." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2, no. 1 (1994): 115–23. http://dx.doi.org/10.1109/92.273147.

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35

Fagin, B., and C. Renard. "Field programmable gate arrays and floating point arithmetic." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2, no. 3 (1994): 365–67. http://dx.doi.org/10.1109/92.311646.

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36

Yen-Tai Lai and Ping-Tsung Wang. "Hierarchical interconnection structures for field programmable gate arrays." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 5, no. 2 (1997): 186–96. http://dx.doi.org/10.1109/92.585219.

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37

Banerjee, P., D. Saha, and S. Sur-Kolay. "Cone-based placement for field programmable gate arrays." IET Computers & Digital Techniques 5, no. 1 (2011): 49. http://dx.doi.org/10.1049/iet-cdt.2009.0058.

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38

VENKATESWARAN, N., S. PATTABIRAMAN, J. DESOUZA, et al. "A DESIGN METHODOLOGY FOR VERY LARGE ARRAY PROCESSORS-PART 2: PACUBE VLSI ARRAYS." International Journal of Pattern Recognition and Artificial Intelligence 09, no. 02 (1995): 263–301. http://dx.doi.org/10.1142/s0218001495000134.

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Abstract (sommario):
The types of functional VLSI chips needed for general and special purpose (computationally intensive) applications are wide ranging, Hence, to reduce the turn-around time of these VLSI chips, mask/field programmable PLAs, gate arrays SLAs and FPGAs are available. However these VLSI arrays are unsuitable for designing ultrahigh performance special purpose VLSI chips. There is a strong need for developing a suitable mask programmable VLSI structures exclusively for designing ultrahigh performance and cost-effective special purpose systems. For this purpose, a macro cell based mask programmable P
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39

McNelles, Phillip, and Lixuan Lu. "ICONE23-1171 DESIGN OF A TRITIUM-IN-AIR-MONITOR USING FIELD PROGRAMMABLE GATE ARRAYS." Proceedings of the International Conference on Nuclear Engineering (ICONE) 2015.23 (2015): _ICONE23–1—_ICONE23–1. http://dx.doi.org/10.1299/jsmeicone.2015.23._icone23-1_93.

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40

Amer Abbas, Yasir, Razali Jidin, Norziana Jamil, Muhammad Reza Z\'aba, and Mohd Ezanee Rusli. "PRINCE IP-core on Field Programmable Gate Arrays (FPGA)." Research Journal of Applied Sciences, Engineering and Technology 10, no. 8 (2015): 914–22. http://dx.doi.org/10.19026/rjaset.10.2447.

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41

Rais. "Field Programmable Gate Arrays Based Realization of Truncated Multipliers." American Journal of Applied Sciences 8, no. 7 (2011): 681–84. http://dx.doi.org/10.3844/ajassp.2011.681.684.

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42

Ababei, Cristinel, Shaun Duerr, William Joseph Ebel Jr., Russell Marineau, Milad Ghorbani Moghaddam, and Tanzania Sewell. "Open Source Digital Camera on Field Programmable Gate Arrays." International Journal of Handheld Computing Research 7, no. 4 (2016): 30–40. http://dx.doi.org/10.4018/ijhcr.2016100103.

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Abstract (sommario):
We present an open source digital camera implemented on a field programmable gate array (FPGA). The camera functionality is completely described in VHDL and tested on the DE2-115 educational FPGA board. Some of the current features of the camera include video mode at 30 fps, storage of taken snapshots into SDRAM memories, and grayscale and edge detection filters. The main contributions of this project include 1) the actual system level design of the camera, tested and verified on an actual FPGA chip, and 2) the public release of the entire implementation including source code and documentation
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43

Chan, P. K., M. D. F. Schlag, C. Ebeling, and L. McMurchie. "Distributed-memory parallel routing for field-programmable gate arrays." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 19, no. 8 (2000): 850–62. http://dx.doi.org/10.1109/43.856973.

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44

Fei Li, Y. Lin, Lei He, Deming Chen, and J. Cong. "Power modeling and characteristics of field programmable gate arrays." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 24, no. 11 (2005): 1712–24. http://dx.doi.org/10.1109/tcad.2005.852293.

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45

Teng, Bill, and J. H. Anderson. "Latch-Based Performance Optimization for Field-Programmable Gate Arrays." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 32, no. 5 (2013): 667–80. http://dx.doi.org/10.1109/tcad.2012.2235913.

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46

Poon, Kara K. W., Steven J. E. Wilton, and Andy Yan. "A detailed power model for field-programmable gate arrays." ACM Transactions on Design Automation of Electronic Systems 10, no. 2 (2005): 279–302. http://dx.doi.org/10.1145/1059876.1059881.

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47

Lai, Y. T., and C. C. Kao. "Technology mapping algorithm for heterogeneous field programmable gate arrays." IEE Proceedings - Computers and Digital Techniques 149, no. 6 (2002): 249. http://dx.doi.org/10.1049/ip-cdt:20020748.

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48

MacQueen, D. M., D. M. Gingrich, and N. J. Buchanan. "Ionizing radiation effects in XC4036X field programmable gate arrays." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 479, no. 2-3 (2002): 603–10. http://dx.doi.org/10.1016/s0168-9002(01)00947-0.

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49

Conti, Vincenzo, Carmelo Militello, Filippo Sorbello, and Salvatore Vitabile. "Biometric sensors rapid prototyping on field-programmable gate arrays." Knowledge Engineering Review 30, no. 2 (2015): 201–19. http://dx.doi.org/10.1017/s0269888914000307.

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AbstractBiometric user authentication in large-scale distributed systems involves passive scanners and networked workstations and databases for user data acquisition, processing, and encryption. Unfortunately, traditional biometric authentication systems are prone to several attacks, such as Replay Attacks, Communication Attacks, and Database Attacks. Embedded biometric sensors overcome security limits of conventional software recognition systems, hiding its common attack points. The availability of mature reconfigurable hardware technology, such as field-programmable gate arrays, allows the d
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50

López, Aitor, Daniel Pérez, Prometheus DasMahapatra, and José Capmany. "Auto-routing algorithm for field-programmable photonic gate arrays." Optics Express 28, no. 1 (2020): 737. http://dx.doi.org/10.1364/oe.382753.

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