Gotowe bibliografie tematyczne / 22-nm technology node

Spis treści

  1. Artykuły w czasopismach
  2. Rozprawy doktorskie
  3. Książki
  4. Części książek
  5. Streszczenia konferencji

Gotowa bibliografia na temat „22-nm technology node”

Autor: Grafiati
Data publikacji: 6 września 2023
Data aktualizacji: 31 lipca 2025

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Artykuły w czasopismach na temat "22-nm technology node"

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Li, Zongru, Christopher Jarrett Elash, Chen Jin, et al. "Comparison of Total Ionizing Dose Effects in 22-nm and 28-nm FD SOI Technologies." Electronics 11, no. 11 (2022): 1757. http://dx.doi.org/10.3390/electronics11111757.

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Total ionizing dose (TID) effects from Co-60 gamma ray and heavy ion irradiation were studied at the 22-nm FD SOI technology node and compared with the testing results from the 28-nm FD SOI technology. Ring oscillators (RO) designed with inverters, NAND2, and NOR2 gates were used to observe the output frequency drift and current draw. Experimental results show a noticeable increased device current draw and decreases in RO frequencies where NOR2 ROs have the most degradation. As well, the functionality of a 256 kb SRAM block and shift-register chains were evaluated during C0-60 irradiation. SRA
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Das, Pankaj Kumar, Anurag Yadav, and Nidhi Chandra. "Analysis of Delay and Dynamic Crosstalk in Spatially Arranged Mixed CNT Bundle Interconnects at Different Technology Nodes." Key Engineering Materials 994 (November 5, 2024): 39–45. http://dx.doi.org/10.4028/p-vcvy4l.

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In the present nanoscale regime, mixed carbon nanotube bundles (MCBs) are considered to be highly promising interconnect options. This research paper introduces a spatially arranged mixed carbon nanotubes (CNTs) bundle (MCB), wherein single-walled CNTs (SWCNTs) and multi-walled CNTs (MWCNTs) occupy equal halves in the MCB. An equivalent single conductor (ESC) model for MCB is employed to analyze the interconnect performances in terms of signal transmission delay and dynamic crosstalk delay at different technology nodes (i.e., 32nm, 22nm, and 16 nm). Encouragingly, a significant reduction in si
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Xu, Peng, Yinghua Piao, Liang Ge, et al. "Investigation of Novel Junctionless MOSFETs for Technology Node Beyond 22 nm." ECS Transactions 44, no. 1 (2019): 33–39. http://dx.doi.org/10.1149/1.3694293.

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Holmes, Steven. "22-nm-node technology active-layer patterning for planar transistor devices." Journal of Micro/Nanolithography, MEMS, and MOEMS 9, no. 1 (2010): 013001. http://dx.doi.org/10.1117/1.3302125.

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Saxena, Shubhangi, and Kamsali Manjunathachari. "Novel Nanoelectronic Materials and Devices: For Future Technology Node." ECS Transactions 107, no. 1 (2022): 15701–11. http://dx.doi.org/10.1149/10701.15701ecst.

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Since the last six decades, technology node has grown smaller from micrometer to nanometer dimensions. In continuation of Moore's Law, the research is going on for device/supply voltage shrinking to go beyond 22 nm CMOS technology node. However, many physical and quantum challenges appear at a smaller scale, which causes shrinking beyond 22 nm critical and needs innovative materials and devices for scaling in the nanometer regime. Incorporating nanoengineered materials to realize research achievements has shown timely development with significant influence in electronic industries. These new m
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Baklanov, Mikhail R., Evgeny A. Smirnov, and Larry Zhao. "Ultra Low Dielectric Constant Materials for 22 nm Technology Node and Beyond." ECS Transactions 35, no. 4 (2019): 717–28. http://dx.doi.org/10.1149/1.3572315.

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Mitrovic, Ivona Z., and Stephen Hall. "Rare Earth Silicate Formation: A Route Towards High-k for the 22 nm Node and Beyond." Journal of Telecommunications and Information Technology, no. 4 (June 26, 2023): 560. http://dx.doi.org/10.26636/jtit.2009.4.969.

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Over the last decade there has been a significant amount of research dedicated to finding a suitable high-k/metal gate stack to replace conventional SiON/poly-Si electrodes. Materials innovations and dedicated engineering work has enabled the transition from research lab to 300 mm production a reality, thereby making high-k/metal gate technology a pathway for continued transistor scaling. In this paper, we will present current status and trends in rare earthbased materials innovations; in particular Gd-based, for the high-k/metal gate technology in the 22 nm node. Key issues and challenges for
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Huang, Zhengfeng, Yan Zhang, Wenhui Wu, et al. "A high-speed quadruple-node-upset-tolerant latch in 22 nm CMOS technology." Microelectronics Reliability 147 (August 2023): 115032. http://dx.doi.org/10.1016/j.microrel.2023.115032.

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Li, Zongru, Christopher Elash, Chen Jin, et al. "SEU performance of Schmitt-trigger-based flip-flops at the 22-nm FD SOI technology node." Microelectronics Reliability 146 (July 2023): 115033. http://dx.doi.org/10.1016/j.microrel.2023.115033.

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Lu, Peng, Can Yang, Yifei Li, Bo Li, and Zhengsheng Han. "Three-Dimensional TID Hardening Design for 14 nm Node SOI FinFETs." Eng 2, no. 4 (2021): 620–31. http://dx.doi.org/10.3390/eng2040039.

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The fin field-effect transistor (FinFET) has been the mainstream technology on the VLSI platform since the 22 nm node. The silicon-on-insulator (SOI) FinFET, featuring low power consumption, superior computational power and high single-event effect (SEE) resistance, shows advantages in integrated circuits for space applications. In this work, a rad-hard design methodology for SOI FinFETs is shown to improve the devices’ tolerance against the Total Ionizing Dose (TID) effect. Since the fin height direction enables a new dimension for design optimization, a 3D Source/Drain (S/D) design combined
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Rozprawy doktorskie na temat "22-nm technology node"

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Bansal, Anil Kumar. "CMOS scaling considerations in sub 10-nm node multiple-gate FETS." Thesis, IIT Delhi, 2019. http://eprint.iitd.ac.in:80//handle/2074/8046.

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Książki na temat "22-nm technology node"

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Wang, Guilei. Investigation on SiGe Selective Epitaxy for Source and Drain Engineering in 22 nm CMOS Technology Node and Beyond. Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-15-0046-6.

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Wang, Guilei. Investigation on SiGe Selective Epitaxy for Source and Drain Engineering in 22 nm CMOS Technology Node and Beyond. Springer, 2019.

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Wang, Guilei. Investigation on Sige Selective Epitaxy for Source and Drain Engineering in 22 Nm CMOS Technology Node and Beyond. Springer Singapore Pte. Limited, 2020.

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Balasinski, Artur. Design for Manufacturability: From 1d to 4D for 90 22 NM Technology Nodes. Springer New York, 2016.

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Balasinski, Artur. Design for Manufacturability: From 1D to 4D for 90–22 nm Technology Nodes. Springer, 2013.

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Balasinski, Artur. Design for Manufacturability: From 1D to 4D for 90-22 Nm Technology Nodes. Springer London, Limited, 2013.

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Części książek na temat "22-nm technology node"

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Wang, Guilei. "Strained Silicon Technology." In Investigation on SiGe Selective Epitaxy for Source and Drain Engineering in 22 nm CMOS Technology Node and Beyond. Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-15-0046-6_2.

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Kaur, Ravneet, Charu Madhu, and Deepti Singh. "Impact of Buried Oxide Layer Thickness on the Performance Parameters of SOI FinFET at 22 nm Node Technology." In Advances in Intelligent Systems and Computing. Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-5903-2_54.

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Wang, Guilei. "Introduction." In Investigation on SiGe Selective Epitaxy for Source and Drain Engineering in 22 nm CMOS Technology Node and Beyond. Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-15-0046-6_1.

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Wang, Guilei. "Epitaxial Growth of SiGe Thin Films." In Investigation on SiGe Selective Epitaxy for Source and Drain Engineering in 22 nm CMOS Technology Node and Beyond. Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-15-0046-6_3.

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Wang, Guilei. "SiGe S/D Integration and Device Verification." In Investigation on SiGe Selective Epitaxy for Source and Drain Engineering in 22 nm CMOS Technology Node and Beyond. Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-15-0046-6_4.

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Wang, Guilei. "Pattern Dependency of SiGe Layers Selective Epitaxy Growth." In Investigation on SiGe Selective Epitaxy for Source and Drain Engineering in 22 nm CMOS Technology Node and Beyond. Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-15-0046-6_5.

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Wang, Guilei. "Conclusions and Prospects." In Investigation on SiGe Selective Epitaxy for Source and Drain Engineering in 22 nm CMOS Technology Node and Beyond. Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-15-0046-6_6.

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Yin, Huaxiang, and Jiaxin Yao. "Advanced Transistor Process Technology from 22- to 14-nm Node." In Complementary Metal Oxide Semiconductor. InTech, 2018. http://dx.doi.org/10.5772/intechopen.78655.

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Streszczenia konferencji na temat "22-nm technology node"

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Gambino, J. P. "Copper interconnect technology for the 22 nm node." In 2011 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA). IEEE, 2011. http://dx.doi.org/10.1109/vtsa.2011.5872228.

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Finders, Jo, Mircea Dusa, Jan Mulkens, Yu Cao, and Maryana Escalante. "Solutions for 22-nm node patterning using ArFi technology." In SPIE Advanced Lithography. SPIE, 2011. http://dx.doi.org/10.1117/12.881598.

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Kazuya Ohuchi, Christian Lavoie, Conal E. Murray, et al. "Extendibility of NiPt silicide to the 22-nm node CMOS technology." In 2008 International Workshop on Junction Technology (IWJT). IEEE, 2008. http://dx.doi.org/10.1109/iwjt.2008.4540037.

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Kim, Ryoung-Han, Steven Holmes, Scott Halle, et al. "22 nm technology node active layer patterning for planar transistor devices." In SPIE Advanced Lithography, edited by Harry J. Levinson and Mircea V. Dusa. SPIE, 2009. http://dx.doi.org/10.1117/12.814277.

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Zhou, Renjie, Gabriel Popescu, and Lynford L. Goddard. "Finding defects in a 22 nm node wafer with visible light." In CLEO: Applications and Technology. OSA, 2013. http://dx.doi.org/10.1364/cleo_at.2013.af2j.2.

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Agarwal, Vivek Kumar, Manisha Guduri, and Aminul Islam. "Power and variability analysis of CMOS logic families @ 22-nm technology node." In 2014 3rd International Conference on Reliability, Infocom Technologies and Optimization (ICRITO) (Trends and Future Directions). IEEE, 2014. http://dx.doi.org/10.1109/icrito.2014.7014674.

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Roy, Chandaramauleshwar, and Aminul Islam. "Comparative analysis of various 9T SRAM cell at 22-nm technology node." In 2015 IEEE 2nd International Conference on Recent Trends in Information Systems (ReTIS). IEEE, 2015. http://dx.doi.org/10.1109/retis.2015.7232929.

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Gallitre, M., L. G. Gosset, A. Farcy, et al. "Performance predictions of prospective air gap architectures for the 22 nm node." In 2007 IEEE International Interconnect Technology Conferencee. IEEE, 2007. http://dx.doi.org/10.1109/iitc.2007.382374.

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Lu, Hai-Jin, Zong-Yan Pan, Pei-Yu Chen, Zhi-Cheng Zhang, and Ming-Zhi Chen. "Optimization of contact W related processes for 28/22 nm HKMG technology node." In 2021 5th IEEE Electron Devices Technology & Manufacturing Conference (EDTM). IEEE, 2021. http://dx.doi.org/10.1109/edtm50988.2021.9420977.

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Colombeau, B., T. Thanigaivelan, E. Arevalo, T. Toh, R. Miura, and H. Ito. "Ultra-shallow Carborane molecular implant for 22-nm node p-MOSFET performance boost." In 2009 International Workshop on Junction Technology (IWJT). IEEE, 2009. http://dx.doi.org/10.1109/iwjt.2009.5166211.

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