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Artykuły w czasopismach na temat "32-bit processor"
Phanindra, K. "32-Bit MIPS RISC Processor". International Journal for Research in Applied Science and Engineering Technology V, nr X (23.10.2017): 1119–23. http://dx.doi.org/10.22214/ijraset.2017.10162.
Pełny tekst źródłaHayes, W. P., R. N. Kershaw, L. E. Bays, J. R. Boddie, E. M. Fields, R. L. Freyman, C. J. Garen i in. "A 32-bit VLSI digital signal processor". IEEE Journal of Solid-State Circuits 20, nr 5 (październik 1985): 998–1004. http://dx.doi.org/10.1109/jssc.1985.1052427.
Pełny tekst źródłaTanaka, Shigeya, Takashi Hotta, Masahiro Iwamura, Tatsumi Yamauchi, Tadaaki Bandoh, Atsuo Hotta, Seiji Iwamoto i Shigemi Adachi. "A 70-MHz, 32-bit BiCMOS processor". Electronics and Communications in Japan (Part II: Electronics) 74, nr 6 (1991): 44–52. http://dx.doi.org/10.1002/ecjb.4420740605.
Pełny tekst źródłaHuang, Sheng-Chieh, Liang-Gee Chen i Thou-Ho Chen. "A 32-bit logarithmic number system processor". Journal of VLSI signal processing systems for signal, image and video technology 14, nr 3 (grudzień 1996): 311–19. http://dx.doi.org/10.1007/bf00929624.
Pełny tekst źródłaKim, Ji-Hoon, Jong-Yeol Lee i Ando Ki. "Core-A: A 32-bit Synthesizable Processor Core". IEIE Transactions on Smart Processing and Computing 4, nr 2 (30.04.2015): 83–88. http://dx.doi.org/10.5573/ieiespc.2015.4.2.083.
Pełny tekst źródłaVoevodin, V. P., V. N. Govorun, A. M. Davidenko, An V. Ekimov, N. S. Ivanova, V. I. Kovaltsov, Yu M. Kozyaev i in. "The 780/E 32-bit specialised processor-emulator". Computer Physics Communications 57, nr 1-3 (grudzień 1989): 532–35. http://dx.doi.org/10.1016/0010-4655(89)90281-6.
Pełny tekst źródłaMatsushita, Y., T. Jibiki, H. Takahashi i T. Takamizawa. "A 32/24 bit digital audio signal processor". IEEE Transactions on Consumer Electronics 35, nr 4 (1989): 785–92. http://dx.doi.org/10.1109/30.106896.
Pełny tekst źródłaAshith, M. B. "1024-Bit/2048-Bit RSA Implementation on 32-Bit Processor for Public Key Cryptography". IETE Technical Review 19, nr 4 (lipiec 2002): 203–5. http://dx.doi.org/10.1080/02564602.2002.11417032.
Pełny tekst źródłaLee, Kwang-Min, i Sungkyung Park. "Low-Gate-Count 32-Bit 2/3-Stage Pipelined Processor Design". Journal of the Institute of Electronics and Information Engineers 53, nr 4 (25.04.2016): 59–67. http://dx.doi.org/10.5573/ieie.2016.53.4.059.
Pełny tekst źródłaBurud, Mr Anand S., i Dr Pradip C. Bhaskar. "Processor Design Using 32 Bit Single Precision Floating Point Unit". International Journal of Trend in Scientific Research and Development Volume-2, Issue-4 (30.06.2018): 198–202. http://dx.doi.org/10.31142/ijtsrd12912.
Pełny tekst źródłaRozprawy doktorskie na temat "32-bit processor"
Maamar, Ali Hussein. "A 32-bit self-checking RISC processor using Dong's Code". Thesis, University of Newcastle Upon Tyne, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.285335.
Pełny tekst źródłaJönsson, Patricia. "Evaluation in which context a 32-bit, rather than an 8-bit processor may be appropriate to use, based on power consumption". Thesis, Malmö högskola, Fakulteten för teknik och samhälle (TS), 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:mau:diva-20846.
Pełny tekst źródłaThe term Internet of Things grows bigger and bigger and the world is about to have 50 billionconnected devices. IoT devices are dependent on low power consumption and thereforea low power processor is important to have. This study performs tests on two power-savingprocessors to determine which processor is most suitable for an IoT product. The test wasbased on three applications, which in turn are based on actual IoT situations. The threeapplications have different levels of intency. In the first application, the processors do notwork very hard. In the second application, the processors get more work and in the thirdapplication, the processors get the hardest work. Power consumption is measured usingAtmel Power debugger The result shows that low-active IoT devices have a lower powerconsumption with an 8-bit processor, but an IoT device that is more active has lower powerconsumption with a Cortex-M0 + based 32-bit processor.
Fang, Gloria(Gloria Yu Liang). "Instruction-level power consumption simulator for modeling simple timing and power side channels in a 32-bit RISC-V micro-processor". Thesis, Massachusetts Institute of Technology, 2021. https://hdl.handle.net/1721.1/130686.
Pełny tekst źródłaCataloged from the official PDF of thesis.
Includes bibliographical references (pages 139-140).
We create a Python based RISC-V simulator that is capable of simulating any assembly code written in RISC-V, and even perform simple power analysis of RISC-V designs. The power consumption of non-privileged RISC-V RV32IM instructions are measured experimentally, forming the basis for our simulator. These instructions include memory loads and stores, PC jumps and branches, as well as arithmetic instructions with register values. The object-oriented simulator also supports stepping and debugging. In the context of designing software for hardware use, the simulator helps assess vulnerability to side channel attacks by accepting input power consumption values. The power consumption graph of any disassembled RISC-V code can be obtained if the power consumption of each instruction is given as an input; then, from the output power consumption waveforms, we can assess how vulnerable a system is to side channel attacks. Because the power values can be customized based on what's experimentally measured, this means that our simulator can be applied to any disassembled code and to any system as long as the input power consumption of each instruction is supplied. Finally, we demonstrate an example application of the simulator on a pseudorandom function for simple side channel power analysis.
by Gloria (Yu Liang) Fang.
M. Eng.
M.Eng. Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science
Su, Chien-Chang, i 蘇健彰. "Integrated Software Development Environment for a 32-bit / 16-bit Processor Family". Thesis, 2007. http://ndltd.ncl.edu.tw/handle/3gpzv5.
Pełny tekst źródła國立中山大學
資訊工程學系研究所
95
To the general purpose microprocessors, we often need to change microprocessors’ hardware architecture because of customized purpose. But already existing application program is incompatible to the new hardware architecture, and increase the product’s development period. In this thesis, we discuss the modification of two kinds of hardware architecture, include new instruction set extension and change the size of datapath to deal with specific application. To the former, our laboratory develop a 32-bit microprocessor SYS32-TM, increase MME instruction set to deal with multimedia application. The latter, based on Thumb instruction set , we develop 16-bit microprocessor SYS16-TM, we modify its’ datapath from 32-bit to 16-bit, we will show how to let already existing application program can execute on the new hardware architecture. In SYS32-TM, we use the way of inline assembly to embedded MME instruction set in C source code, we have to modify the assembler, define and parse the MME instruction set, so the assembler can recognize it. In SYS16-TM, we have sign extension and address offset problems, we have to modify the compiler backend’s machine description to solve the sign extension and address offset instruction set behavior, and modify the library. To build SYS16-TM software environment, we have to set C Run Time Environment in Thumb mode, not support exchange between ARM mode and Thumb mode, and write the correct linker script, to set the program start address in 0x0000, to solve ARM’s initial program start address in 0x8000. As a result, In SYS32-TM, we use assembler to identify the MME instruction set can embedded in existing C source code. In SYS16-TM, we execute the testbench include sorts, Hanoi, Fibonacci number etc, and use simulator to verify its’ correctness.
Darwish, Mohammad Mostafa. "Formal verification of a 32-bit pipelined RISC processor". Thesis, 1994. http://hdl.handle.net/2429/5260.
Pełny tekst źródłaLi, Wen-jie, i 李文傑. "A Scalable RSA Cryptographic Processor with 32-Bit Modular Multiplier". Thesis, 2006. http://ndltd.ncl.edu.tw/handle/26789610187671920567.
Pełny tekst źródła國立高雄大學
電機工程學系碩士班
94
With the popularity of the portable electronic devices, the chip area and power consumption must be reduced, and because of this, we propose a scalable RSA cryptosystem chip, which is implemented with a 32-bit core. Our design provides the trade-off between security and computation time. If the security is more important, we can choose longer key to get higher security. Otherwise, the shorter key could be chosen to reduce the computation time. To realize the chip of this design, we used Cadence, Synopsys and TSMC 0.35um cell library to simulate and implement. The RSA core takes 2.55M clocks to finish a 512-bit modular exponentiation in average and the critical path delay is only 3.2 ns. The chip area is 1.81mm x 1.81mm. Since a 32-bit core is adopted, our chip has smaller area.
XIE, REN-FA, i 謝仁發. "A 32-bit hybrid floating-point binary and logarithmic number system processor". Thesis, 1990. http://ndltd.ncl.edu.tw/handle/10886867769518457164.
Pełny tekst źródłaChen, Chien-Chih, i 陳建志. "The Linux Porting and Integration Verification of An Academic 32-bit Processor". Thesis, 2012. http://ndltd.ncl.edu.tw/handle/32566192674843841485.
Pełny tekst źródła國立中山大學
資訊工程學系研究所
101
For improving the performance and application of microprocessor, it is necessary to integrate pipelined core, exception control unit, cache unit and memory management unit (MMU). The operating system is an effective way for microprocessor integration verification. However, it is not a feasible debugging methodology to detect the exact design bug while operating system booting crash. We found the main execution features of operating system are the data transfer and exception handling. We propose an integration verification methodology based on these execution features. The methodology is to verify concurrent cache transfer operation, consecutive cache transfer operation, external interrupt exception handling, page fault exception handling and multiple interrupt exception handling for microprocessor integration. We utilize ARM7-Like developed by our laboratory to do the experiment. It is effective to detect the design bugs in RTL simulation by the software-based verification methodology proposed by us. The modified ARM7-Like microprocessor is able to successfully boot Linux kernel and execute user applications in FPGA.
Peng, Yi Xiong, i 彭義雄. "ASIC Design and Implementation of 32-Bit LNS Addition and Subtraction Processor". Thesis, 1994. http://ndltd.ncl.edu.tw/handle/17662755757560652760.
Pełny tekst źródłaHsin, Wei-Kuo, i 辛威虢. "Efficient MP3 Decoder System using a 32-bit Low-Power Embedded Processor Core". Thesis, 2009. http://ndltd.ncl.edu.tw/handle/61855656677322982581.
Pełny tekst źródła國立交通大學
電子工程系所
97
This thesis presents the research result of an efficient MP3 decoder system using a 32-bit low-power embedded processor core, named ACARM9 (ACademic ARM9). The ISA (Instruction Set Architecture) of ACARM9 adopts the ARM V5E architecture but owns more efficient multiplication instructions. Hence the ADS (ARM Develop Suite) can be directly used. ADS can first be used to compile the code of high level programming language (C, C++) written by users to the assembly code, and then can assemble the assembly code to the low level machine code for ACARM9 use. It indicates the high usability of ACARM9. Moreover, this thesis presents a methodology for platform-based design. The proposed processor is mapped onto the FPGA and integrated within the ARM926EJ-S Versatile Development Board. Then an MP3 decoder system, which is capable of providing high decoding rate and playing audio synchronously, is successfully implemented using the proposed platform.
Książki na temat "32-bit processor"
Corporation, Intel. 16-/32-bit embedded processor handbook. Santa Clara, Ca: Intel Corporation, 1990.
Znajdź pełny tekst źródła(Europe), NEC Electronics. 32-bit digital signal processors data book. Düsseldorf: NEC Electronics, 1993.
Znajdź pełny tekst źródłaSmith, Simon L. Exp the Scientific Word Processor Version 5.0: 32-Bit Application for Windows 95 and Windows Nt. Brooks/Cole Pub Co, 1997.
Znajdź pełny tekst źródłaCzęści książek na temat "32-bit processor"
Civera, Pierluigi, Dante Del Corso, Gianluca Piccinini i Maurizio Zamboni. "A 32 Bit Processor for Compiled Prolog". W The Kluwer International Series in Engineering and Computer Science, 13–26. Boston, MA: Springer US, 1989. http://dx.doi.org/10.1007/978-1-4613-1619-0_2.
Pełny tekst źródłaBit, Abhishek. "64-Bit Custom Math ISA in Configurable 32-Bit RISC Processor". W Lecture Notes in Electrical Engineering, 564–75. Singapore: Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-1420-3_60.
Pełny tekst źródłaKim, Hyun-Gyu, i Hyeong-Cheol Oh. "A Low-Power DSP-Enhanced 32-Bit EISC Processor". W High Performance Embedded Architectures and Compilers, 302–16. Berlin, Heidelberg: Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/11587514_20.
Pełny tekst źródłaPatra, Sumit, Sunil Kumar, Swati Verma i Arvind Kumar. "Design and Implementation of 32-bit MIPS-Based RISC Processor". W Lecture Notes in Electrical Engineering, 747–57. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-32-9775-3_68.
Pełny tekst źródłaMangalwedhe, Sneha, Roopa Kulkarni i S. Y. Kulkarni. "Low Power Implementation of 32-Bit RISC Processor with Pipelining". W Lecture Notes in Electrical Engineering, 307–20. Singapore: Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-8234-4_27.
Pełny tekst źródłaAnjana, S. J., K. Padmakumar, Joji Daniel, L. S. Syamlal, Ganta Nagendra Mourya Teja, K. Ranjani, R. Paramasivam i M. Narayanan Namboodiripad. "Pre-Silicon Validation of 32-Bit Indigenous Processor for Space Applications". W Transactions on Computational Science and Computational Intelligence, 189–202. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-49500-8_17.
Pełny tekst źródłaLe-Huu, Khoi-Nguyen, Thanh T. Vu, Diem N. Ho i Anh-Vu Dinh-Duc. "Towards a VLIW Architecture for the 32-Bit Digital Signal Processor Core". W Lecture Notes in Electrical Engineering, 763–68. Berlin, Heidelberg: Springer Berlin Heidelberg, 2014. http://dx.doi.org/10.1007/978-3-642-41674-3_109.
Pełny tekst źródłaShashidar, R., R. Santhosh Kumar, A. M. MahalingaSwamy i M. Roopa. "FPGA Implementation of Low Power Pipelined 32-Bit RISC Processor Using Clock Gating". W Proceedings of the International Conference on Data Engineering and Communication Technology, 769–77. Singapore: Springer Singapore, 2016. http://dx.doi.org/10.1007/978-981-10-1678-3_74.
Pełny tekst źródłaTillich, Stefan, i Johann Großschädl. "Instruction Set Extensions for Efficient AES Implementation on 32-bit Processors". W Lecture Notes in Computer Science, 270–84. Berlin, Heidelberg: Springer Berlin Heidelberg, 2006. http://dx.doi.org/10.1007/11894063_22.
Pełny tekst źródłaTillich, Stefan, Christoph Herbst i Stefan Mangard. "Protecting AES Software Implementations on 32-Bit Processors Against Power Analysis". W Applied Cryptography and Network Security, 141–57. Berlin, Heidelberg: Springer Berlin Heidelberg, 2007. http://dx.doi.org/10.1007/978-3-540-72738-5_10.
Pełny tekst źródłaStreszczenia konferencji na temat "32-bit processor"
George, Mark, i Julie Brichacek. "Radiation hardened 32-bit processor (RH32)". W 15th International Communicatons Satellite Systems Conference and Exhibit. Reston, Virigina: American Institute of Aeronautics and Astronautics, 1994. http://dx.doi.org/10.2514/6.1994-1104.
Pełny tekst źródłaSingh, Narendra Bahadur, i Prashant Singh. "Design of 32-bit real numeric processor". W 2013 International Conference on Advanced Electronic Systems (ICAES). IEEE, 2013. http://dx.doi.org/10.1109/icaes.2013.6659368.
Pełny tekst źródłaKim, Ji-Hoon, Duk-Hyun You, Ki-Seok Kwon, Eun-Joo Bae, WonHee Son i In-Cheol Park. "Design of high-performance 32-bit embedded processor". W 2008 International SoC Design Conference (ISOCC). IEEE, 2008. http://dx.doi.org/10.1109/socdc.2008.4815746.
Pełny tekst źródłaOh, Hyun Woo, Kwon Neung Cho i Seung Eun Lee. "Design of 32-bit Processor for Embedded Systems". W 2020 International SoC Design Conference (ISOCC). IEEE, 2020. http://dx.doi.org/10.1109/isocc50952.2020.9332944.
Pełny tekst źródłaKubde, R. M., D. B. Bhoyar i R. S. Khedikar. "Design of 32 bit (MIPS) RISC PROCESSOR using FPGA". W ICWET '10: International Conference and Workshop on Emerging Trends in Technology. New York, NY, USA: ACM, 2010. http://dx.doi.org/10.1145/1741906.1742123.
Pełny tekst źródłaAadarsh, Aadarsh, Aditya Kumar, Aditya Yadav i P. C. Joshi. "Design and Power Analysis of 32-Bit Pipelined Processor". W 2021 International Conference on Advance Computing and Innovative Technologies in Engineering (ICACITE). IEEE, 2021. http://dx.doi.org/10.1109/icacite51222.2021.9404622.
Pełny tekst źródłaBhargava, Akansha, i R. S. Ochawar. "Biometric Access Control Implementation Using 32 bit Arm Cortex Processor". W 2014 International Conference on Electronic Systems, Signal Processing and Computing Technologies (ICESC). IEEE, 2014. http://dx.doi.org/10.1109/icesc.2014.98.
Pełny tekst źródłaBink, Arjan, i Richard York. "ARM996HS™ the first licensable, clockless 32-bit processor core". W 2006 IEEE Hot Chips 18 Symposium (HCS). IEEE, 2006. http://dx.doi.org/10.1109/hotchips.2006.7477862.
Pełny tekst źródłaArdalan, S., i A. Adibi. "Design, simulation and synthesis of a 32-bit math-processor". W 48th Midwest Symposium on Circuits and Systems, 2005. IEEE, 2005. http://dx.doi.org/10.1109/mwscas.2005.1594390.
Pełny tekst źródłaBertoni, Guido, Luca Breveglieri, Farina Roberto i Francesco Regazzoni. "Speeding Up AES By Extending a 32 bit Processor Instruction Set". W IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06). IEEE, 2006. http://dx.doi.org/10.1109/asap.2006.62.
Pełny tekst źródłaRaporty organizacyjne na temat "32-bit processor"
Siy, P. F., J. T. Carter, L. R. D'Addario i D. A. Loeber. Dose Rate and Total Dose Radiation Testing of the Texas Instruments TMS320C30 32-Bit Floating Point Digital Signal Processor. Fort Belvoir, VA: Defense Technical Information Center, sierpień 1991. http://dx.doi.org/10.21236/ada239767.
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