Gotowe bibliografie tematyczne / 8b/10b encoders

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  1. Artykuły w czasopismach
  2. Rozprawy doktorskie
  3. Streszczenia konferencji

Gotowa bibliografia na temat „8b/10b encoders”

Autor: Grafiati
Data publikacji: 3 czerwca 2025
Data aktualizacji: 31 lipca 2025

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Artykuły w czasopismach na temat "8b/10b encoders"

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Popa, Stefan, Mihai Ivanovici, and Radu-Mihai Coliban. "Optimal Implementations of 8b/10b Encoders and Decoders for AMD FPGAs." Electronics 13, no. 6 (2024): 1062. http://dx.doi.org/10.3390/electronics13061062.

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The 8b/10b IBM encoding scheme is used in a plethora of communication technologies, including USB, Gigabit Ethernet, and Serial ATA. We propose two primitive-based structural designs of an 8b/10b encoder and two of an 8b/10b decoder, all targeted at modern AMD FPGA architectures. Our aim is to reduce the amount of resources used for the implementations. We compare our designs with implementations resulting from behavioral models as well as with state-of-the-art solutions from the literature. The implementation results show that our solutions provide the lowest resource utilization with compara
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Song, Siqi, Heguo Yin, Jianzhong Zhao, Yi Zhan, and Peter Poechmueller. "An 8B/10B parallel encoder design for the polarity pre-processing." Journal of Physics: Conference Series 2450, no. 1 (2023): 012055. http://dx.doi.org/10.1088/1742-6596/2450/1/012055.

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Abstract To tackle the high latency and slow encoding speed of 8B/10B encoder circuits in high-speed serial interfaces, a parallel structure for polarity pre-processing based on logic operations is proposed to optimize encoder performance in this article. Firstly, the encoding process is divided into polarity pre-processing and coding two pipeline stages. This method equals each stage’s delay and decreases the coding waiting period. Additionally, the structure employs polarity pre-processing to optimize the critical delay paths into multi-stage heterodyne gates in series. Therefore, the effect
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Chen, Zhang Jin, Guo Hai Zhong, and Zhuo Bi. "A High Speed 8B/10B Encoder/Decoder Design Based on Low Cost FPGA." Advanced Materials Research 462 (February 2012): 361–67. http://dx.doi.org/10.4028/www.scientific.net/amr.462.361.

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A high speed 8B/10B Encoder/Decoder is presented in this paper. The Encoder/Decoder is based on Altera’s low cost FPGA Cyclone family. The Encoder/Decoder includes parallel pipeline structure. The Encoder/Decoder is applied to the Serializer/Deserializer (SERDES) of high-speed serial bus. The Encoder/Decoder is synthesized and simulated by Quartus II 9.1. The synthesis and analysis results show the maximum frequency is more than 359MHz. The timing simulation results show the clock frequency is more than 125 MHz. The single channel data rate of serial bus can get to 1.25Gbps. The proposed Encod
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Kim, Yong-Woo, Beomseok Shin, and Jin-Ku Kang. "High-speed 8B/10B encoder design using a simplified coding table." IEICE Electronics Express 5, no. 16 (2008): 581–85. http://dx.doi.org/10.1587/elex.5.581.

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NANNIPIERI, Pietro, Daniele DAVALLE, and Luca FANUCCI. "A Novel Parallel 8B/10B Encoder: Architecture and Comparison with Classical Solution." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E101.A, no. 7 (2018): 1120–22. http://dx.doi.org/10.1587/transfun.e101.a.1120.

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Subhash, Patel *. Abhishek Vaghela Bhavin Gajjar. "DESIGN OF PHASE LOCKED LOOP." INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY 6, no. 5 (2017): 312–20. https://doi.org/10.5281/zenodo.573512.

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In this work, we have designed CDR-PLL for 1GHz frequency. The design is carried out in the 180nm CMOS technology. We have use Hogge phase detector with the Kim-Lee delay cell based VCO. The designed CDR-PLL is tested by applying the 8B-10B encoded data and the simulation results are represented. The obtained results show that the clock is recovered successfully.
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Park, Junyong, Sumin Choi, Jonghoon J. Kim, et al. "A Novel Stochastic Model-Based Eye-Diagram Estimation Method for 8B/10B and TMDS-Encoded High-Speed Channels." IEEE Transactions on Electromagnetic Compatibility 60, no. 5 (2018): 1510–19. http://dx.doi.org/10.1109/temc.2017.2766295.

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Wang, De Gui, Cheng Li, and Tian Huai Ding. "An Improved Approach to RS485-Based Long-Distance High Speed Telemetry for Industrial Sensor Data." Applied Mechanics and Materials 543-547 (March 2014): 1013–17. http://dx.doi.org/10.4028/www.scientific.net/amm.543-547.1013.

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In industrial fields such as seismic explorations, RS485 is considered a workhorse interface standard, and it is the most widely used for serial interface found on sensors. However, long-distance transmission at high data throughput is one of the key features. An improved RS485-based high-speed remote transmission method is developed to implement the transmission of large amounts of data from distributed sensors. Based on the signal integrity analysis, the hardware interface designs including interface chips and impedance matching are determined by continuous square-wave pulse transmission. Th
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9

Wojcik, E., A. M. Murphy, H. Fares, K. Dang-Vu, and S. I. Tsubota. "Enhancer of rudimentaryp1, e(r)p1, a highly conserved enhancer of the rudimentary gene." Genetics 138, no. 4 (1994): 1163–70. http://dx.doi.org/10.1093/genetics/138.4.1163.

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Abstract A hybrid dysgenesis-induced mutation, enhancer of rudimentaryp1 (e(r)p1), is a recessive enhancer of a weak rudimentary mutant phenotype in Drosophila melanogaster. The e(r) gene was cloned using P element tagging and localized to region 8B on the X chromosome. It encodes a 1.0-kb and a 1.2-kb transcript. The 1.0-kb transcript is present in both adult males and females, while the 1.2-kb transcript is predominantly found in females. The difference in the lengths of the two e(r) transcripts is caused by two different polyadenylation sites spaced 228 bp apart. The amounts of both of thes
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Bello-Perez, Melissa, Jesús Hurtado-Tamayo, Ricardo Requena-Platek, et al. "MERS-CoV ORF4b is a virulence factor involved in the inflammatory pathology induced in the lungs of mice." PLOS Pathogens 18, no. 9 (2022): e1010834. http://dx.doi.org/10.1371/journal.ppat.1010834.

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No vaccines or specific antiviral drugs are authorized against Middle East respiratory syndrome coronavirus (MERS-CoV) despite its high mortality rate and prevalence in dromedary camels. Since 2012, MERS-CoV has been causing sporadic zoonotic infections in humans, which poses a risk of genetic evolution to become a pandemic virus. MERS-CoV genome encodes five accessory proteins, 3, 4a, 4b, 5 and 8b for which limited information is available in the context of infection. This work describes 4b as a virulence factor in vivo, since the deletion mutant of a mouse-adapted MERS-CoV-Δ4b (MERS-CoV-MA-Δ
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Rozprawy doktorskie na temat "8b/10b encoders"

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Jana, Prateek Kumar. "Design of 8B/10B encoder and its OVM compliant verification IP." Thesis, 2011. http://ethesis.nitrkl.ac.in/2890/2/Thesis.pdf.

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Today in the era of modern technology micro electronics play a very vital role in every aspects of life of an individual, increasing use for micro electronics equipments increases the demand for manufacturing its components and its availability, reducing its manufacturing time, resulting in increasing the failure rate of the finished product. In order to overcome this problem the Technocrats develop a method called Verification, a process which is a part of manufacturing microelectronics products and its main objective is to verify the intent of the design is preserved in its implementation.
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Streszczenia konferencji na temat "8b/10b encoders"

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Xu, Qiaoyu, and Huijie Liu. "8b/10b Encoder Design." In 2nd International Conference on Computer Application and System Modeling. Atlantis Press, 2012. http://dx.doi.org/10.2991/iccasm.2012.25.

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Ashrafi, Hamed, Morteza Mousazadeh, and Kh Hadidi. "An 8B/10B encoder with 2GHz operating frequency." In 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2016. http://dx.doi.org/10.1109/mwscas.2016.7870005.

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Wang, Qi, Si-liang Hua, and Dong-hui Wang. "A 1.1 GHz 8B/10B encoder and decoder design." In Electronics (PrimeAsia). IEEE, 2010. http://dx.doi.org/10.1109/primeasia.2010.5604943.

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Yong-woo Kim and Jin-ku Kang. "An 8B/10B encoder with a modified coding table." In APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS). IEEE, 2008. http://dx.doi.org/10.1109/apccas.2008.4746322.

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Sahni, Kanika, Kiran Rawat, Sujata Pandey, and Ziauddin Ahmad. "Low power approach for implementation of 8B/10B encoder and 10B/8B decoder used for high speed communication." In 2014 2nd International Conference on Emerging Technology Trends in Electronics, Communication and Networking (ET2ECN). IEEE, 2014. http://dx.doi.org/10.1109/et2ecn.2014.7044951.

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Yadav, Shivani, Sujata Pandey, and Ashutosh Gupta. "Implementation of 8B/10B encoder-decoder for Gigabit Ethernet Frame." In 2014 Eleventh International Conference on Wireless and Optical Communications Networks (WOCN). IEEE, 2014. http://dx.doi.org/10.1109/wocn.2014.6923049.

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Quesada-Martinez, Andres, Javier Aparicio-Morales, Jose Campos-Araya, Alfonso Chacon-Rodriguez, Ronny Garcia-Ramirez, and Renato Rimolo-Donadio. "Evaluation of 8b/10b FPGA Encoder Implementations for SerDes Links." In 2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS). IEEE, 2020. http://dx.doi.org/10.1109/lascas45839.2020.9069001.

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Su, Chun-Yu, Chiung-An Chen, Shih-Lun Chen, and Jin-Yang Lai. "USB 3.0 Using FPGA Optimization for 8b/10b Encoder/Decoder." In 2021 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS). IEEE, 2021. http://dx.doi.org/10.1109/ispacs51563.2021.9650993.

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Aref, I. A., N. A. Ahmed, F. Rodriguez-Salazar, and K. Elgaid. "RTL-level modeling of an 8B/10B encoder-decoder using SystemC." In 2008 IFIP International Conference on Wireless and Optical Communications Networks - (WOCN). IEEE, 2008. http://dx.doi.org/10.1109/wocn.2008.4542493.

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Popa, Stefan, Radu-Mihai Coliban, and Mihai Ivanovici. "An Optimal Implementation of an 8b/10b Encoder for Xilinx FPGAs." In 2022 International Symposium on Electronics and Telecommunications (ISETC). IEEE, 2022. http://dx.doi.org/10.1109/isetc56213.2022.10010077.

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