Rozprawy doktorskie: „CARRIER RELIABILITY”

7

Jiang, Liangjun. "HOT CARRIER EFFECT ON LDMOS TRANSISTORS." Doctoral diss., University of Central Florida, 2007. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/3230.

Pełny tekst źródła

Streszczenie:

One of the main problems encountered when scaling down is the hot carrier induced degradation of MOSFETs. This problem has been studied intensively during the past decade, under both static and dynamic stress conditions. In this period it has evolved from a more or less academic research topic to one of the most stringent constraints guaranteeing the lifetime of sub-micron devices. New drain engineering technique leads to the extensive usage of lateral doped drain structures. In these devices the peak of the lateral field is lowered by reducing the doping concentration near the drain and by providing a smooth junction transition instead of an abrupt one. Therefore, the amount of hot carrier generation for a given supply voltage and the influence of a certain physical damage on the electrical characteristics is decreased dramatically. A complete understanding of the hot carrier degradation problem in sub-micron 0.25um LD MOSFETs is presented in this work. First we discuss the degradation mechanisms observed under, for circuit operation, somewhat artificial but well-controlled uniform-substrate hot electron and substrate hot-hole injection conditions. Then the more realistic case of static channel hot carrier degradation is treated, and some important process-related effects are illustrated, followed by the behavior under the most relevant case for real operation, namely dynamic degradation. An Accurate and practical parameter extraction is used to obtain the LD MOSFETs model parameters, with the experiment verification. Good agreement between the model simulation and experiment is achieved. The gate charge transfer performance is examined to demonstrate the hot carrier effect. Furthermore, In order to understand the dynamic stress on the LD MOSFET and its effect on RF circuit, the hot-carrier injection experiment in which dynamic stress with different duty cycle applied to a LD MOS transistor is presented. A Class-C power amplifier is used to as an example to demonstrate the effect of dynamic stress on RF circuit performance. Finally, the strategy for improving hot carrier reliability and a forecast of the hot carrier reliability problem for nano-technologies are discussed. The main contribution of this work is, it systemically research the hot carrier reliability issue on the sub-micron lateral doped drain MOSFETs, which is induced by static and dynamic voltage stress; The stress condition mimics the typical application scenarios of LD MOSFET. Model parameters extraction technique is introduced with the aid of the current device modeling tools, the performance degradation model can be easily implement into the existing computer-aided tools. Therefore, circuit performance degradation can be accurately estimated in the design stage. CMOS technologies are constantly scaled down. The production on 65 nm is on the market. With the reduction in geometries, the devices become more vulnerable to hot carrier injection (HCI). HCI reliability is a must for designs implemented with new processes. Reliability simulation needs to be implemented in PDK libraries located on the modeling stage. The use of professional tools is a prerequisite to develop accurate device models, from DC to GHz, including noise modeling and nonlinear HF effects, within a reasonable time. Designers need to learn to design for reliability and they should be educated on additional reliability analyses. The value is the reduction of failure and redesign costs. Ph.D. School of Electrical Engineering and Computer Science Engineering and Computer Science Electrical Engineering

Style APA, Harvard, Vancouver, ISO itp.

8

Le, Huy X. P. "On the methodology of assessing hot-carrier reliability of analog circuits." Thesis, Massachusetts Institute of Technology, 1999. http://hdl.handle.net/1721.1/84212.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

9

Das, A. G. Man Mohan. "Effect of wearout processes on the critical timing parameters and reliability of CMOS bistable circuits." Thesis, Durham University, 1997. http://etheses.dur.ac.uk/4701/.

Pełny tekst źródła

Streszczenie:

The objective of the research presented in this thesis was to investigate the effects of wearout processes on the performance and reliability of CMOS bistable circuits. The main wearout process affecting reliability of submicron MOS devices was identified as hot-carrier stress (and the resulting degradation in circuit performance). The effect of hot-carrier degradation on the resolving time leading to metastability of the bistable circuits also have been investigated. Hot-carrier degradation was identified as a major reliability concern for CMOS bistable circuits designed using submicron technologies. The major hot-carrier effects are the impact ionisation of hot- carriers in the channel of a MOS device and the resulting substrate current and gate current generation. The substrate current has been used as the monitor for the hot-carrier stress and have developed a substrate current model based on existing models that have been extended to incorporate additional effects for submicron devices. The optimisation of the substrate current model led to the development of degradation and life-time models. These are presented in the thesis. A number of bistable circuits designed using 0.7 micron CMOS technology design rules were selected for the substrate current model analysis. The circuits were simulated using a set of optimised SPICE model parameters and the stress factors on each device was evaluated using the substrate current model implemented as a post processor to the SPICE simulation. Model parameters for each device in the bistable were degraded according to the stress experienced and simulated again to determine the degradation in characteristic timing parameters for a predetermined stress period. A comparative study of the effect of degradation on characteristic timing parameters for a number of latch circuits was carried out. The life-times of the bistables were determined using the life-time model. The bistable circuits were found to enter a metastable state under critical timing conditions. The effect of hot-carrier stress induced degradation on the metastable state operation of the bistables were analysed. Based on the analysis of the hot-carrier degradation effects on the latch circuits, techniques are suggested to reduce hot-carrier stress and to improve circuit life-time. Modifications for improving hot- carrier reliability were incorporated into all the bistable circuits which were re-simulated to determine the improvement in life-time and reliability of the circuits under hot-carrier stress. The improved circuits were degraded based on the new stress factors and the degradation effects on the critical timing parameters evaluated and these were compared with those before the modifications. The improvements in the life-time and the reliability of the selected bistable circuits were quantified. It has been demonstrated that the hot-carrier reliability for all the selected bistable circuits can be improved by design techniques to reduce the stress on identified critically stressed devices.

Style APA, Harvard, Vancouver, ISO itp.

10

Koeppel, Gaudenz Alesch. "Reliability considerations of future energy systems : multi-carrier systems and the effect of energy storage /." Zürich : ETH, 2007. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=17058.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

11

Liu, Yi. "STUDY OF OXIDE BREAKDOWN, HOT CARRIER AND NBTI EFFECTS ON MOS DEVICE AND CIRCUIT RELIABILITY." Doctoral diss., University of Central Florida, 2005. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/3550.

Pełny tekst źródła

Streszczenie:

As CMOS device sizes shrink, the channel electric field becomes higher and the hot carrier (HC) effect becomes more significant. When the oxide is scaled down to less than 3 nm, gate oxide breakdown (BD) often takes place. As a result, oxide trapping and interface generation cause long term performance drift and related reliability problems in devices and circuits. The RF front-end circuits include low noise amplifier (LNA), local oscillator (LO) and mixer. It is desirable for a LNA to achieve high gain with low noise figure, a LO to generate low noise signal with sufficient output power, wide tuning range, and high stability, and a mixer to up-convert or down-convert the signal with good linearity. However, the RF front-end circuit performance is very sensitive to the variation of device parameters. The experimental results show that device performance is degraded significantly subject to HC stress and BD. Therefore, RF front-end performance is degraded by HC and BD effects. With scaling and increasing chip power dissipation, operating temperatures for device have also been increasing. Another reliability concern, which is the negative bias temperature instability (NBTI) caused by the interface traps under high temperature and negative gate voltage bias, arises when the operation temperature of devices increases. NBTI has received much attention in recent year and it is found that NIT is present for all stress conditions and NOT is found to occur at high VG. Therefore, the probability of BD in pMOSFET increases with temperature since trapped charges during the NBTI process increase, thus resulting in percolation, a main cause of oxide degradation. The above effects can cause significant degradations in transistors, thus leading to the shifts of RF performance. This dissertation focuses on the following aspects: (1) RF performance degradation in nMOSFET and pMOSFET due to hot carrier and soft breakdown effects are examined experimentally and will be used for circuit application in the future. (2) A modeling method to analyze the gate oxide breakdown effects on RF nMOSFET has been proposed. The device performance drifts due to gate oxide breakdown are examined, breakdown spot resistance and total gate capacitance are extracted before and after stress for 0.16 um CMOS technology. (3) LC voltage controlled oscillator (VCO) performance degradation due to gate oxide breakdown effect is evaluated. (4) NBTI, HCI and BD combined effects on RF performance degradation are investigated. A physical picture illustrating the NBTI induced BD process is presented. A model to evaluate the time-to-failure (TTF) during NBTI is developed. DCIV method is used to extract the densities of NIT and NOT. Measurements show that there is direct correlation between the steplike increase in the gate current and the oxide-trapped charge (NOT). However, Breakdown has nothing to do with interface traps (NIT). (5) It is found that the degradation due to NSH stress is more severe than that of NS stress at high temperature. A model aiming to evaluate the stress-induced degradation is also developed. Ph.D. Department of Electrical and Computer Engineering Engineering and Computer Science Electrical Engineering

Style APA, Harvard, Vancouver, ISO itp.

12

Steighner, Jason. "Investigation and trade study on hot carrier reliability of the PHEMT for DC and RF performance." Master's thesis, University of Central Florida, 2011. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/5048.

Pełny tekst źródła

Streszczenie:

A unified study on the hot carrier reliability of the Pseudomorphic High Electron Mobility Transistor (PHEMT) is carried out through Sentaurus Device Simulation, measurement, and physical analyses. A trade study of devices with four various geometries are evaluated for DC and RF performance. The trade-off of DC I-V characteristics, transconductance, and RF parameters versus hot carrier induced gate current is assessed for each device. Ambient temperature variation is also evaluated to observe its impact on hot carrier effects. A commercial grade PHEMT is then evaluated and measured to demonstrate the performance degradation that occurs after a period of operation in an accelerated stress regime--one hour of high drain voltage, low drain current stress. This stress regime and normal operation regime are then modeled through Sentaurus. Output characteristics are shown along with stress mechanisms within the device. Lastly, a means of simulating a PHEMT post-stress is introduced. The approach taken accounts for the activation of dopants near the channel. Post-stress simulation results of DC and RF performance are then investigated. ID: 030423238; System requirements: World Wide Web browser and PDF reader.; Mode of access: World Wide Web.; Thesis (M.S.)--University of Central Florida, 2011.; Includes bibliographical references (p. 46-47). M.S. Masters Electrical Engineering and Computer Science Engineering and Computer Science

Style APA, Harvard, Vancouver, ISO itp.

13

Raghunathan, Uppili Srinivasan. "TCAD modeling of mixed-mode degradation in SiGe HBTs." Thesis, Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/54315.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

14

Zhu, Chendong. "The mixed-mode reliability stress of Silicon-Germanium heterojunction bipolar transistors." Diss., Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/14647.

Pełny tekst źródła

Streszczenie:

The objective of the dissertation is to combine the recent Mixed-Mode reliability stress studies into a single text. The thesis starts with a review of silicon-germanium heterojunction bipolar transistor fundamentals, development trends, and the conventional reliability stress paths used in industry, after which the new stress path, Mixed-Mode stress, is introduced. Chapter 2 is devoted to an in-depth discussion of damage mechanisms that includes the impact ionization effct and the selfheating effect. Chapter 3 goes onto the impact ionization effect using two-dimensional calibrated MEDICI simulations. Chapter 4 assesses the reliability of SiGe HBTs in extreme temperature environments by way of comprehensive experiments and MEDICI simulations. A comparison of the device lifetimes for reverse-EB stress and mixed-mode stress indicates different damage mechanisms govern these phenomena. The thesis concludes with a summary of the project and suggestions for future research in chapter 5.

Style APA, Harvard, Vancouver, ISO itp.

15

Huang, Wei-Jie, and Wei-Jie Huang. "Towards Increased Photovoltaic Energy Generation Efficiency and Reliability: Quantum-Scale Spectral Sensitizers in Thin-Film Hybrid Devices and Microcracking in Monocrystalline Si." Diss., The University of Arizona, 2016. http://hdl.handle.net/10150/623175.

Pełny tekst źródła

Streszczenie:

The present work focuses on two strategies contributing to the development of high efficiency, cost-effective photovoltaic (PV) technology for renewable energy generation: the design of new materials offering enhanced opto-electronic performance and the investigation of material degradation processes and their role in predicting the long-term reliability of PV modules in the field. The first portion of the present work investigates the integration of a novel CdTe-ZnO nanocomposite material as a spectral sensitizer component within a thin-film, hybrid heterojunction (HJ) PV device structure. Quantum-scale semiconductors have the potential to improve PV device performance through enhanced spectral absorption and photocarrier transport. This is realized via appropriate design of the semiconductor nanophase (providing tunable spectral absorption) and its spatial distribution within an electrically active matrix (providing long-range charge transport). Here, CdTe nanocrystals, embedded in an electrically active ZnO matrix, form a nanocomposite (NC) offering control of both spectral absorption and photocarrier transport behavior through the manipulation of nanophase assembly (ensemble effects). A sequential radio- frequency (RF) magnetron sputter deposition technique affords the control of semiconductor nanophase spatial distribution relative to the HJ plane in a hybrid, ZnO-P3HT test structure. Energy conversion performance (current density-voltage (J-V) and external quantum efficiency (EQE) response) was examined as a function of the location of the CdTe nanophase absorber region using both one dimensional solar cell capacitance simulator (SCAPS) and the experimental examination of analogous P3HT-ZnO based hybrid thin films. Enhancement in simulated EQE over a spectral range consistent with the absorption region of the CdTe nanophase (i.e. 400–475 nm) is confirmed in the experimental studies. Moreover, a trend of decreasing quantum efficiency in this spectral range with increasing separation between the CdTe nanophase region and the heterojunction plane is observed. The results are interpreted in terms of carrier scattering/recombination length mitigating the successful transport of carriers across the junction. The second portion of the research addresses the need for robust PV performance in commercial module as a primary contributor to cost-effective operation in both distributed systems and utility scale generation systems. The understanding of physical and chemical mechanisms resulting in the degradation of materials of construction used in PV modules is needed to understand the contribution of these processes to module integrity and performance loss with time under varied application environments. In this context, the second part of present study addresses microcracking in Si–an established degradation process contributing to PV module power loss. The study isolates microcrack propagation in single-crystal Si, and investigates the effect of local environment (temperature, humidity) on microcrack elongation under applied strains. An investigation of microindenter-induced crack evolution with independent variation of both temperature and vapor density was pursued in PV-grade Si wafers. Under static tensile strain conditions, an increase in sub-critical crack elongation with increasing atmospheric water content was observed. To provide further insight into the potential physical and chemical conditions at the microcrack tip, micro-Raman measurements were performed. Preliminary results confirm a spatial variation in the frequency of the primary Si vibrational resonance within the crack-tip region, associated with local stress state, whose magnitude is influenced by environmental conditions during the period of applied static strain. The experimental effort was paired with molecular dynamics (MD) investigations of microcrack evolution in single-crystal Si to furnish additional insight into mechanical contributions to crack elongation. The MD results demonstrate that crack-tip energetics and associated cracking crystal planes and morphology are intimately related to the crack and applied strain orientations with respect to the principal crystallographic axes. The resulting fracture surface energy and the stress-strain response of the Si under these conditions form the basis for preliminary micro-scale peridynamics (PD) simulations of microcrack development under constant applied strain. These efforts were integrated with the experimental results to further inform the mechanisms contributing to this important degradation mode in Si-based photovoltaics.

Style APA, Harvard, Vancouver, ISO itp.

16

CUI, ZHI. "MODELING AND SIMULATION OF LONG TERM DEGRADATION AND LIFETIME OF DEEP-SUBMICRON MOS DEVICE AND CIRCUIT." Doctoral diss., University of Central Florida, 2005. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/2163.

Pełny tekst źródła

Streszczenie:

Long-term hot-carrier induced degradation of MOS devices has become more severe as the device size continues to scale down to submicron range. In our work, a simple yet effective method has been developed to provide the degradation laws with a better predictability. The method can be easily augmented into any of the existing degradation laws without requiring additional algorithm. With more accurate extrapolation method, we present a direct and accurate approach to modeling empirically the 0.18-ìm MOS reliability, which can predict the MOS lifetime as a function of drain voltage and channel length. With the further study on physical mechanism of MOS device degradation, experimental results indicated that the widely used power-law model for lifetime estimation is inaccurate for deep submicron devices. A better lifetime prediction method is proposed for the deep-submicron devices. We also develop a Spice-like reliability model for advanced radio frequency RF MOS devices and implement our reliability model into SpectreRF circuit simulator via Verilog-A HDL (Hardware Description Language). This RF reliability model can be conveniently used to simulate RF circuit performance degradation Ph.D. Department of Electrical and Computer Engineering Engineering and Computer Science Electrical Engineering

Style APA, Harvard, Vancouver, ISO itp.

17

Chen, Chang-Chih. "System-level modeling and reliability analysis of microprocessor systems." Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/53033.

Pełny tekst źródła

Streszczenie:

Frontend and backend wearout mechanisms are major reliability concerns for modern microprocessors. In this research, a framework which contains modules for negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), hot carrier injection (HCI), gate-oxide breakdown (GOBD), backend time-dependent dielectric breakdown (BTDDB), electromigration (EM), and stress-induced voiding (SIV) is proposed to analyze the impact of each wearout mechanism on state-of-art microprocessors and to accurately estimate microprocessor lifetimes due to each wearout mechanism. Taking into account the detailed thermal profiles, electrical stress profiles and a variety of use scenarios, composed of a fraction of time in operation, a fraction of time in standby, and a fraction of time when the system is off, this work provides insight into lifetime-limiting wearout mechanisms, along with the reliability-critical microprocessor functional units for a system. This enables circuit designers to know if their designs will achieve an adequate lifetime and further make any updates in the designs to enhance reliability prior to committing the designs to manufacture.

Style APA, Harvard, Vancouver, ISO itp.

18

Arora, Rajan. "Trade-offs between performance and reliability of sub 100-nm RF-CMOS technologies." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/50140.

Pełny tekst źródła

Streszczenie:

The objective of this research is to develop an understanding of the trade-offs between performance and reliability in sub 100-nm silicon-on-insulator (SOI) CMOS technologies. Such trade-offs can be used to demonstrate high performance reliable circuits in scaled technologies. Several CMOS reliability concerns such as hot-carrier stress, ionizing irradiation damage, RF stress, temperature effects, and single-event effects are studied. These reliability mechanisms can cause temporary or permanent damage to the semiconductor device and to the circuits using them. Several improvements are made to the device layout and process to achieve optimum performance. Parasitics are shown to play a dominant role in the performance and reliability of sub 100-nm devices. Various techniques are suggested to reduce these parasitics, such as the use of the following: a) optimum device-width, b) optimum gate-finger to gate-finger spacing, c) optimum source/drain metal contact spacing, and d) floating-body/body-contact. The major contributions from this research are summarized as follows: 1) Role of floating-body effects on the performance and reliability of sub 100-nm CMOS-on-SOI technologies is investigated for the first time [1], [2]. It is demonstrated through experimental data and TCAD simulations that floating-body devices have improved RF performance but degraded reliability compared to body-contacted devices. 2) Floating-body effects in a cascode core is studied. Cascode cores are demonstrated to achieve much larger reliability lifetimes than a single device. A variety of cascode topologies are studied to achieve the trade-o s between performance and reliability for high-power applications [2]. 3) The use of body-contact to modulate the performance of devices and single-poledouble- throw (SPDT) switches is studied. The SPDT switch performance is shown to improve with a negative body-bias. 4) The impact of device width on the RF performance and reliability is studied. Larger width devices are shown to have greater degradation, posing challenging questions for RF design in strained-Si technologies [3]. 5) A novel study showing the e ect of source/drain metal contact spacing and gate-finger to gate-finger spacing on the device RF performance is carried out. Further, the impact of above on the hot-carrier, RF stress, and total-dose irradiation tolerance is studied [3], [4]. 6) Latchup phenomenon in CMOS is shown to be possible at cryogenic temperatures (below 50 K), and its consequences are discussed [5]. 7) A time-dependent device degradation model has been developed in technology computer aided design (TCAD) to model reliability in CMOS and SiGe devices. 8) The total-dose irradiation tolerance and hot-carrier reliability of 32-nm CMOSon- SOI technology is reported for the first time. The impact of HfO2 based gate dielectric on the performance and reliability is studied [6]. 9) The impact of technology scaling from 65-nm to 32-nm on the performance and reliability of CMOS technologies is studied [6]. 10) Cryogenic performance and reliability of 45-nm nFETs is investigated. The RF performance improves significantly at 77 K. The hot-carrier device reliability is shown to improve at low temperatures in short-channel CMOS technologies.

Style APA, Harvard, Vancouver, ISO itp.

19

Tran, Thi-Phuong-Yen. "CMOS 180 nm Compact Modeling Including Ageing Laws for Harsh Environment." Thesis, Bordeaux, 2022. http://www.theses.fr/2022BORD0185.

Pełny tekst źródła

Streszczenie:

Au cours des dernières décennies, la demande de fonctionnalités complexes et d'intégration haute densité pour les Circuits Intégrés (CI) a mené à une réduction de la taille des dispositifs métal-oxyde-silicium (MOS). Dans ce scénario, les problèmes de fiabilité sont les préoccupations considérables par suite de la miniaturisation de l'appareil, telles que Hot Carrier Injection (HCI) et Bias Temperature Instability (BTI) qui ont un impact sérieux sur les performances de l'appareil. Dans certains domaines d'application où le coût des pannes est extrêmement élevé, comme l'espace, les champs pétrolifères ou les soins de santé, l'appareil doit pouvoir fonctionner de manière stable et fiable, en particulier dans une plage de températures étendue. Bien que les mécanismes de défaillance des dispositifs aient été intensivement étudiés dans le passé, les investigations de ces mécanismes à hautes températures sont rarement étudiées.L'objectif de cette thèse est de développer les lois de vieillissement de la technologie CMOS 0.18µm afin d'optimiser la conception des circuits pour une durée de vie ciblée sous des températures extrêmes. Nous avons mené une campagne intensive de tests de vieillissement pour nMOS et pMOS avec plusieurs longueurs de grille. Les mécanismes HCI et BTI intrinsèques ont été caractérisés et modélisés sous des tensions de polarisation de fonctionnement typique pour éviter le risque de sur-accélération d'autres mécanismes d'usure qui ne sont pas censés être expérimentés dans l'application pratique. Notre expérimentation est un test à longue durée avec un temps de stress allant jusqu'à 2,000 heures. Cette thèse présente des résultats de mesure jusqu'à 230°C qui n'ont jamais été étudiés auparavant dans la littérature pour cette technologie.Les lois de vieillissement sont finalement intégrées dans un environnement de conception assistée par ordinateur (EDA) pour prédire l'évolution des paramètres électriques dégradés du transistor/circuit et l'estimation de la durée de vie en conséquence des effets du vieillissement. De plus, le test de fiabilité au niveau du circuit a été réalisé pour valider et vérifier les modèles de vieillissement proposés. Cette approche offre la possibilité d'évaluer et de simuler la dérive de spécification du CI due à l'effet du vieillissement dans la phase de conception précoce In the past decades, the demand for complicated functionality and high-density integration for Integrated Circuits (ICs) has resulted in metal-oxide-silicon (MOS) devices' scaling down. In this scenario, the reliability problems are the considerable concerns due to the device miniaturization, such as Hot Carrier Injection (HCI) and Bias Temperature Instability (BTI) that seriously impact the device performance. In some application fields where the cost of failure is extremely high such as space, oilfield, or healthcare, the device must be able to stably and reliably work, especially at an extensive temperature range. Although device failure mechanisms have been intensively investigated in the past, the investigations of these mechanisms at high temperatures are seldom studied.This thesis aims to develop the aging laws for 0.18µm CMOS technology to optimize circuit design for a targeted lifetime under extreme temperatures. We conducted an intensive aging test campaign for both nMOS and pMOS featuring several gate lengths. The intrinsic HCI and BTI mechanisms were characterized and modeled under typical operating voltage biases to avoid the risk of overaccelerating other wear-out mechanisms that are not supposed to be experienced in practical application. Our experiment is a long-term test with a stress time of up to 2,000 hours. This thesis presents measurement results up to 230°C that have never been studied before in the literature for this technology.The aging laws are finally integrated into an electronic design automation (EDA) environment to predict the evolution of the degraded transistor/circuit electrical parameters and the lifetime estimation due to the aging effects. In addition, the reliability test at the circuit level has been performed to validate and verify the proposed aging models. This approach offers the possibility to assess and simulate the IC specification drift due to the aging effect in the early design phase and optimize the circuit design over lifetime

Style APA, Harvard, Vancouver, ISO itp.

20

Mamy, Randriamihaja Yoann. "Etude de la fiabilité des technologies CMOS avancées, depuis la création des défauts jusqu'à la dégradation des transistors." Thesis, Aix-Marseille, 2012. http://www.theses.fr/2012AIXM4781/document.

Pełny tekst źródła

Streszczenie:

L'étude de la fiabilité représente un enjeu majeur de la qualification des technologies de l'industrie de la microélectronique. Elle est traditionnellement étudiée en suivant la dégradation des paramètres des transistors au cours du temps, qui sert ensuite à construire des modèles physiques expliquant le vieillissement des transistors. Nous avons fait le choix dans ces travaux d'étudier la fiabilité des transistors à l'échelle microscopique, en nous intéressant aux mécanismes de ruptures de liaisons atomiques à l'origine de la création des défauts de l'oxyde de grille. Nous avons tout d'abord identifié la nature des défauts et modéliser leurs dynamiques de capture de charges afin de pouvoir reproduire leur impact sur des mesures électriques complexes. Cela nous a permis de développer une nouvelle méthodologie de localisation des défauts, le long de l'interface Si-SiO2, ainsi que dans le volume de l'oxyde. La mesure des dynamiques de créations de défauts pour des stress de type porteurs chauds et menant au claquage de l'oxyde de grille nous a permis de développer des modèles de dégradation de l'oxyde, prédisant les profils de défauts créés à l'interface et dans le volume de l'oxyde. Nous avons enfin établi un lien précis entre l'impact de la dégradation d'un transistor sur la perte de fonctionnalité d'un circuit représentatif du fonctionnement d'un produit digital.L'étude et la modélisation de la fiabilité à l'échelle microscopique permet d'avoir des modèles plus physiques, offrant ainsi une plus grande confiance dans les extrapolations de durées de vie des transistors et des produits Reliability study is a milestone of microelectronic industry technology qualification. It is usually studied by following the degradation of transistors parameters with time, used to build physical models explaining transistors aging. We decided in this work to study transistors reliability at a microscopic scale, by focusing on atomic-bond-breaking mechanisms, responsible of defects creation into the gate-oxide. First, we identified defects nature and modeled their charge capture dynamics in order to reproduce their impact on complex electrical measurements degradation. This has allowed us developing a new methodology of defects localization, along the Si/SiO2 interface, and in the volume of the gate-oxide. Defects creation dynamics measurement, for Hot Carrier stress and stress conditions leading to the gate-oxide breakdown, has allowed us developing gate-oxide degradation models, predicting generated defect profiles at the interface and into the volume of the gate-oxide. Finally, we established an accurate link between a transistor degradation impact on circuit functionality loss.Reliability study and modeling at a microscopic scale allows having more physical models, granting a better confidence in transistors and products lifetime extrapolation

Style APA, Harvard, Vancouver, ISO itp.

21

Arfaoui, Wafa. "Fiabilité Porteurs Chauds (HCI) des transistors FDSOI 28nm High-K grille métal." Thesis, Aix-Marseille, 2015. http://www.theses.fr/2015AIXM4335.

Pełny tekst źródła

Streszczenie:

Au sein de la course industrielle à la miniaturisation et avec l’augmentation des exigences technologiques visant à obtenir plus de performances sur moins de surface, la fiabilité des transistors MOSFET est devenue un sujet d’étude de plus en plus complexe. Afin de maintenir un rythme de miniaturisation continu, des nouvelles architectures de transistors MOS en été introduite, les technologies conventionnelles sont remplacées par des technologies innovantes qui permettent d'améliorer l'intégrité électrostatique telle que la technologie FDSOI avec des diélectriques à haute constante et grille métal. Malgré toutes les innovations apportées sur l’architecture du MOS, les mécanismes de dégradations demeurent de plus en plus prononcés. L’un des mécanismes le plus critique des technologies avancées est le mécanisme de dégradation par porteurs chauds (HCI). Pour garantir les performances requises tout en préservant la fiabilité des dispositifs, il est nécessaire de caractériser et modéliser les différents mécanismes de défaillance au niveau du transistor élémentaire. Ce travail de thèse porte spécifiquement sur les mécanismes de dégradations HCI des transistors 28nm FDSOI. Basé sur l’énergie des porteurs, le modèle en tension proposé dans ce manuscrit permet de prédire la dégradation HC en tenant compte de la dépendance en polarisation de substrat incluant les effets de longueur, d’épaisseur de l’oxyde de grille ainsi que l’épaisseur du BOX et du film de silicium. Ce travail ouvre le champ à des perspectives d’implémentation du model HCI pour les simulateurs de circuits, ce qui représente une étape importante pour anticiper la fiabilité des futurs nœuds technologiques As the race towards miniaturization drives the industrial requirements to more performances on less area, MOSFETs reliability has become an increasingly complex topic. To maintain a continuous miniaturization pace, conventional transistors on bulk technologies were replaced by new MOS architectures allowing a better electrostatic integrity such as the FDSOI technology with high-K dielectrics and metal gate. Despite all the architecture innovations, degradation mechanisms remains increasingly pronounced with technological developments. One of the most critical issues of advanced technologies is the hot carrier degradation mechanism (HCI) and Bias Temperature Instability (BTI) effects. To ensure a good performance reliability trade off, it is necessary to characterize and model the different failure mechanisms at device level and the interaction with Bias Temperature Instability (BTI) that represents a strong limitation of scaled CMOS nodes. This work concern hot carrier degradation mechanisms on 28nm transistors of the FDSOI technology. Based on carrier’s energy, the energy driven model proposed in this manuscript can predict HC degradation taking account of substrate bias dependence (VB) including the channel length effects (L), gate oxide thickness (TOX) , back oxide BOX (TBox) and silicon film thickness (TSI ). This thesis opens up new perspectives of the model Integration into a circuit simulator, to anticipate the reliability of future technology nodes and check out circuit before moving on to feature design steps

Style APA, Harvard, Vancouver, ISO itp.

22

Ndiaye, Cheikh. "Etude de la fiabilité de type negative bias temperature instability (NBTI) et par porteurs chauds (HC) dans les filières CMOS 28nm et 14nm FDSOI." Thesis, Aix-Marseille, 2017. http://www.theses.fr/2017AIXM0182/document.

Pełny tekst źródła

Streszczenie:

L’avantage de cette architecture FDSOI par rapport à l’architecture Si-bulk est qu’elle possède une face arrière qui peut être utilisée comme une deuxième grille permettant de moduler la tension de seuil Vth du transistor. Pour améliorer les performances des transistors canal p (PMOS), du Germanium est introduit dans le canal (SiGe) et au niveau des sources/drain pour la technologie 14nm FDSOI. Par ailleurs, la réduction de la géométrie des transistors à ces dimensions nanométriques fait apparaître des effets de design physique qui impactent à la fois les performances et la fiabilité des transistors.Ce travail de recherche est développé sur quatre chapitres dont le sujet principal porte sur les performances et la fiabilité des dernières générations CMOS soumises aux mécanismes de dégradation BTI (Bias Temperature Instability) et par injections de porteurs chauds (HCI) dans les dernières technologies 28nm et 14nm FDSOI. Dans le chapitre I, nous nous intéressons à l’évolution de l’architecture du transistor qui a permis le passage des nœuds Low-Power 130-40nm sur substrat silicium à la technologie FDSOI (28nm et 14nm). Dans le chapitre II, les mécanismes de dégradation BTI et HCI des technologies 28nm et 14nm FDSOI sont étudiés et comparés avec les modèles standards utilisés. L’impact des effets de design physique (Layout) sur les paramètres électriques et la fiabilité du transistor sont traités dans le chapitre III en modélisant les contraintes induites par l’introduction du SiGe. Enfin le vieillissement et la dégradation des performances en fréquence ont été étudiés dans des circuits élémentaires de type oscillateurs en anneau (ROs), ce qui fait l’objet du chapitre IV The subject of this thesis developed on four chapters, aims the development of advanced CMOS technology nodes fabricated by STMicroelectronics in terms of speed performance and reliability. The main reliability issues as Bias Temperature Instability (BTI) and Hot-Carriers (HC) degradation mechanisms have been studied in the most recent 28nm and 14nm FDSOI technologies nodes. In the first chapter, we presents the evolution of transistor architecture from the low-power 130-40nm CMOS nodes on silicon substrate to the recent FDSOI technology for 28nm and 14nm CMOS nodes. The second chapter presents the specificity of BTI and HCI degradation mechanisms involved in 28nm and 14nm FDSOI technology nodes. In the third chapter, we have studied the impact of layout effects on device performance and reliability comparing symmetrical and asymmetrical geometries. Finally the trade-off between performance and reliability is studied in the fourth chapter using elementary circuits. The benefit of using double gate configuration with the use of back bias VB in FDSOI devices to digital cells, allows to compensate partially or totally the aging in ring oscillators (ROs) observed by the frequency reduction. This new compensation technique allows to extend device and circuit lifetime offering a new way to guaranty high frequency performance and long-term reliability

Style APA, Harvard, Vancouver, ISO itp.

23

Guichard, Éric. "Contribution à l'étude de la sensibilité au vieillissement des technologies SOI durcies." Grenoble INPG, 1995. http://www.theses.fr/1995INPG0102.

Pełny tekst źródła

Streszczenie:

Devant le developpement des technologies soi dans le domaine militaire et spatial et aujourd'hui civil, il s'agissait d'essayer de mieux comprendre les mecanismes physiques de degradation, par porteurs chauds, intervenant dans les transistors et les circuits. La specificite des transistors soi par rapport aux transistors bulk est la presence de l'oxyde enterre. Ce dernier, bien qu'apportant de nombreux avantages au fonctionnement des dispositifs, est considere, aujourd'hui encore, comme le talon d'achille des transistors soi vis a vis du vieillissement. Cependant, nous avons montre que pour les technologies futures ou la tension d'alimentation sera bien inferieure a 3v, la degradation de l'oxyde enterre disparait. La comparaison des transistors sur couche simox fine et tres epaisse (equivalente au bulk) a ete menee sur des transistors a canaux n et p. Les mecanismes physiques de base sont identiques, seule la degradation de l'oxyde enterre intervient lors du vieillissement des transistors p-mos. Un des aspects originaux de cette these est l'etude de la degradation dynamique des transistors soi. Pour ce faire, nous avons concu des circuits de test inedits, ou la caracterisation des transistors in-situ dans le circuit est possible. Ceci nous a permis de correler la degradation statique et dynamique. Le resultat principal est que la degradation dynamique reste faible: la derive de frequence, pour un oscillateur en anneau par exemple, n'atteint que quelques pourcents dans des conditions severes de vieillissement. Enfin, tout au long de notre etude, nous avons utilise l'emission lumineuse comme technique d'analyse du vieillissement des transistors et des circuits. C'est un moyen tres pratique de localiser visuellement les zones d'un circuit qui sont susceptibles de se degrader

Style APA, Harvard, Vancouver, ISO itp.

24

Vincent, Emmanuel. "Étude des propriétés de dégradation du système SI/SIO#2 : application a la fiabilité des filières CMOS submicroniques." Grenoble INPG, 1996. http://www.theses.fr/1996INPG0126.

Pełny tekst źródła

Streszczenie:

Compte tenu de la reduction spectaculaire des dimensions critiques des dispositifs elementaires utilises dans la fabrication des circuits integres, les questions de fiabilite des dielectriques minces des technologies cmos submicroniques sont au cur des preoccupations de l'industrie des semiconducteurs. Dans ce contexte, l'objet de ce memoire est l'etude des phenomenes physiques responsables de la degradation des isolants intervenant dans les dispositifs mos. Apres des rappels generaux sur le systeme si-sio#2 et sur les methodes de caracterisation utilisees, nous presentons dans le deuxieme chapitre les caracteristiques de piegeage en volume des oxydes minces d'epaisseur entre 5,5 nm et 12 nm. Nous mettons clairement en evidence le caractere universel de la loi de degradation sur une large gamme d'epaisseurs et de conditions experimentales de contrainte et de temperature. Une tentative de modelisation de la loi universelle de piegeage est presentee sur la base d'un mecanisme de piegeage-depiegeage. Le troisieme chapitre est consacre aux problemes de claquage des dielectriques minces. Nous montrons de facon incontestable la relation existant entre les proprietes de piegeage et le phenomene de claquage. En particulier, nous demontrons l'existence d'une charge critique piegee en volume lors du claquage dont nous soulignons l'importance comme parametre determinant pour la comprehension et l'evaluation du claquage dans les oxydes compte tenu de son invariance avec les conditions experimentales (intensite de la contrainte et temperature). L'existence de cette charge permet de proposer un modele de claquage fonde sur les caracteristiques de piegeage des isolants qui autorise pour la premiere fois une comprehension quantitative des donnees de claquage obtenues en fonction du mode de contrainte (a tension constante ou a courant constant). Enfin, nous illustrons dans le quatrieme chapitre la pertinence de l'etude des proprietes de piegeage pour l'evaluation de la qualite du systeme si/sio#2 a travers l'etude des performances d'oxydes nitrures sous n#2o

Style APA, Harvard, Vancouver, ISO itp.

25

Shams, Kollol 3085942. "Understanding the Value of Travel Time Reliability for Freight Transportation to Support Freight Planning." FIU Digital Commons, 2016. http://digitalcommons.fiu.edu/etd/2828.

Pełny tekst źródła

Streszczenie:

Today’s logistics practices are moving from inventory-based push supply chains to replenishment-based pull supply chains, leading to a lower and less centralized inventory, smaller shipment sizes, and more just-in-time deliveries. As a result, industries are now demanding greater reliability in freight transportation. Delays and uncertainty in freight transportation translate directly into additional inventory, higher manufacturing costs, less economic competitiveness for businesses, and higher costs of goods that are being passed on to the consumers. Given the growing demand in freight transportation, the emerging needs to better understand freight behavior for better policy and investment decisions, and the increasing role of reliability in freight transportation, this research aims at providing a) better understanding of how the freight system users value travel time reliability in their transportation decisions, and b) advanced methods in quantifying the user’s willingness to pay for the improvement of transportation related attributes, particularly travel time reliability. To understand how the freight industry values travel time reliability in their transportation decisions, and particularly the presence of user heterogeneity, this research designed and conducted a stated preference (SP) survey for freight users in road transportation. Based on the feedback received during the pilot stage, reliability was measured as the standard deviation of travel time and presented as a frequency of on-time and late delivery in the choice scenarios. The survey collected 1,226 responses from 159 firms in Florida between January and May 2016 via online and paper methods. Various modeling approaches were explored to estimate the willingness to pay (WTP) measures among freight users, including multinomial logit (MNL) and mixed logit model. Market segmentation and interaction modeling techniques were employed to investigate preference variations among user groups, commodity groups, product type, and various other shipment characteristics, including shipping distance and weight. In general, across all groups in the sample, values of $37.00 per shipment-hour ($1.53 per ton-hour) for travel time savings and $55.00 per shipment-hour ($3.81 per ton- hour) for improvements of reliability were found in this research. Furthermore, while investigating the effects of shipping characteristics on the user’s preference in WTP, the results suggested that shipping distance and weight were the two most important variables. The results of the study help advance the understanding of the impact of the performance of transportation systems on freight transportation, which will lead to policy and investment decisions that better serve the needs of the freight community.

Style APA, Harvard, Vancouver, ISO itp.

26

Moras, Albero Miquel. "Caracterización de la variabilidad dependiente del tiempo de MOSFETs ultraescalados para su modelado compacto." Doctoral thesis, Universitat Autònoma de Barcelona, 2017. http://hdl.handle.net/10803/457581.

Pełny tekst źródła

Streszczenie:

El transistor MOSFET es uno de los dispositivos más utilizados en multitud de aplicaciones electrónicas gracias a sus excelentes características de funcionamiento, su bajo consumo y su gran capacidad de miniaturización. El constante progreso de la tecnología microelectrónica ha permitido una reducción de las dimensiones de este dispositivo, lo que ha conllevado mejoras en las prestaciones de los circuitos integrados (CI). Sin embargo, cuando estas dimensiones alcanzan el rango nanométrico, aparecen diferentes fenómenos físicos de distinta naturaleza como efectos de canal corto, procesos cuánticos y/o aumento de los campos eléctricos dentro del dispositivo, que afectan a las prestaciones y a fiabilidad de dichos transistores. Relacionados con el aumento de los campos eléctricos han aparecido diferentes mecanismos de fallo como el Bias Temperature Instability (BTI), la Degradación por Portadores Calientes (CHC) y la Ruptura Dieléctrica (BD), entre otros, que repercuten negativamente en la fiabilidad del transistor y, a su vez, al funcionamiento de los CIs. En tecnologías actuales, tanto el BTI como el CHC son mecanismos que producen modificaciones en los parámetros eléctricos de los transistores. Ambos mecanismos se caracterizan por la degradación de la tensión umbral (incremento, ΔVth) y otros parámetros eléctricos relevantes del MOSFET, como por ejemplo la transconductancia, cuando son sometidos a estreses durante su funcionamiento en un circuito integrado. Tanto el BTI y como el CHC se atribuyen a la generación de trampas en el dieléctrico y en la interfaz entre el dieléctrico y el canal del transistor, convirtiéndose en uno de los principales problemas de fiabilidad de las tecnologías de ultraescaladas, ya que pueden afectar a la vida útil de los dispositivos y la de los circuitos. La rápida variación de la tensión umbral observada cuando finaliza el estrés ha resultado ser uno de los problemas que dificultan la caracterización del BTI. Cuando se utilizan las técnicas de caracterización convencionales, los efectos de degradación quedan subestimados debido a la rápida recuperación de Vth inherente al fenómeno. Para resolver este problema, se ha desarrollado una técnica de caracterización ultrarrápida con el objetivo de reducir el tiempo que transcurre entre la interrupción del estrés y la medida de Vth. Para complementar esta técnica, se ha desarrollado una metodología de extracción de parámetros basada en el modelo físico PDO (Probabilístic Defect Occupancy Model). Esta metodología permite reproducir ΔVth obtenida de la caracterización y obtener información de los defectos que contribuyen en la degradación de la tensión umbral. Además, en este trabajo se ha realizado un estudio sistemático de la influencia de la temperatura y la tensión de estrés en la puerta y el drenador (degradación de NBTI y CHC, respectivamente) en ΔVth. Para ello se han considerado diferentes condiciones de estrés con el fin de estudiar como se modifica la distribución de defectos que contribuyen a ΔVth. Para obtener la distribución se ha realizado un análisis unificado de los resultados, independientemente de las condiciones de estrés (BTI o CHC), en el contexto del modelo PDO. A través de la metodología presentada, se ha obtenido la distribución de defectos a partir de ΔVth medido experimentalmente para las diferentes condiciones de estrés. Finalmente, se han analizado los parámetros de pequeña señal del transistor MOSFET cuando se aplican diferentes tensiones NBTI en el rango de radiofrecuencias. Con el fin de obtener estos parámetros se ha desarrollado una metodología que relaciona el circuito de pequeña señal y los parámetros [S] medidos. Con el fin de transferir el cambio de los parámetros de pequeña señal debido a la tensión de estrés, se ha simulado un amplificador simple y analizado el producto ganancia ancho de banda. MOSFET transistor is one of the most used device many applications thanks to its excellent operation characteristics, low power consumption and high miniaturization capability. The microelectronic technology progress has allowed reducing the MOSFET dimensions, which has led to improve the performance of integrated circuits (IC). However, when such dimensions reach the nanometric range, different physical phenomena such as short-channel effects, quantum processes and/or increase of electric fields in the device appear affecting the performance and reliability of transistors. During the device operation in the circuit, due to the large electric fields and temperature within the device, several aging mechanisms such as Bias Temperature Instability (BTI) or Channel Hot Carrier degradation (CHC), which progressively modify the initial device electrical characteristics, appear. Both mechanisms are characterized by the degradation of threshold voltage (shift, ΔVth) and other relevant electrical parameters of the MOSFET, like transconductance, when they are subjected to an electrical stress during its operation in an integrated circuit. BTI and CHC degradation, which are attributed to trap generation in the dielectric-bulk interface when high electric fields are applied to the transistor, are one of the main reliability problems of ultrascaled technologies that can limit the lifetime of devices and circuits The recovery of the threshold voltage is one of the issue that makes difficult the BTI characterization because of VTH changes very fast when the electrical stress is removed. For BTI studies, when the conventional characterization techniques are used, the degradation effects are underestimated due to fast recovery processes inherent to the phenomenon. To solve this problem, ultrafast characterization technique has been developed with the aim of studying the BTI degradation in pMOS transistors by acquiring the threshold voltage shift in very short times after the electrical stress removal. In addition, parameter extraction methodology based on Probabilistic Defect Occupancy model (PDO) for the BTI has been developed with the aim of reproducing and fitting the experimental ΔVth, as a function of time, and obtaining the defect distribution parameters and also the permanent part dependence which takes part during the stress/recovery stage. In this work, the influence of the temperature and the high electric fields at the gate and drain terminals (NBTI and CHC degradation, respectively) on the ΔVth has been analyzed in large area pMOSFETs. In addition, different stress conditions have been applied in order to know how those conditions modify the defect distribution that takes part in ΔVth. To obtain the distribution, a unified analysis of the results, regardless of the stress conditions (BTI and CHC) has been done in the context of the PDO model. By means of the methodology presented above, the defect distribution has been obtained and its dependence on the different stress conditions has been studied. Knowing how defect distribution changes with the stress conditions will allow to transfer the effects of NBTI and CHC degradation at device level up to the circuit level in order to evaluate how the device properties affect the circuit performance and reliability. Finally, the MOSFET small signal parameters have been analyzed when different NBTI stresses at the radiofrequency range are applied to the MOSFET. In order to get those parameters, a methodology that takes into account the small signal circuit and the measured [S] parameters has been developed. To transfer the small signal parameters shift, due to the stress, to the circuit level, a simple amplifier has been simulated and the gain bandwidth analyzed.

Style APA, Harvard, Vancouver, ISO itp.

27

Jacquet, Thomas. "Reliability of SiGe, C HBTs operating at 500 GHz : characterization and modeling." Thesis, Bordeaux, 2016. http://www.theses.fr/2016BORD0354/document.

Pełny tekst źródła

Streszczenie:

Le sujet de cette thèse est l’analyse de la fiabilité des transistors bipolaires à hétérojonction SiGe:C et descircuits intégrés associés. Dans ce but, un modèle compact prenant en compte l’évolution des caractéristiquesdes transistors SiGe:C a été développé. Ce modèle intègre les lois de vieillissement des mécanismes dedéfaillance des transistors identifiés lors des tests de vieillissement. Grâce aux simulations physiques TCADcomplétées par une analyse du bruit basses fréquences, deux mécanismes de dégradations ont été localisés. Eneffet, selon les conditions de polarisation, des porteurs chauds se retrouvent injectés aux interfaces dutransistor. Ces porteurs chauds ont suffisamment d’énergie pour dégrader l’interface en augmentantprogressivement leurs densités de pièges. L’une des deux interfaces dégradées se situe au niveau del’’’espaceur’’ émetteur-base dont l’augmentation de la densité de piège dépend des porteurs chauds créés parionisation par impact. L’autre interface dégradée se situe entre le silicium et le STI dont l’augmentation dedensité de pièges dépend des porteurs chauds générés par ionisation par impact et/ou par génération Auger.En se basant sur ces résultats, une loi de vieillissement a été incorporée dans le modèle compact HICUM. Enutilisant ce modèle, l’étude de l’impact des mécanismes de défaillance sur un circuit amplificateur faible bruit aété menée. Cette étude a montré que le modèle compact intégrant les lois de vieillissement offre la possibilitéd’étudier la fiabilité d’un circuit complexe en utilisant les outils de conception standard permettant ainsi dediminuer le temps de conception global The SiGe:C HBT reliability is an important issue in present and future practical applications. To reduce the designtime and increase the robustness of circuit applications, a compact model taking into account aging mechanismactivation has been developed in this thesis. After an aging test campaign and physical TCAD simulations, onemain damage mechanism has been identified. Depending on the bias conditions, hot carriers can be generatedby impact ionization in the base-collector junction and injected into the interfaces of the device where trapdensity can be created, leading to device degradation. This degradation mechanism impacting the EB/spacerinterface has been implemented in the HICUM compact model. This compact model has been used to performreliability studies of a LNA circuit. The CPU simulation time is not impacted by the activation of the degradationcompact model with an increase in computation time lower than 1%. This compact model allows performing areliability analysis with conventional circuit simulators and can be used to assist the design of more robustcircuits, which could help in reducing the design time cycle L’affidabilità dei transistori a eterogiunzione SiGe:C è un aspetto molto importante nella progettazione circuitale,sia per le tecnologie attuali che per quelle in fase di sviluppo. In questo lavoro di tesi è stato sviluppato un modellocompatto in grado di descrivere i principali meccanismi di degrado, in modo da contribuire alla progettazione dicircuiti relativamente più robusti rispetto a tali fenomeni, ciò che potrebbe favorire una riduzione dei tempi diprogetto. A seguito di una campagna sperimentale e di un’analisi con tecniche TCAD, è stato identificato unmeccanismo principale di degrado. In particolari condizioni di polarizzazione, i portatori ad elevata energiagenerati per ionizzazione a impatto nella regione di carica spaziale, possono raggiungere alcune interfacce deldispositivo e ivi provocare la formazione di trappole. Solo la generazione di trappole relativa allo spaceremettitore-base è stata considerata nella formulazione del modello, essendo il fenomeno più rilevante. Ilmodello è stato utilizzato per effettuare alcuni studi di affidabilità di un amplificatore a basso rumore. Il tempocomputazionale non è significativamente influenzato dall’attivazione del modello di degrado, aumentando solodell’1%. Il modello sviluppato è compatibile con i comuni programmi di simulazione circuitale, e può essereimpiegato nella progettazione di circuiti con una migliore immunità rispetto ai fenomeni di degrado,contribuendo così a un riduzione dei tempi di progetto

Style APA, Harvard, Vancouver, ISO itp.

28

Laurent, Antoine. "Etude des mécanismes physiques de fiabilité sur transistors Trigate/Nanowire." Thesis, Université Grenoble Alpes (ComUE), 2018. http://www.theses.fr/2018GREAT024/document.

Pełny tekst źródła

Streszczenie:

En continuant à suivre la loi de Moore, les transistors ont atteint des dimensions de plus en plus réduites. Cependant pour les largeurs inférieures à 100nm, des effets parasites dits de canaux courts sont apparus. Il a ainsi fallu développer de nouvelles architectures, à savoir les transistors 3D, aussi appelés trigates, finfets ou encore nanofils. Le remplacement des transistors planaires utilisés depuis les années 60 par ces dispositifs tridimensionnels constitue une réelle rupture technologique et pose de sérieuses questions quant à la fiabilité de ces nouveaux composants électroniques. Parmi les spécificités des dispositifs 3D, on peut notamment citer l’utilisation de différents plans cristallins du silicium, les potentiels effets d’angle ou encore le confinement des porteurs de charge. Les principaux mécanismes de fiabilité doivent, à ce titre, être étudiés afin de prédire le vieillissement de tels dispositifs. Ainsi, l’évolution du transistor MOS et les limites de l’architecture planaire sont rappelées dans un premier temps. Les différents mécanismes de dégradation ainsi que les méthodes de caractérisation sont également exposés. Les défauts d’oxyde jouant un rôle important en fiabilité, l’impact sur la tension de seuil VT d’une charge élémentaire q selon sa localisation spatiale a été simulé. On a ainsi pu constater que l’influence de ces défauts change selon leur position mais aussi selon les dimensions du transistor lui-même. Par la suite, le manuscrit se concentre sur la dégradation BTI (Bias Temperature Instabilities). Une comparaison entre les transistors trigates et d’autres quasi planaires a ainsi été effectuée en mettant en évidence les effets de la largeur du MOSFET. Un autre mécanisme important de fiabilité est intitulé dégradation par porteurs chauds ou HC, hot carriers en anglais. Les principaux modèles développés sur les architectures planaires ont été rappelés puis vérifiés pour les transistors 3D. Lors de stress HC, les niveaux de courant sont tels que des effets d’auto-échauffement apparaissent et dégradent les paramètres électriques du dispositif. Cette contribution a alors dû être décorrélée de la contrainte porteurs chauds afin d’obtenir uniquement la dégradation HC. De manière similaire au BTI, les effets de la largeur du transistor ont également été analysés pour ce mécanisme de fiabilité. Enfin, l’effet des contraintes mécaniques dans le canal, telles que le strained-SOI ou l’apport de germanium, a été étudié non seulement du point de vue des performances mais également de la fiabilité. Nous avons alors pu en déduire le meilleur compromis performance/fiabilité réalisable By continuing to follow Moore’s law, transistors have reached ever smaller dimensions. However, from 100nm gate length, parasitic effects called short channel effects appear. As a result new architectures named trigate, nanowires or finfets have been developed. The transition from planar technology used for the last fifty years to 3D devices is a major technological breakthrough. The special features of these architectures like conduction over various crystalline planes, corner effects or carrier confinement effects raise numerous questions about their reliability. Main reliability mechanisms have to be study in order to evaluate 3D transistor aging. In this way, MOS transistor evolution and planar architecture limits have first been reminded. The electrical degradation mechanisms and their characterization methods have also been exposed. As oxide defects represent an important part of device reliability, impact on threshold voltage VT of an elementary charge q has been simulated in accordance to its spatial localization. Thus we can notice that the defect influence on VT change with at once its position and the device dimensions. Next, this manuscript focuses on Bias Temperature Instabilities (BTI). A parallel has been done between narrow Trigate devices and wide ones which can be considered as planar transistors and a width effect on NBTI (Negative BTI) degradation has been highlighted. Another major reliability mechanism is called hot carrier degradation. Its principle models developed on planar architecture have been remembered and their validity on Trigate transistors has been verified. During HC stress, current density can be so high that self-heating effects appear and degrade device electrical parameters. Therefore this contribution has been decorrelate from HC degradation in order to obtain the result of HC stress only. As in BTI chapter, width effect has also been evaluated for this reliability mechanism. Finally strain effects in channel region have been analyzed from both performance and reliability point of view. As a conclusion the best tradeoff between these two items has been determined

Style APA, Harvard, Vancouver, ISO itp.

29

Bonner, J. K. "Kirk", and Silveira Carl de. "Thermal Cycling Fatigue Investigation of Surface Mounted Components with Eutectic Tin-Lead Solder Joints." International Foundation for Telemetering, 1996. http://hdl.handle.net/10150/611418.

Pełny tekst źródła

Streszczenie:

International Telemetering Conference Proceedings / October 28-31, 1996 / Town and Country Hotel and Convention Center, San Diego, California Eutectic (63% tin-37% lead) or near-eutectic (40% tin-60% lead) tin-lead solder is widely used for creating electrical interconnections between the printed wiring board (PWB) and the components mounted on the board surface. For components mounted directly on the PWB mounting pads, that is, surface mounted components, the tin-lead solder also constitutes the mechanical interconnection. Eutectic solder has a melting point of 183°C (361°F). It is important to realize that its homologous temperature, defined as the temperature in degrees Kelvin over its melting point temperature (T(m)), also in degrees Kelvin, is defined as T/T(m). At room temperature (25°C = 298K), eutectic solder's homologous temperature is 0.65. It is widely acknowledged that materials having a homologous temperature ≥ 0.5 are readily subject to creep, and the solder joints of printed wiring assemblies are routinely exposed to temperatures above room temperature. Hence, solder joints tend to be subject to both thermal fatigue and creep. This can lead to premature failures during service conditions. The geometry, that is, the lead configuration, of the joints can also affect failure. Various geometries are better suited to withstand failure than others. The purpose of this paper is to explore solder joint failures of dual in-line (DIP) integrated circuit components, leadless ceramic chip carriers (LCCCs), and gull wing and J-lead surface mount components mounted on PWBs.

Style APA, Harvard, Vancouver, ISO itp.

30

Candelier, Philippe. "Contribution à l'amélioration de la fiabilité des mémoires non volatiles de type flash EEPROM." Université Joseph Fourier (Grenoble ; 1971-2015), 1997. http://www.theses.fr/1997GRE10245.

Pełny tekst źródła

Streszczenie:

L'augmentation continue de la densite d'integration des memoires non-volatiles de type flash eeprom passe par la comprehension des mecanismes de degradation intervenant dans le cadre du fonctionnement de ces memoires. Nous avons pu correler les degradations observees sur des dispositifs elementaires (transistors et capacites) aux derives des caracteristiques de la cellule flash. Cette etude demontre que de nouveaux modes de fonctionnement devront etre envisages. Le mode d'effacement par la source, habituellement utilise, pose des problemes d'optimisation technologique pour les cellules de faible longueur de grille (generation de trous chauds difficile a controler). Il devra vraisemblablement etre remplace par l'effacement fn qui est plus fiable pour les criteres d'endurance et de retention apres endurance. Parmi les degradations observees, le probleme principal est l'augmentation de la perte de charge avec l'amincissement des dielectriques et avec la degradation de l'oxyde de grille lors des cycles ecriture/effacement. Face au premier probleme, la mise en place d'une fonction de rafraichissement periodique semble necessaire. Face au second probleme, l'effacement fn a ete optimise en minimisant le champ electrique dans l'oxyde de grille par l'utilisation d'impulsions trapezoidales. Des progres technologiques importants (dielectriques interpolysilicium deposes, isolation laterale de type box) ont ensuite ete introduits dans le procede de fabrication afin permettre une integration plus poussee. La validation de ces evolutions technologiques ouvre les portes de la generation de cellules flash 0. 25 m. Finalement, face au probleme d'augmentation de la densite d'integration, la programmation multi-niveaux est une solution simple dont la fiabilite a ete amelioree grace a la realisation d'un systeme de programmation convergente. La faisabilite d'un doublement de capacite memoire a alors ete demontree.

Style APA, Harvard, Vancouver, ISO itp.

31

Couret, Marine. "Failure mechanisms implementation into SiGe HBT compact model operating close to safe operating area edges." Thesis, Bordeaux, 2020. http://www.theses.fr/2020BORD0265.

Pełny tekst źródła

Streszczenie:

Afin de répondre au marché florissant des applications térahertz, les filières BiCMOS atteignent désormais des fréquences de coupure supérieures à 0,5 THz. Ces performances dynamiques sont obtenues grâce aux améliorations technologiques apportées aux transistors bipolaires à hétérojonction (TBH) SiGe. Toutefois, cette montée en fréquence à entraîner un décalage du point de polarisation des transistors au plus proche, voir au-delà, de l’aire de sécurité de fonctionnement (SOA). En conséquence, de nombreux effets physiques « parasites » sont présents tel que l’ionisation par impact ou bien l’auto-échauffement pouvant potentiellement activer des mécanismes de défaillance et ainsi limiter la fiabilité à long terme du transistor. Dans le cadre de cette thèse, nous proposons une approche pour la description et la modélisation de la dégradation par porteurs chauds au sein des TBH SiGe fonctionnant aux frontières de la SOA. L’étude est basée sur une caractérisation approfondie en conditions statiques et dynamiques des transistors. Du fait de ses résultats de mesures, une modélisation de l’ionisation par impact et de l’auto-échauffement a été proposé permettant d’étendre, avec précision, le domaine de validité des modèles compact commerciaux (HiCuM). Au-vu du fonctionnement aux limites de la SOA, une campagne de vieillissement a été mise en place afin de mieux cerner l’origine physique de ce mécanisme de défaillance. De ce fait, il a été démontré que la dégradation par porteurs chauds entraîne la création de densités de pièges au niveau de l’interface Si/SiO2del’espaceur émetteur-base induisant un courant de recombinaison supplémentaire dans la base. Un modèle compact intégrant des lois de vieillissement (HiCuM-AL) a été développé prédisant l’évolution des paramètres électriques d’un transistor ou d’un circuit au travers d’un facteur de vieillissement accéléré. Afin de faciliter son utilisation dans des outils de conception assistée par ordinateur (CAO), les lois de vieillissement ont été adaptées en fonction de la géométrie et de l’architecture de l’espaceur émetteur-base. Le modèle a démontré sa robustesse et sa précision pour plusieurs technologies de TBH SiGe et, ce, pour différentes conditions de vieillissement. De plus, une étude de la fiabilité de plusieurs architectures de circuits intégrés a été réalisé menant à une localisation précise des régions les plus sensibles au mécanisme de dégradation par porteurs chauds. Le modèle HiCuM-AL ouvre ainsi la voie à des simulations optimisées pour la conception de circuits millimétriques en termes de performances, mais aussi de fiabilité à long terme In an ever-growing terahertz market, BiCMOS technologies have reached cut-off frequencies beyond 0.5 THz. These dynamic performances are achieved thanks to the current technological improvements in SiGe heterojunction bipolar transistors (HBTs). However, these increased performances lead to a shift of the transistors bias point closer to, or even beyond, the conventional safe-operating-area (SOA). As a consequence, several "parasitic" physical effects are encountered such as impact-ionization or self-heating which can potentially activate failure mechanisms, hence limiting the long-term reliability of the electric device. In the framework of this thesis, we develop an approach for the description and the modeling of hot-carrier degradation occurring in SiGe HBTs when operating near the SOA edges. The study aims to provide an in-depth characterization of transistors operating under static and dynamic operating conditions. Based on these measurements results, a compact model for the impact-ionization and the self-heating has been proposed, ultimately allowing to extend the validity domain of a commercially available compact model (HiCuM). Considering the operation as close as possible to the SOA, an aging campaign was conducted to figure out the physical origin behind such failure mechanism. As a result, it has been demonstrated that hot-carrier degradation leads to the creation of trap densities at the Si/SiO2interface of the emitter-base spacer which induces an additional recombination current in the base. A compact model integrating aging laws (HiCuM-AL) was developed to predict the evolution of the transistor/circuit electrical parameters through an accelerated aging factor. For ease of use in computer-aided design (CAD) tools, the aging laws have been scaled according to the geometry and architecture of the emitter-base spacer. The model has demonstrated its robustness and its accuracy for different SiGe HBT technologies under various aging conditions. In addition, a study on the reliability of several integrated circuits has been performed leading to a precise location of the most sensitive regions to the hot-carrier degradation mechanism. Thus, the HiCuM-AL model paves the way to perform circuit simulations optimizing the mm-wave circuit design not only in term of sheer performances but also in term of long-term reliability

Style APA, Harvard, Vancouver, ISO itp.

32

Faynot, Olivier. "Caractérisation et modélisation du fonctionnement des transistors MOS ultra-submicroniques fabriqués sur films SIMOX très minces." Grenoble INPG, 1995. http://www.theses.fr/1995INPG0121.

Pełny tekst źródła

Streszczenie:

Ce memoire est consacre a la caracterisation et a la modelisation des transistors mos fabriques sur des films simox tres minces. Dans le premier chapitre, outre l'orientation de la microelectronique, nous detaillons l'interet potentiel que peut susciter la technologie soi pour les applications basse-tension. Ensuite, nous analysons les phenomenes de couplage d'interfaces apparaissant dans deux types de conduction de transistors totalement desertes: la conduction par canal d'inversion et la conduction par canal d'accumulation. Puis, les effets de canaux courts sont etudies dans l'objectif d'optimiser l'architecture des transistors soi ultra-submicroniques. Les phenomenes lies a l'ionisation par impact sont ensuite presentes pour les deux types de conduction. Un procede simple de fabrication est alors decrit et les resultats experimentaux des transistors et des circuits mettent en avant les avantages du soi pour les applications basse-tension. Le dernier chapitre est dedie a la caracterisation des phenomenes de porteurs chauds des transistors soi completement desertes

Style APA, Harvard, Vancouver, ISO itp.

33

Bestory, Corinne. "Développement de stratégies de conception en vue de la fiabilité pour la simulation et la prévision des durées de vie de circuits intégrés dès la phase de conception." Thesis, Bordeaux 1, 2008. http://www.theses.fr/2008BOR13627/document.

Pełny tekst źródła

Streszczenie:

La conception en vue de la fiabilité (DFR, Design for Reliability) consiste à simuler le vieillissement électrique des composants élémentaires pour évaluer la dégradation d'un circuit complet. C'est dans ce contexte de fiabilité et de simulation de cette dernière, qu'une stratégie de conception en vue de la fiabilité a été développée au cours de ses travaux. Cette stratégie, intégrant une approche « système » de la simulation, s'appuie sur l'ajout de deux étapes intermédiaires dans la phase de conception. La première étape est une étape de construction de modèles comportementaux compacts à l'aide d'une méthodologie basée sur une approche de modélisation multi niveaux (du niveau transistor au niveau circuit) des dégradations d'un circuit. La seconde étape consiste alors l'analyse descendante de la fiabilité de ce circuit, à l'aide de simulations électriques utilisant ses modèles comportementaux dits « dégradables », afin de déterminer les blocs fonctionnels et/ou les composants élémentaires critiques de l'architecture de ce dernier, vis-à-vis d'un mécanisme de défaillance et un profil de mission donnés. Cette analyse descendante permet aussi d'évaluer l'instant de défaillance de ce circuit. Les dispersions statiques, lies au procédé de fabrication utilisé, sur les performances d'un lot de CIs ont aussi été prises en compte afin d'évaluer leur impact sur la dispersion des instants de défaillance des circuits intégrés. Ces méthodes ont été appliquées à deux mécanismes de dégradation : les porteurs chauds et les radiations Design for reliability (DFR) consists in assessing the impact of electrical ageing of each elementary component, using electrical simulations, on performance degradations of a full device. According to DFR concept and reliability simulation, theses works present a new DFR strategy. This strategy based on the integration of two intermediate phases in the ICs and SoC design flow. The first phase is a bottom-up ageing behavioural modelling phase of a circuit (from transistor level to circuit level). The second phase is a « top-down reliability analyses » phase of this circuit, performing electrical simulations using its ageing behavioural models, in order to determine critical functional blocks and / or elementary components of its architecture according to a failure mechanism and a given mission profile. Theses analyses also allow determining the failure time of this circuit. Statistical dispersions on ICs performances, due to the used manufacturing process, have been taking into account in order to assess their impact on failure time dispersions of a ICs lot. The method has been applied on two degradation mechanisms: hot carriers and radiations

Style APA, Harvard, Vancouver, ISO itp.

34

Tsao, Chih-Pin, and 曹志彬. "Hot-Carrier reliability in deep submicron CMOS device." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/16925700898041641574.

Pełny tekst źródła

Streszczenie:

碩士 國立成功大學 微電子工程研究所碩博士班 90 In this study, the effects of hot-carrier induced drain current degradation and gate leakage current induced by ultra-thin gate oxide on 0.18μm and 0.15μm CMOS devices will be investigated. In the first chapter, the background of hot-carrier effects will be discussed. Results show that in deep submicron device, the worst case of hot-carrier induced drain current degradation is characterized at drain voltage higher than 0.1V which was well known as the worst case condition in long channel device. The worst case of characterized Vd was found to lager at higher temperature and substrate bias. A simplified model was presented to explain this new observation. Results show that the lowering of quasi-fermi level and the effect of the velocity saturation region (DL) contribute to the monotonically decrease ΔID/ID (%) as a function of measured VD. However, Qinv near the drain side also decreases since Vc increases. This mechanism results in the increase in DId/Id. Hence, the value of the worst case of characterized Vd is determined by this two competing mechanisms. In the third chapter, enhanced hot-carrier induced Id degradation under high gate voltage stress was observed in pMOSFETs. Some mechanisms which may contribute to this phenomenon are discussed here。Results show that (I) F-N tunneling-current stress has finite effect on enhanced high gate voltage stress although gate oxide electric field as high as above 15MV/cm was applied. Anode hole injection model was adopted to explain the server F-N tunneling effect on pMOSFET than on nMOSFET. The hole component of the injected F-N tunneling-current was found to the dominant mechanism. (II) Electron tunneling from the gate due to ultra-thin gate oxide and Auger recombination assisted hot hole energy gain process were found to contribute to this phenomenon. Besides, this enhancement in Id degradation is more significant under high temperatures or lower supply voltages. Finally, in the last chapter, future work is discussed.

Style APA, Harvard, Vancouver, ISO itp.

35

Lee, Jia-Rui, and 李佳叡. "Studies on Hot-Carrier Reliability in High-Voltage MOSFETs." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/46789891396748452586.

Pełny tekst źródła

Streszczenie:

博士 國立成功大學 微電子工程研究所碩博士班 96 In this dissertation, the hot-carrier-induced degradation in 0.35 μm n-type self-aligned lateral double-diffused MOSFET (LDMOS) and p-type drain-extended MOSFET (DEMOS) devices are studied. When the nLDMOS device is used in a power switching circuits with an unclamped inductive load, the off-state avalanche breakdown occurs during on-state to off-state transient. The device degrades because of the high electric field and impact ionization located near the drain side poly-gate edge. The main mechanism of device degradation is the interface states and positive oxide-trapped charges created by breakdown-induced hole injection. The interface states degrade device turn-on resistance (Ron) however positive oxide-trapped charges reduce the series resistance. The degradation has the tendency to saturate, which in consistent with the saturation of interface states and oxide-trapped charges generation. Moreover, increasing the device drift drain (NDD) region dosage can reduce the generation of interface states, leading to an improved degradation. Besides Ron degradation, the off-state breakdown voltage (BVdss) increases while off-state avalanche breakdown occurs. It is suggested that the main mechanism of BVdss increase is the hole trapping created by hole injection. TCAD simulation reveals that hole trapping attract mirror electrons at Si/SiO2 surface and lower the potential contour crowding and reduce lateral and vertical electric field under drain side spacer. As a consequence, the impact ionization rate at breakdown point is lowered, leading to a higher breakdown voltage. While the nLDMOS devices operate on on-state, the devices degrade due to high operating voltage and high electric field. The location of hot-carrier-induced interface states varies with different stress gate voltage. The interface states located in accumulation region under poly-gate have little effect on Idlin degradation. As a result, interface states located in drain-side spacer region dominate Idlin degradation when interface states located in channel region are negligible. In our experiment, increasing NDD dosage results in improved Idlin degradation. TCAD simulations reveal that high NDD dosage increases impact ionization rate in accumulation and channel regions, but reduces impact ionization rate in spacer region, leading to an improved Idlin degradation. Finally, the drain current shifts after hot carrier stress in pDEMOS transistors is studied. The drain saturation (Idsat) and linear current (Idlin) both increase after hot carrier stress due to hot electron injection and electron trapping. Electron trapping reduces the resistance of p-drift region hence increases drain current. Moreover, the current shifts are dependent on the length of drain extended region under poly gate. Device with longer drain extended under poly produces less current increment after Igmax stressing. TCAD simulation reveals that the path of current flow under Idlin and Idsat condition can explain the relation between the drain extended overlap and the current shifts.

Style APA, Harvard, Vancouver, ISO itp.

36

Li, Jian Fang, and 李劍芳. "Reliability analysis for mid-ship structure of bulk carrier." Thesis, 1995. http://ndltd.ncl.edu.tw/handle/49487316057887387484.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

37

Pagey, Manish Prabhakar. "Hot-carrier reliability simulation in aggresively scaled MOS transistors." 2003. http://etd.library.vanderbilt.edu/ETD-db/available/etd-12032003-100902/.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

38

Wu, Tai-Ching, and 吳泰慶. "Hot Carrier Reliability in 12V High Voltage P-LDMOS Transistors." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/30479749998144585484.

Pełny tekst źródła

Streszczenie:

碩士 國立成功大學 微電子工程研究所碩博士班 97 In this thesis, the experiment mainly studies on the hot-carrier reliability of a 0.35 μm p-type lateral double diffusion metal oxide semiconductor field-effect-transistor. Base on the degradation of every parameter, we can analyze the mechanism causing the device degradation. First, the differences between HV device structure and normal LV MOS structure are introduced. The development of LDMOS device is also introduced. As process scaling down, the reliability becomes an important issue to discuss. After hot carrier stress experiment on standard dimension device, some parameters under different gate bias result in different degradation trends. TCAD simulation and charge pumping method are used to confirm the damage location induced different degradation. At last we study on lifetime issue to compare the device reliability. First we need a degradation index in lifetime model. And then we process hot carrier stress experiment on different dimension devices (S, L, and C). Then the extracted lifetime results are compared to find out which dimension variation will improve the device reliability.

Style APA, Harvard, Vancouver, ISO itp.

39

Chen, Shiang-Yu, and 陳翔裕. "Hot Carrier Reliability of 12V High Voltage n-LDMOS Transistors." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/34503827838537514146.

Pełny tekst źródła

Streszczenie:

碩士 國立成功大學 微電子工程研究所碩博士班 94 In recent years, LDMOS transistors have been widely used in high voltage integrated circuits (HVIC). That’s due to its process flow being compatible with low voltage CMOS devices. In some applications, LMDOS transistors operate under high gate and drain voltage, thus hot carrier reliability becomes a serious concern. In this thesis, hot carrier reliability of LDMOS transistors will be investigated in detail. First of all, LDMOS transistors designed to operate at Vds=12V are studied. Substrate current (Isub) of the devices continually increases as measure gate voltage, thus indicates that Kirk effect is significant even at low gate voltage region. In addition, based on experiment and simulation results, two degradation mechanisms are observed in this device at low and high gate stress voltage. The degradation of device parameters such as Gm(max), on resistance(Ron) also supports our theory. At the same time, anomalous increase of saturation current (Id(sat)) is observed after low gate voltage stress. To improve the lifetime of the LDMOS transistors, devices with longer drift region length (Ld) are also investigated. Owing to the large decrease of lateral electric field, degradation of device characteristics is significantly reduced. Isub in longer Ld device is also much lowered at low gate voltage region. In other words, it implies that Kirk effect occurs later in longer Ld devices. Moreover, based on experiment results damage is more uniformly distributed in the channel and drift region in this device. Finally, depending on the various applications, devices with different gate oxide thickness are designed. In this part, hot carrier reliability of LDMOS transistors with thin gate oxide will be investigated. Based on experiment results, two competing mechanisms dominate the Ron degradation at low and high stress gate voltage. One mechanism will lead to the increase of Ron degradation, while the other one will result in the decrease of Ron degradation.

Style APA, Harvard, Vancouver, ISO itp.

40

Hsiao, Mei-Yi, and 蕭美宜. "Effect of Oxygen Annealing on Hot-Carrier Reliability of HfO2 nMOSFETs." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/c46sx3.

Pełny tekst źródła

Streszczenie:

碩士 國立臺北科技大學 機電整合研究所 99 In order to avoid the short channel effect in the MOSFET, the thickness of the dielectric has gradually become thinner. However, the serious problems of leakage current and reliability due to the thinning oxide are also unavoidable. Therefore, using high-k materials passes into one of the most significant studies. After many years of researches, the Hafnium-based high-k materials emerge as the most promising candidates to replace SiO2 and SiON gate dielectrics. It has been reported that the oxygen vacancy defects of high-k dielectrics can be passivated by annealing process, and the device degradation of bias temperature instability (BTI) tests can be improved. However, the hot carrier injection (HCI) is still an important reliability issue. And only few literatures concerned about the channel hot carrier reliability for adding oxygen in post-deposition annealing. Hence, this study is concentrated on this subject. The nMOSEFT experimental samples were fabricated from 45 nm node high performance logic technology of UMC. The process of HfO2 dielectric layer was deposited by atomic layer deposition (ALD). The wafers were then annealed with and without oxygen after ALD. The channel width of the nMOSFETs is 10 μm and channel lengths are 10 μm and 0.1 μm. In this research, the different stress voltages and temperatures are included in the experiment. Consequently experimental data are used to figure out the dependence of degradation on stress voltage and temperature, and to determine the difference of two kinds of wafers. The experimental results show that the basic electric characteristics have no significant improvement for the process with oxygen post-deposition annealing. After the CHC stress, the degradation in those short channel nMOSFETs reveals larger than that in long channel. The threshold voltage shift becomes larger as stress voltage and temperature increasing. From the analyzed data, the process with oxygen post-deposition annealing can effectively reduce the degradation of the devices; it should be due to the passivation of oxygen vacancies during the oxygen annealing.

Style APA, Harvard, Vancouver, ISO itp.

41

Yang, Hui-Ting, and 楊惠婷. "A Study on the Hot-Carrier Reliability of 200V SOI PLDMOS." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/17003352917403750503.

Pełny tekst źródła

Streszczenie:

碩士 亞洲大學 資訊工程學系碩士班 97 The reliability of the high voltage P-LDMOS is examined extensively by moving the impact ionization area and varying the surface electric field in the drift region. Breakdown walkout in high-voltage P-LDMOS devices on a thin SOI layer is demonstrated closely related to gate-metal field plate extension and gate channel length. The two field peaks along the channel can be reduced by varying the impact ionization area properly. N-well ion implantation dose monitoring and gate-metal field plate extensions are also studied to effectively improve the breakdown voltage and the reliability of the device with 12 micron P-drift length on SOI for 200V applications.

Style APA, Harvard, Vancouver, ISO itp.

42

Liu, Xin-chang, and 劉信昌. "Reliability Analysis of a Maintained Bulk Carrier Subjected Corrosion and Fatigue." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/19944119167581906619.

Pełny tekst źródła

Streszczenie:

碩士 國立成功大學 系統及船舶機電工程學系碩博士班 97 In general the structure of large ships are made of steel, the corrosion and fatigue of the steel may occur due to the waves and harsh environment. The purpose of this study is to assess fatigue translate into structure failure and reliability analysis on the structure of maintained ships after failure under the effect of combined corrosion and fatigue crack. The reliability analysis of fatigue crack is broken down into two failure model, for one is concerning the reliability of the possession of initial crack in fatigue crack growth, the other is regarding fatigue reliability before initial crack. The process of corrosion also can be separated into two stages：the first is the time during which the coating protection is effective, the second starts when the effectiveness of the coating is ineffectual and general corrosion starts occurring. Since the time to crack initiation and the termination of coating life are random variables, and thus the reliability of initial crack and the probability of coating failure are taken into consideration when it comes to the reliability of ship’s structure. Finally, based on the combined effects of fatigue and corrosion, the reliability or the probability of failure of a bulk carrier is studied to make the improvements on repairing.

Style APA, Harvard, Vancouver, ISO itp.

43

Kuo, Yu-Chen, and 郭育禎. "Characteristics and Hot Carrier Reliability in 40V n-type LDMOS Transistors." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/22495897312119913693.

Pełny tekst źródła

Streszczenie:

碩士 國立成功大學 微電子工程研究所碩博士班 97 In this thesis, device characteristics and hot carrier reliability of n-type LDMOS transistors with different device dimension are investigated. The device used in this thesis has four main layout parameters: channel length, accumulation length, length of drift region with gate control and length of drift region without gate control. As for device characteristics, the effect of parameters of channel length and accumulation length are more significant than that of parameters of drift region with gate control and length of drift region without gate control. The unexpected connection between Ron, BVoff and accumulation length can be explained by TCAD Simulation. Then we choose a standard device dimension to perform constant voltage hot carrier stress and discuss the hot carrier degradation phenomenon and mechanism. The degradation of Ron reveals different power index of degradation for different stressed bias. By means of TCAD simulation and charge pumping analysis, the phenomenon of anomalous degradation can be discussed and explained in detail. Besides, effects of device dimension on Ron lifetime are investigated. Among prodigious enhancement of lifetime is certain as accumulation length increased. So, accumulation length is reduced and the effect of this change on Ron and Idsat are discussed. Charge pumping analysis and TCAD simulation are used to evidence for the stress experimental results. Finally, compare with device characteristics and hot carrier stressed experiments. We can conclude that accumulation length is an important concern in this device when considering both device performance and hot carrier reliability. Such an analysis can provide useful feedback in designing LDMOS devices.

Style APA, Harvard, Vancouver, ISO itp.

44

Yih, Cherng-Ming, and 易成名. "Investigation of Hot-Carrier Injection Induced Reliability Issues in Flash Memories." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/73427801549497138777.

Pełny tekst źródła

Streszczenie:

博士 國立交通大學 電子工程系 87 Hot carrier induced reliability issues have become increasingly important for miniaturized flash memory design. These reliability issues include hot carrier related issues, such as oxide damage, program/erase cycling endurance, disturbance, and data retention. In this dissertation, the hot-carrier injection induced reliability problems in stacked-gate flash memories is investigated. First, a new model based on the charge-balance theory was proposed to accurately calculate the floating gate voltage. Based on the new model, the method to determine the capacitive coupling coefficients and a compact SPICE model was developed. Then, an oxide damage characterization method was developed for simultaneously determining the lateral distributions of interface states (Nit) and oxide charges (Qox) under both channel-hot-electron programming bias and source FN erase bias stress conditions. According to the extracted profiles of Nit and Qox, a new gate current model was successfully developed for the first time by taking the hot-electron stress generated Nit and Qox into account. In this model, we suggest that Nit filled with electrons will serve as a new scattering center and reduce the hot-electron injection probability. The generated Qox is also introduced as an additional factor affecting the potential barrier at the Si-SiO2 interface. Moreover, the oxide-field dependent stress-induced leakage current (SILC) as well as its related disturbance on the source FN erased flash memory has been studied by using a new approach. The salient features of the method are two fold. One is that the individual contributions of SILC and disturbance due to either carrier charging/discharging in the oxide or positive charge-assisted/trap-assisted tunneling (PCAT/TAT) of electrons into the floating gate can be separated. The other one is that it is very sensitive to determine the ultra-low SILC (< 10-20 A). In this study, we first observed that the generated Nit dominates the gate current degradation not only at the IB,max stress condition but also at the IG,max stress condition. The major programming degradation mechanisms of flash memory cells after P/E cycles due to Nit was also identified. In addition, we also observed that the carrier charging/discharging in the oxide is the main disturb mechanism at low oxide field. At high oxide field, PCAT/TAT of electrons into the floating gate is the major cause for the disturb failure.

Style APA, Harvard, Vancouver, ISO itp.

45

Liu, Jun-Lin, and 劉駿霖. "Reliability Analysis of a Double Hull Bulk Carrier with Corrosion Effects." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/65529682437162812242.

Pełny tekst źródła

Streszczenie:

碩士 國立成功大學 系統及船舶機電工程學系碩博士班 93 Generally, the hull structures usually are made of steel, however the steel will deteriorate under the environment of the high salt and the high humidity. In order to solve the damage of ship due to corrosion, many experts have developed several kinds of linear or non-linear ship corrosion model respectively by way of material experiment、statistics data and various corrosion model. In general, non-linear corrosion model can explain the real corrosion process more than linear corrosion model. Therefore, the non-linear corrosion model is used in present investigation. 　In this study, the new time variant non-linear ship corrosion model is proposed and other two kinds of corrosion models are used to evaluate the corrosion effects on ship plates. A double hull bulk carrier is selected as an example to exam the method of FORM and SORM. The reliability index of the ship structure under various failure modes is studied. In addition, different recording periods are also considered, the comparison of corrosion reliability between the ship with stationary repair period and the ship without any repair is presented.

Style APA, Harvard, Vancouver, ISO itp.

46

Kuo, Jui-Min, and 郭瑞旻. "Hot-carrier Induced Reliability Degradation in High Voltage P-LDMOS Transistors." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/44883155072548759819.

Pełny tekst źródła

Streszczenie:

碩士 國立清華大學 電子工程研究所 100 In this thesis, the p-type lateral diffused MOS (LDMOS) transistor used in this work is implemented with a 0.5 μm 2p3m high-voltage process. To investigate the reliability issue, charge pumping method is used to detect the interface states of the device. And to combine TCAD (Technology Computer Aided Design) simulation supports the analysis of the device. First, we have background review, which contains the introduction of the high-voltage device, the mechanism of hot-carrier degradation, and the methodology of charge pumping. Then the measurement set-up and the characteristic parameters extraction for the virgin devices are discussed. According to measurement result, we observe that Kirk effect will degrade the reliability in short channel (L = 1 μm) device. Due to Kirk effect, it produces a specific double-hump bulk current in short channel device. The hot-carrier degradation experiment is performed in long channel (L = 5 μm) and short channel (L = 1 μm) devices respectively. Both two channel lengths have mainly damage in the P-well region when stresses at the first peak. And when stressed at the second peak, there has serious degradation in whole device. The shift of electric field makes the degradation of on-resistance (Ron) and the shift of threshold voltage (VT, on). The simulation can give the reasonable explanation.

Style APA, Harvard, Vancouver, ISO itp.

47

Lu, Ying-Hsin, and 盧頴新. "Investigation on the Reliability and Hot Carrier degradation in Advance MOSFET." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/56e373.

Pełny tekst źródła

Streszczenie:

博士 國立中山大學 物理學系研究所 107 Since 1960, the world’s the first metal-oxide-semiconductor-field-effect transistors (MOSFETs) were invented by Kahng and Atalla in Bell Lab. The transistor length is 25 μm, and gate oxide thickness is 100nm. Nowadays, MOSFETs have become the dominant devices for ultra-large-scale integration (ULSI) circuits due to its low cost, power consumption and easy to scale down. In 1965, Gordon Moore, one of Intel''s founders, first proposed Moore’s Law: The number of components per integrated circuit will doubling every year. And with the advancement of technology, the 10 nm fin transistor (fin FET) has been mass-produced and applied to advance electronic products. In the micro-engineering of the integrated circuit, in addition to the miniaturization of the channel length as the primary key technology; the threshold voltage (Vth) in the modulated integrated circuit is also one of the key technologies. For example, ultra-thin oxide layers, ion implantation modulation of channels, gate stack modulation, etc. Different modulation methods will have different effects on the basic electrical properties and reliability of the transistor. Therefore, in the first part, we mainly study the metal annealing sequence in gate stack modulation. In this section, we study the effect of metal pre/post metal deposition annealing on the cerium oxide layer. In the initial electrical characteristics, the most apparent difference is threshold voltage (Vth) resulting from the work-function difference between the gate material and the semiconductor. Furthermore, fast I-V measurements indicate that the device with post-metal deposition annealing shows more degradation of Vth in NBTI, which originates from the more nitrogen interstitial defects in HfO2. This phenomenon is confirmed to be due to the process-related pre-existing defects by an analysis of double sweep fast I-V measurements. In order to further verify the effect of nitrogen interstitial defects on the MOSFET, in the second part we used fast I-V measurements to study the effect of different TiN gate nitrogen concentrations on the interstitial defect in the HfO2 layer. In the previous section, we discovered the existence of nitrogen interstitial defects through fast I-V measurement and NBTI. In this part, we can further find that the higher nitrogen content in the metal, and the nitrogen is affected by the thermal diffusion, the more nitrogen interstitial defects will exist in the HfO2 layer. In the reliability, the nitrogen interstitial defect takes the role of the hole trapping center in the HfO2 layer. Therefore, when performing NBTI at room temperature, we observed that the main cause of transistor degradation is mostly due to hole trapping, rather than the decline of Subthreshold Swing (S.S.) caused by the traditional Reaction-Diffusion Model. Moreover, through the fast I-V double sweep measurement after NBTI, it can be found that devices with more nitrogen interstitial defects have a large hysteresis after deterioration. This also means that the bond inside the HfO2 layer is affected by the nitrogen interstitial defect, and it is easier to break the bond to form a new hole capture center. Therefore, for the nitrogen interstitial defects for the first and second portions. In the third part, we eliminate the oxygen vacancies and nitrogen interstitial defects in the HfO2 layer by different nitridation process. Based on previous studies, the oxygen vacancy in hafnium oxide could be passivated by the diffusion nitrogen, thus, enhancing the performance and reliability of n-MOSFET. On the other hand, as for p-MOSFET device, the nitrogen diffuses into the channel interface to generate interface defects, causing S.S. degradation to the device. However, in the HfO2 thin film, the nitrogen interstitial defect will be generated when the concentration of nitrogen is higher. These interstitial defects are located in HfO2 with the energy level below the mid-gap. Therefore, the holes can be trapped into the nitrogen interstitial defects while they transport from the channel to the gate. This work investigates the reduction of nitridation time and annealing time to device to further verify the hafnium oxide layer of nitrogen and oxygen vacancies bonding to reduce nitrogen interface defects. The influence of different nitrogen concentration and annealing time to device performance and reliability are also investigated. Finally, In the evolution of MOSFET technology, in addition to the evolution of the transistor in Moore''s Law, another research direction is to increase the diversity of functions, called More than More. In its development, it contains many different functional components, such as RF, high voltage components, CMOS image sensor, etc. In this section we will discuss an abnormal recovery phenomenon induced by hole injection during hot carrier degradation in silicon-on-insulator n-type metal-oxide-semiconductor transistors. How the hole injection induces the abnormal recovery behavior can be clarified by different hot carrier degradation (HCD) measurement sequences. According to this HCD result, the channel surface energy band is drawn down and the interface defect will be temporarily shielded, an effect caused by the trapped hole. Furthermore, results of different stress voltage experiments indicate that the amount of hole injection is determined by the electric field between the gate and drain.

Style APA, Harvard, Vancouver, ISO itp.

48

Ze-Wei, Jhou. "DC Hot Carrier Reliability at Elevated Temperatures for nMOSFETs Using 0.13Mum Technology." 2005. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0006-2007200517293700.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

49

Wu, Kuo-Ming, and 吳國銘. "Development and Hot-Carrier Reliability Study of Integrated High-Voltage MOSFET Transistors." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/16242266300247122086.

Pełny tekst źródła

Streszczenie:

博士 國立成功大學 電機工程學系碩博士班 95 In this dissertation, the integrated high-voltage MOSFET with three different kinds of application, structure and operation voltage are studied and analyzed on hot-carrier reliability and process conditions correlations. Comparing the hot-carrier reliability of 0.5um 40V N-type drain extended MOSFET (DEMOS) transistors to the conventional low-voltage CMOS transistors; there are there kinds of obviously phenomena – Kick effect accelerated the device degradation, the degradation is proportional to the gate bias and degradation recovery. The hot-carrier reliability behavior of this DEMOS transistor is thus very different from the conventional CMOS transistors. According to the experimental results and two-dimensional process and electric simulation analysis, we identify that under a fixed drain voltage, devices stressed at a higher Vgs results in a greater maximum transconductance (Gmmax) and on-resistance (Ron,sp) degradation. Under higher Vgs, the increase in channel hot-carrier injection is responsible for the greater Gmmax degradation. On the other hand, Kirk effect induced increase in drain avalanche hot carriers near the drain as well as higher electric field in the channel is responsible for the greater Ron degradation. Second, AC lifetime is much longer than DC lifetime because of the recovery in degradation. An anomalous hot-carrier degradation phenomenon was observed in 0.5mm 12V N-type drain extended MOS transistors (N-DEMOS) with various n-type drain drift (NDD) implant dosage. Under the same stress condition, the device with higher NDD dosage produces higher substrate current, slightly higher transconductance degradation (Gmmax), but lower on-resistance (Ron,sp) degradation. Two degradation mechanisms are identified from the analysis of electrical data and two-dimensional device simulations. The first mechanism is hot electron injection in accumulation region near the junction of channel and accumulation region. The second mechanism is hot hole injection in the accumulation region near the spacer. This injection of hot holes creates positive charge trapping in the gate oxide, resulting in negative mirror charges in accumulation region that reduces Ron,sp. The second mechanism is identified to account for the anomalous lower Ron degradation. For high power management integrated circuit (PMIC) product, we develop a 0.35 um 12V N-type lateral double diffuse MOSFET (LDMOS) transistor, and study hot-carrier reliability accordingly. The maximum bulk current (Ib) occurs at different gate bias on various NDD dosages under the Poly gate accumulation region. Under higher NDD dosage, the first bulk current peak is higher, but the second peak is lower. When the gate bias under the first bulk current peak, both the acceptor-type and donor-type interface traps (Nit) are generated simultaneously by the hot hole injection at gate accumulation region and hot electron injection at channel region, respectively. Acceptor-type Nit induced positive charges and results in higher Ron, however, the stress in higher NDD device generated positive charge oxide traps that induced negative charges and results in lower Ron. When device is stressed under the gate bias at second bulk current peak, the additional channel high electric field damage results in serious Gmmax degradation and thus larger Ron degradation. Because of the special design of power management IC, the current surge and voltage spike occur on the drain of LDMOS transistors forced the unclamped device into the avalanche break down, when inductive load switching, and induced device degradation. With fixed current pulse stress, the break down voltage (BVdss), Ron,sp and threshold voltage (Vth) become higher and trend to saturate after several stress times. Break down induced hot holes injections generate a lot of acceptor-type Nit under Poly edge will dynamically change the micro electric field and increase the break down voltage. Acceptor-type Nit attracts electrons and increases the drain series resistance and results in Ron degradation. At last, we deliver an excellent high-voltage 035um 12V Bipolar, CMOS, DMOS (BCD) technology with 21V BVdss and 7 mW-mm2 Ron high performance N-type LDMOS, which demonstrates our technology capability and enable the fabless companies to design the smaller, higher efficiency and more competitive PMIC products.

Style APA, Harvard, Vancouver, ISO itp.

50

Yeh, Chang Hua, and 葉昌樺. "Investigation of Hot Carrier Reliability Issues in STI and Strained-Silicon MOSFET's." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/52610615356862911344.

Pełny tekst źródła

Streszczenie:

碩士 長庚大學 電子工程研究所 92 This thesis addresses the issues related to hot carrier reliabilities in CMOS devices. At first, results on the width dependent hot-carrier (HC) degradation for shallow-trench-isolated (STI) CMOS devices are presented. This is a very crucial issue for the present and future CMOS ULSI using STI technologies. Both thick gate oxide and thin gate oxide exhibit different effects for STI CMOS devices. And then, the analysis of interface reliability in the most advanced strained-silicon devices will be studied. It is important to evaluate the electric property of the new structure device. For the study of STI induced reliability, we present new results on the width dependent hot-carrier (HC) reliabilities for shallow-trench-isolated (STI) p-MOSFET’s in a multiple oxide CMOS technology. For the first time, different phenomena in p-MOSFET’s for a multiple oxide process have been observed. Extensive studies have been made for ALD grown and plasma treated oxide p-MOSFET’s. Experimental data shows that the drain current degradation is enhanced for a reducing gate width. For thick gate oxide (above 30Å), the ID degradation is due to the channel length shortening, and electron trap is dominant for the device degradation. While for ultra-thin gate oxide (below 20Å), the ID degradation is due to width narrowing, and hole trap is dominant, in which both electron and hole trap induced VT are significant. The degradation in thick-oxide p-MOSFET’s causes an increase of off-state leakage current and an increase of VT for that in thin-oxide with reduced width. The final part of the thesis is focused on the reliability characterization of most advanced strained-silicon MOSFET's. In order to investigate the interface property of strained-silicon MOSFET's, an advanced charge-pumping measurement is performed. From the experimental data, we found a two-level maximum charge-pumping current for the first time. It reveals that two layers of interface, including gate oxide/silicon and silicon/silicon germanium, are detected. Finally we apply hot carrier stress to evaluate the electrical reliability of this new generation devices.

Style APA, Harvard, Vancouver, ISO itp.

Rozprawy doktorskie na temat „CARRIER RELIABILITY”

Utwórz poprawne odniesienie w stylach APA, MLA, Chicago, Harvard i wielu innych