Zaloguj się

Gotowe bibliografie tematyczne / CMOS / Artykuły w czasopismach

Kliknij ten link, aby zobaczyć inne rodzaje publikacji na ten temat: CMOS.

Artykuły w czasopismach na temat „CMOS”

Autor: Grafiati

Data publikacji: 4 czerwca 2021

Data aktualizacji: 25 lipca 2025

Utwórz poprawne odniesienie w stylach APA, MLA, Chicago, Harvard i wielu innych

Wybierz rodzaj źródła:

Sprawdź 50 najlepszych artykułów w czasopismach naukowych na temat „CMOS”.

Przycisk „Dodaj do bibliografii” jest dostępny obok każdej pracy w bibliografii. Użyj go – a my automatycznie utworzymy odniesienie bibliograficzne do wybranej pracy w stylu cytowania, którego potrzebujesz: APA, MLA, Harvard, Chicago, Vancouver itp.

Możesz również pobrać pełny tekst publikacji naukowej w formacie „.pdf” i przeczytać adnotację do pracy online, jeśli odpowiednie parametry są dostępne w metadanych.

Przeglądaj artykuły w czasopismach z różnych dziedzin i twórz odpowiednie bibliografie.

1

Lohmann, Anne Møller, Anne Poder Petersen, Johannes Martin Schmid, Hans Jürgen Hoffmann, and Jeanette Finderup. "Understanding the combined symptom medication score in the light of contexts and mechanisms." PLOS One 20, no. 6 (2025): e0326143. https://doi.org/10.1371/journal.pone.0326143.

Pełny tekst źródła

Streszczenie:

Background In a clinical trial of allergen‐specific immunotherapy for allergic rhinoconjunctivitis, the Combined Symptom Medication Score (CSMS) was utilized as the primary endpoint. This was aligned with the European Academy of Allergy and Clinical Immunology recommendation. However, participants wanted to elaborate on how their behaviour affected their score, so voluntary free text boxes were added to the CSMS questionnaire. This study aimed to evaluate the patient-reported outcomes registered in the free text boxes to identify and understand contexts and mechanisms that may affect the CSMS.

Style APA, Harvard, Vancouver, ISO itp.

2

Marfungah, Siti, and Suartini Suartini. "The Position Of Commitment-Making Officials As Legal Subjects In Disputes Over Construction Service Agreements In Indonesian Courts." Eduvest - Journal of Universal Studies 4, no. 11 (2024): 10015–25. http://dx.doi.org/10.59188/eduvest.v4i11.1603.

Pełny tekst źródła

Streszczenie:

The role of the Commitment Making Officer (CMO) is crucial because they are responsible for the procurement process and contract implementation. However, disputes often occur regarding the CMO's legal position in the agreement. This study aims to examine in depth how courts in Indonesia view and regulate the legal position of CMO as a legal subject in the settlement of construction service agreement disputes. This study uses normative legal research methods with legislative and comparative approaches. The results showed that courts in Indonesia tend to position CMO as a legal subject that has

Style APA, Harvard, Vancouver, ISO itp.

3

Deleonibus, S. "Alternative CMOS or alternative to CMOS?" Microelectronics Reliability 41, no. 1 (2001): 3–12. http://dx.doi.org/10.1016/s0026-2714(00)00196-7.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

4

Chang, Woong-Joo, Chae-Jun Lee, Joon-Hyung Kim, and Tae-Hwan Jang. "Cryogenic CMOS LNA in 28nm CMOS Process for Quantum Computing." Journal of the Institute of Electronics and Information Engineers 61, no. 10 (2024): 25–31. https://doi.org/10.5573/ieie.2024.61.10.25.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

5

Kawahito, Shoji. "CMOS Image Sensors." IEEJ Transactions on Sensors and Micromachines 134, no. 7 (2014): 199–205. http://dx.doi.org/10.1541/ieejsmas.134.199.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

6

Lau, K. T., W. Y. Wang, and K. W. Ng. "Adiabatic-CMOS/CMOS-adiabatic logic interface circuit." International Journal of Electronics 87, no. 1 (2000): 27–32. http://dx.doi.org/10.1080/002072100132417.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

7

Banerjee, Sanjay K., Leonard Franklin Register, Emanuel Tutuc, et al. "Graphene for CMOS and Beyond CMOS Applications." Proceedings of the IEEE 98, no. 12 (2010): 2032–46. http://dx.doi.org/10.1109/jproc.2010.2064151.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

8

GABARA, THAD. "PULSED LOW POWER CMOS." International Journal of High Speed Electronics and Systems 05, no. 02 (1994): 159–77. http://dx.doi.org/10.1142/s0129156494000097.

Pełny tekst źródła

Streszczenie:

A simple CMOS circuit technique called PPS (Pulsed Power Supply) CMOS is used to reduce the power dissipation of Conventional 0.9 μm CMOS by 10X when operated at 32 MHz. Combinational and sequential logic can utilize this technique including the I/O (input/output) buffers. Thus, PPS CMOS offers a full chip solution for low power dissipation CMOS. In addition, several advantages occur in this new circuit technique: (1) low power signal propagation through several gates in series can occur during each evaluation cycle; (2) crowbar current does not occur; (3) additional placed devices, i.e. bipol

Style APA, Harvard, Vancouver, ISO itp.

9

Ko, Ji Wang, and Woo Young Choi. "Monolithic-3D (M3D) Complementary Metal-Oxide-Semiconductor-Nanoelectromechanical (CMOS-NEM) Hybrid Reconfigurable Logic (RL) Circuits." Journal of Nanoscience and Nanotechnology 20, no. 7 (2020): 4176–81. http://dx.doi.org/10.1166/jnn.2020.17790.

Pełny tekst źródła

Streszczenie:

Monolithic-three-dimensional (M3D) CMOS-nanoelectromechanical (CMOS-NEM) hybrid reconfigurable logic (RL) circuits are compared and analyzed with CMOS-only RL ones in the 130-nm CMOS technology node. M3D CMOS-NEM hybrid RL circuits are superior to CMOS-only ones in terms of power consumption and signal transfer speed thanks to the NEM memory switches. As well as in the routing part, it has many advantages in the logic part following the switch.

Style APA, Harvard, Vancouver, ISO itp.

10

Agrawal, Gaurav R., and Leena A. Yelmule. "Linear CMOS LNA." International Journal of Trend in Scientific Research and Development Volume-3, Issue-1 (2018): 829–35. http://dx.doi.org/10.31142/ijtsrd19087.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

11

Karthikeyan, A., and P. S. Mallick. "Body-Biased Subthreshold Bootstrapped CMOS Driver." Journal of Circuits, Systems and Computers 28, no. 03 (2019): 1950051. http://dx.doi.org/10.1142/s0218126619500518.

Pełny tekst źródła

Streszczenie:

This paper proposes a body-biased bootstrapped CMOS driver for subthreshold applications. The proposed driver has been implemented with the same number of transistors as conventional bootstrapped CMOS driver. The performance of the subthreshold bootstrapped CMOS driver has been compared with the conventional bootstrapped CMOS driver. Our results show that the proposed body-biased subthreshold bootstrapped CMOS driver has 37% reduction in delay and 39% reduction in power dissipation compared to conventional bootstrapped CMOS driver. The proposed driver is more suitable to drive large loads comp

Style APA, Harvard, Vancouver, ISO itp.

12

Wong, H. S. P., D. J. Frank, P. M. Solomon, C. H. J. Wann, and J. J. Welser. "Nanoscale CMOS." Proceedings of the IEEE 87, no. 4 (1999): 537–70. http://dx.doi.org/10.1109/5.752515.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

13

Malhi, S. D. S., K. E. Bean, R. Sunderesan, and L. R. Hite. "Overlaid CMOS." Electronics Letters 22, no. 11 (1986): 598–99. http://dx.doi.org/10.1049/el:19860406.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

14

Brown, G. A., P. M. Zeitzoff, G. Bersuker, and H. R. Huff. "Scaling CMOS." Materials Today 7, no. 1 (2004): 20–25. http://dx.doi.org/10.1016/s1369-7021(04)00051-3.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

15

Lee, Charles M., and Ellen W. Szeto. "Zipper CMOS." IEEE Circuits and Devices Magazine 2, no. 3 (1986): 10–17. http://dx.doi.org/10.1109/mcd.1986.6311821.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

16

Sadek, A., and K. Ismail. "CMOS possibilities." Solid-State Electronics 38, no. 9 (1995): 1731–34. http://dx.doi.org/10.1016/0038-1101(95)00037-t.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

17

Ghoshal, U., S. V. Kishore, A. R. Feldman, Luong Huynh, and T. Van Duzer. "CMOS amplifier designs for Josephson-CMOS interface circuits." IEEE Transactions on Appiled Superconductivity 5, no. 2 (1995): 2640–43. http://dx.doi.org/10.1109/77.403132.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

18

Xu, Haoran, Jianghua Ding, and Jian Dang. "Design and Characteristics of CMOS Inverter based on Multisim and Cadence." Journal of Physics: Conference Series 2108, no. 1 (2021): 012034. http://dx.doi.org/10.1088/1742-6596/2108/1/012034.

Pełny tekst źródła

Streszczenie:

Abstract Known as complementary symmetrical metal oxide semiconductor (cos-mos), complementary metal oxide semiconductor is a metal oxide semiconductor field effect transistor (MOSFET) manufacturing process, which uses complementary and symmetrical pairs of p-type and n-type MOSFETs to realize logic functions. CMOS technology is used to build integrated circuit (IC) chips, including microprocessors, microcontrollers, memory chips (including CMOS BIOS) and other digital logic circuits. CMOS technology is also used in analog circuits, such as image sensors (CMOS sensors), data converters, RF cir

Style APA, Harvard, Vancouver, ISO itp.

19

Yu, Le, Yaozu Guo, Haoyu Zhu, Mingcheng Luo, Ping Han, and Xiaoli Ji. "Low-Cost Microbolometer Type Infrared Detectors." Micromachines 11, no. 9 (2020): 800. http://dx.doi.org/10.3390/mi11090800.

Pełny tekst źródła

Streszczenie:

The complementary metal oxide semiconductor (CMOS) microbolometer technology provides a low-cost approach for the long-wave infrared (LWIR) imaging applications. The fabrication of the CMOS-compatible microbolometer infrared focal plane arrays (IRFPAs) is based on the combination of the standard CMOS process and simple post-CMOS micro-electro-mechanical system (MEMS) process. With the technological development, the performance of the commercialized CMOS-compatible microbolometers shows only a small gap with that of the mainstream ones. This paper reviews the basics and recent advances of the C

Style APA, Harvard, Vancouver, ISO itp.

20

O, K. K., S. SANKARAN, C. CAO, et al. "MILLIMETER WAVE TO TERAHERTZ IN CMOS." International Journal of High Speed Electronics and Systems 19, no. 01 (2009): 55–67. http://dx.doi.org/10.1142/s0129156409006084.

Pełny tekst źródła

Streszczenie:

The feasibility of CMOS circuits operating at frequencies in the upper millimeter wave and low sub-millimeter frequency regions has been demonstrated. A 140-GHz fundamental mode VCO in 90-nm CMOS, a 410-GHz push-push VCO in 45-nm CMOS, and a 180-GHz detector circuit in 130-nm CMOS have been demonstrated. With the continued scaling of MOS transistors, 1-THz CMOS circuits will be possible. Though these results are significant, output power of signal generators must be increased and acceptable noise performance of detectors must be achieved in order to demonstrate the applicability of CMOS for im

Style APA, Harvard, Vancouver, ISO itp.

21

Shi, Chenhao. "Applications of CMOS image sensors: Applications and innovations." Applied and Computational Engineering 11, no. 1 (2023): 95–103. http://dx.doi.org/10.54254/2755-2721/11/20230216.

Pełny tekst źródła

Streszczenie:

As semiconductor production processes continue to advance, CMOS image sensors are becoming increasingly popular and are gradually replacing traditional CCD sensors as the mainstream option in the market. Because CMOS image sensors adopt the standard CMOS semiconductor production process, which provides advantages such as low static power consumption, large noise tolerance, strong anti-interference ability, and fast working speed. This article is going to provide an overview of CMOS image sensors and examine their various applications. To achieve this, this article will provide some background

Style APA, Harvard, Vancouver, ISO itp.

22

Roy, Avisek, Mehdi Azadmehr, Bao Q. Ta, Philipp Häfliger, and Knut E. Aasmundtveit. "Design and Fabrication of CMOS Microstructures to Locally Synthesize Carbon Nanotubes for Gas Sensing." Sensors 19, no. 19 (2019): 4340. http://dx.doi.org/10.3390/s19194340.

Pełny tekst źródła

Streszczenie:

Carbon nanotubes (CNTs) can be grown locally on custom-designed CMOS microstructures to use them as a sensing material for manufacturing low-cost gas sensors, where CMOS readout circuits are directly integrated. Such a local CNT synthesis process using thermal chemical vapor deposition (CVD) requires temperatures near 900 °C, which is destructive for CMOS circuits. Therefore, it is necessary to ensure a high thermal gradient around the CNT growth structures to maintain CMOS-compatible temperature (below 300 °C) on the bulk part of the chip, where readout circuits are placed. This paper present

Style APA, Harvard, Vancouver, ISO itp.

23

Nebhen, Jamel, Julien Dubois, Sofiene Mansouri, and Dominique Ginhac. "Low-noise and low power CMOS photoreceptor using split-length MOSFET." Journal of Electrical Engineering 70, no. 6 (2019): 480–85. http://dx.doi.org/10.2478/jee-2019-0081.

Pełny tekst źródła

Streszczenie:

Abstract This paper presents the design of a low-power and low-noise CMOS photo-transduction circuit. We propose to use the new technique of composite transistors for noise reduction of photoreceptor in the subthreshold by exploiting the small size effects of CMOS transistors. Several power and noise optimizations, design requirements, and performance limitations relating to the CMOS photoreceptor are presented. This new structure with composite transistors ensures low noise and low power consumption. The CMOS photoreceptor, implemented in a 130 nm standard CMOS technology with a 1.2 V supply

Style APA, Harvard, Vancouver, ISO itp.

24

Huang, Peihao. "Design and optimization of CMOS layout structure for improved semiconductor device performance." Journal of Physics: Conference Series 2649, no. 1 (2023): 012040. http://dx.doi.org/10.1088/1742-6596/2649/1/012040.

Pełny tekst źródła

Streszczenie:

Abstract CMOS layout structure plays a very important role in the field of semiconductor. Since the invention of CMOS technology in the 1970s, engineers have developed many other CMOS layout technologies based on it. This paper will also focus on the CMOS transistor layout structure, focusing on the analysis of three more important structures, demonstrating their impact on the performance of semiconductor devices. Before that, this paper will first introduce the basic theory of CMOS, such as the drift and diffusion of charge carriers in PN junctions, and the working principle of PMOS and NMOS,

Style APA, Harvard, Vancouver, ISO itp.

25

Haque, M. Samiul, S. Zeeshan Ali, P. K. Guha, et al. "Growth of Carbon Nanotubes on Fully Processed Silicon-On-Insulator CMOS Substrates." Journal of Nanoscience and Nanotechnology 8, no. 11 (2008): 5667–72. http://dx.doi.org/10.1166/jnn.2008.207.

Pełny tekst źródła

Streszczenie:

This paper describes the growth of Carbon Nanotubes (CNTs) both aligned and non-aligned on fully processed CMOS substrates containing high temperature tungsten metallization. While the growth method has been demonstrated in fabricating CNT gas sensitive layers for high temperatures SOI CMOS sensors, it can be employed in a variety of applications which require the use of CNTs or other nanomaterials with CMOS electronics. In our experiments we have grown CNTs both on SOI CMOS substrates and SOI CMOS microhotplates (suspended on membranes formed by post-CMOS deep RIE etching). The fully processe

Style APA, Harvard, Vancouver, ISO itp.

26

Wang, Xinyu, Zhongjie Xu, Hairong Zhong, Xiang’ai Cheng, Zhongyang Xing, and Jiangbin Zhang. "Fresnel Diffraction Model for Laser Dazzling Spots of Complementary Metal Oxide Semiconductor Cameras." Sensors 24, no. 17 (2024): 5781. http://dx.doi.org/10.3390/s24175781.

Pełny tekst źródła

Streszczenie:

Laser dazzling on complementary metal oxide semiconductor (CMOS) image sensors is an effective method in optoelectronic countermeasures. However, previous research mainly focused on the laser dazzling under far fields, with limited studies on situations that the far-field conditions were not satisfied. In this paper, we established a Fresnel diffraction model of laser dazzling on a CMOS by combining experiments and simulations. We calculated that the laser power density and the area of saturated pixels on the detector exhibit a linear relationship with a slope of 0.64 in a log-log plot. In the

Style APA, Harvard, Vancouver, ISO itp.

27

Zhang, C., G. Casse, M. Franks, et al. "High-performance HV-CMOS sensors for future particle physics experiments — an overview." Journal of Instrumentation 17, no. 09 (2022): C09025. http://dx.doi.org/10.1088/1748-0221/17/09/c09025.

Pełny tekst źródła

Streszczenie:

Abstract HV-CMOS (High Voltage-CMOS) sensors are emerging as a prime candidate for future tracking detectors that have extreme requirements on material budget, pixel granularity, time resolution and radiation tolerance. These sensors have the advantages of full monolithic structure, low manufacture cost, fast charge collection and high radiation tolerance. Confirmed and potential tracking applications in physics experiments include the Mu3e experiment, proton EDM searches, future upgrades of LHC (Large Hadron Collider) and CEPC (Circular Electron Positron Collider). The HV-CMOS group at Liverp

Style APA, Harvard, Vancouver, ISO itp.

28

Moez, K. K., and M. I. Elmasry. "Area-efficient CMOS distributed amplifier using compact CMOS interconnects." Electronics Letters 42, no. 17 (2006): 970. http://dx.doi.org/10.1049/el:20061628.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

29

Lee, Byoung Hun. "Exploratory NEMS-CMOS Hybrid Devices for Post CMOS Era." ECS Transactions 18, no. 1 (2019): 857–62. http://dx.doi.org/10.1149/1.3096546.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

30

Kobayashi, Ryosuke, and Masayuki Yamamoto. "Comparison of Si CMOS and SiC CMOS Operational Amplifiers." Solid State Phenomena 360 (August 23, 2024): 157–61. http://dx.doi.org/10.4028/p-ibxs8l.

Pełny tekst źródła

Streszczenie:

In this study, we numerically compare the characteristics of Si and SiC CMOS operational amplifiers (OpAmp) using LTspice. According to prior researches, we set the device parameters for Si and SiC MOSFETs. The OpAmp consists of three stages: the input stage, the gain stage, and the output stage. We established three criteria for the OpAmp's operation: (1) a unity gain frequency of 1MHz, (2) an open-loop gain of at least 75dB, and (3) a phase margin of more than 60° when a load capacitance is 300pF. To achieve a unity gain frequency of 1MHz, we adjusted the values of the resistor and capacitor

Style APA, Harvard, Vancouver, ISO itp.

31

Rim, K., R. Anderson, D. Boyd, et al. "Strained Si CMOS (SS CMOS) technology: opportunities and challenges." Solid-State Electronics 47, no. 7 (2003): 1133–39. http://dx.doi.org/10.1016/s0038-1101(03)00041-8.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

32

Toriumi, Akira, Choong Hyun Lee, Tomonori Nishimura, et al. "(Invited) Feasibility of Ge CMOS for Beyond Si-CMOS." ECS Transactions 33, no. 6 (2019): 33–46. http://dx.doi.org/10.1149/1.3487532.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

33

Li, Gongchen, Fangji Zhao, Zicheng Wang, and Zhe Chen. "The development and application of CMOS image sensor." Applied and Computational Engineering 7, no. 1 (2023): 767–77. http://dx.doi.org/10.54254/2755-2721/7/20230460.

Pełny tekst źródła

Streszczenie:

This paper focuses on the development of Complementary metal-oxide semiconductor (CMOS) image sensor and its applications in aerospace, medical and automotive fields. Firstly, the representative events in history and the contributions of some companies to CMOS image sensor are described. Subsequently, some characteristics of CMOS image sensor are analyzed in the image field involved. In order to evaluate the performance of CMOS image sensor, single even effect and electronic endoscope structures are analyzed and active and passive range finder experiments are carried out. The results show that

Style APA, Harvard, Vancouver, ISO itp.

34

Gao, Changjian, and Dan Hammerstrom. "Cortical Models Onto CMOL and CMOS— Architectures and Performance/Price." IEEE Transactions on Circuits and Systems I: Regular Papers 54, no. 11 (2007): 2502–15. http://dx.doi.org/10.1109/tcsi.2007.907830.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

35

Kumar, Umesh. "Measurements and Analytical Computer-Based Study of CMOS Inverters and Schmitt Triggers." Active and Passive Electronic Components 19, no. 1 (1996): 41–54. http://dx.doi.org/10.1155/1996/52421.

Pełny tekst źródła

Streszczenie:

Modified CMOS inverters with three and four transistors have been made. Two varieties of CMOS Schmitt Triggers have been considered. CMOS Schmitt Trigger with wide hysteresis has been obtained. Complete detailed theoretical, experimental and computer based results are derived and exhibited.

Style APA, Harvard, Vancouver, ISO itp.

36

Chen, Jiahao. "Integrated circuit design based on CMOS technology principle and its application in GPU." Theoretical and Natural Science 12, no. 1 (2023): 141–46. http://dx.doi.org/10.54254/2753-8818/12/20230454.

Pełny tekst źródła

Streszczenie:

In today's society, the application of integrated circuit technology can be seen everywhere, especially in the past two decades. This paper mainly studies the principle and design of CMOS devices in IC technology and discusses the research and analysis of the acceleration algorithm of IC design. This paper adopts the research method of literature review and analysis to summarize the existing research results. This paper first introduces the development background of integrated circuit technology and the importance of CMOS technology. Subsequently, the concept and interconnection principle of C

Style APA, Harvard, Vancouver, ISO itp.

37

Kogut, Igor T., Victor I. Holota, Anatoly Druzhinin, and V. V. Dovhij. "The Device-Technological Simulation of Local 3D SOI-Structures." Journal of Nano Research 39 (February 2016): 228–34. http://dx.doi.org/10.4028/www.scientific.net/jnanor.39.228.

Pełny tekst źródła

Streszczenie:

This paper presents the device-technological simulation of local 3D SOI structures. These structures are created by use microcavities under surface of silicon wafer. Is shown that proposed microcavities could be use as a constructive material for CMOS transistor array on the bulk silicon and 3D SOI-CMOS transistor array, as well as the sensitive elements and their combinations. Such structures allow creation and monolithic integration the CMOS, SOI-CMOS circuits and sensitive elements for IC and SoC.

Style APA, Harvard, Vancouver, ISO itp.

38

SOLIMAN, AHMED M., and AHMED H. MADIAN. "MOS-C TOW-THOMAS FILTER USING VOLTAGE OP AMP, CURRENT FEEDBACK OP AMP AND OPERATIONAL TRANSRESISTANCE AMPLIFIER." Journal of Circuits, Systems and Computers 18, no. 01 (2009): 151–79. http://dx.doi.org/10.1142/s0218126609004995.

Pełny tekst źródła

Streszczenie:

Several MOS-C realizations of the Tow-Thomas circuit using the commercially available voltage operational amplifier and the current feedback operational amplifier are reviewed in this paper. Additional MOS-C Tow-Thomas realizations using the operational transresistance amplifier and the differential current voltage conveyor are also included. MOS-C realizations of the Tow-Thomas circuit using CMOS operational amplifier, CMOS current feedback operational amplifier and CMOS operational transresistance amplifier are also given. Spice simulation results using 0.18 CMOS technology model from MOSIS

Style APA, Harvard, Vancouver, ISO itp.

39

Machowski, Witold, Stanisław Kuta, Jacek Jasielski, and Wojciech Kołodziejski. "Fast Low Voltage Analog Four-Quadrant Multipliers Based on CMOS Inverters." International Journal of Electronics and Telecommunications 56, no. 4 (2010): 381–86. http://dx.doi.org/10.2478/v10177-010-0050-z.

Pełny tekst źródła

Streszczenie:

Fast Low Voltage Analog Four-Quadrant Multipliers Based on CMOS InvertersThe paper presents quarter-square analog four-quadrant multipliers, based on proprietary architecture using four CMOS inverters. The most important upgrade on already published own circuit implementation is the use of the same inverter "core" of the circuit with completely redesigned auxiliary and steering blocks. Two variants of new driving peripherals are considered: one with differential pair, the second with CMOS inverters. The proposed circuit solutions are suitable for RF applications in communication systems due to

Style APA, Harvard, Vancouver, ISO itp.

40

Mohamed, Khaled Salah. "Work around Moore’s Law: Current and next Generation Technologies." Applied Mechanics and Materials 110-116 (October 2011): 3278–83. http://dx.doi.org/10.4028/www.scientific.net/amm.110-116.3278.

Pełny tekst źródła

Streszczenie:

Interconnect dimensions and CMOS transistor feature size approach their physical limits, therefore scaling will no longer play an important role in performance improvement. So, instead of trying to improve the performance of traditional CMOS circuits, integration of multiple technologies and different components in a heterogeneous system that is high performance will be introduced “moore than more” and CMOS replacement”beyond CMOS” will be explored. This paper focuses on Technology level trends where it presents “More Moore”:New Architectures (SOI, FinFET, Twin-Well),”More Moore” :New Material

Style APA, Harvard, Vancouver, ISO itp.

41

Rasheed, Israa Mohammed, and Hassan Jasim Motlak. "Performance parameters optimization of CMOS analog signal processing circuits based on smart algorithms." Bulletin of Electrical Engineering and Informatics 12, no. 1 (2023): 149–57. http://dx.doi.org/10.11591/eei.v12i1.4128.

Pełny tekst źródła

Streszczenie:

Designing ideal analogue circuits has become difficult due to extremely large-scale integration. The complementary metal oxide semiconductor (CMOS) analog integrated circuits (IC) could use an evolutionary method to figure out the size of each device. The CMOS operational transconductance amplifier (CMOS OTA) and the CMOS current conveyor second generation (CMOS CCII) are designed using advanced nanometer transistor technology (180 nm). Both CMOS OTA and CMOS CCII have high performance, such as a wide frequency, voltage gain, slew rate, and phase margin, to include very wide applications in si

Style APA, Harvard, Vancouver, ISO itp.

42

Siswoko, Siswoko, Hariyadi Singgih, and A. Komarudin. "DISAIN PERANCANGAN ALAT UJI IC TTL / CMOS UNTUK PENUNJANG LABORATORIUM ELEKTRONIKA DIGITAL." JURNAL ELTEK 17, no. 2 (2019): 120. http://dx.doi.org/10.33795/eltek.v17i2.186.

Pełny tekst źródła

Streszczenie:

Bentuk IC TTL dan CMOS yang kecil dan memiliki jumlah pin bervariasi membuat orang kesulitan untuk melakukan pengujian kondisi IC TTL dan CMOS secara cepat. Beberapa cara pengujian IC TTL dan CMOS secara manual yakni menggunakan protoboard. Akan tetapi hal tersebut membutuhkan waktu yang cukup lama. Dari permasalahan tersebut, dibutuhkan adanya alat uji yang dapat mempermudah pengguna untuk mengetahui kondisi IC TTL dan CMOS sebelum digunakan. Alat uji IC digital ini dibuat untuk menguji apakah IC yang digunakan dalam keadaan baik atau rusak. Karena jenis IC TTL dan CMOS yang akan diujikan leb

Style APA, Harvard, Vancouver, ISO itp.

43

Xiong, Yuanyuan, Erming Rui, Yu Tian, Qiang Jiao, Fuyu Han, and Pei Liu. "Discussion of Mechanical Shock Test Stress for Ultra-large-scale CMOS Image Sensors." Journal of Physics: Conference Series 2694, no. 1 (2024): 012028. http://dx.doi.org/10.1088/1742-6596/2694/1/012028.

Pełny tekst źródła

Streszczenie:

Abstract The ultra-large-scale CMOS image sensors are significantly different from the traditional CMOS image sensors in terms of pixel size, chip size and structure. CMOS image sensors generally come with an optical window structure that is sealed to the ceramic housing by means of adhesive. The optical window material is generally sapphire, and the larger the image element size, the larger the required glass optical window area. Ultra-large size CMOS image sensors in the package before the general optical window thickness, parallelism, light window average transmittance assessment. The objec

Style APA, Harvard, Vancouver, ISO itp.

44

Kang, Min-Jae, Ho-Chan Kim, Wang-Cheol Song, and Sang-Joon Lee. "CMOS neuron activation function." Journal of Korean Institute of Intelligent Systems 16, no. 5 (2006): 627–34. http://dx.doi.org/10.5391/jkiis.2006.16.5.627.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

45

MOONEY, P. M. "MATERIALS FOR STRAINED SILICON DEVICES." International Journal of High Speed Electronics and Systems 12, no. 02 (2002): 305–14. http://dx.doi.org/10.1142/s0129156402001265.

Pełny tekst źródła

Streszczenie:

Strained Si devices exhibit enhanced carrier mobility compared to that of standard Si CMOS devices of the same dimensions. Recent strained Si CMOS device results are reviewed. Materials issues related to the strained Si/relaxed SiGe heterostructures required for a strained Si CMOS technology are discussed.

Style APA, Harvard, Vancouver, ISO itp.

46

SOLIMAN, AHMED M., and AHMED H. MADIAN. "MOS-C KHN FILTER USING VOLTAGE OP AMP, CFOA, OTRA AND DCVC." Journal of Circuits, Systems and Computers 18, no. 04 (2009): 733–69. http://dx.doi.org/10.1142/s021812660900523x.

Pełny tekst źródła

Streszczenie:

MOS-C realizations of the Kerwin–Huelsman–Newcomb (KHN) circuit using the commercially available Voltage Operational Amplifier (VOA) and the Current Feedback Operational Amplifier (CFOA) are reviewed in this paper. Additional MOS-C KHN realizations using the Operational Transresistance Amplifier (OTRA) and the Differential Current Voltage Conveyor (DCVC) are also included. MOS-C realizations of the KHN circuit using CMOS operational amplifier, CMOS current feedback operational amplifier and CMOS operational transresistance amplifier are also given. Spice simulation results using 0.18 CMOS tech

Style APA, Harvard, Vancouver, ISO itp.

47

JOUVET, N., M. A. BOUNOUAR, S. ECOFFEY, et al. "RECENT DEVELOPMENTS ON 3D INTEGRATION OF METALLIC SET ONTO CMOS PROCESS FOR MEMORY APPLICATION." International Journal of Nanoscience 11, no. 04 (2012): 1240024. http://dx.doi.org/10.1142/s0219581x12400248.

Pełny tekst źródła

Streszczenie:

This work presents a nanodamascene process for a CMOS back-end-of-line fabrication of metallic single electron transistor(SET), together with the use of simulation tools for the development of a SET SRAM memory cell. We show room temperature electrical characterizations of SETs fabricated on CMOS with relaxed dimensions, and simulations of a SET SRAM memory cell. Using their physical characteristics achievable through the use of atomic layer deposition, it will be demonstrated that it has the potential to operate at temperature up to 398 K, and that power consumption is less than that of equiv

Style APA, Harvard, Vancouver, ISO itp.

48

Birla, Shilpi, Sudip Mahanti, and Neha Singh. "Leakage reduction technique for nano-scaled devices." Circuit World 47, no. 1 (2020): 97–104. http://dx.doi.org/10.1108/cw-12-2019-0195.

Pełny tekst źródła

Streszczenie:

Purpose The purpose of this paper is to propose a leakage reduction technique which will works for complementary metal oxide semiconductor (CMOS) and fin field effect transistor (FinFET). Power consumption will always remain one of the major concerns for the integrated circuit (IC) designers. Presently, leakage power dominates the total power consumption, which is a severe issue. It is undoubtedly clear that the scaling of CMOS revolutionizes the IC industry. Still, on the contrary, scaling of the size of the transistor has raised leakage power as one of the significant threats to the IC indus

Style APA, Harvard, Vancouver, ISO itp.

49

M. Surekha, V. HariKrishna, B. MadhuSudhan Reddy, G.Tejaswini, I.Rajasekhar, and K.Divya. "Efficient Approaches to Design Full Adder Using Domino Logic Technique." international journal of engineering technology and management sciences 7, no. 2 (2023): 283–88. http://dx.doi.org/10.46647/ijetms.2023.v07i02.033.

Pełny tekst źródła

Streszczenie:

Static CMOS and Domino CMOS Circuits are significantly used in high performance VLSI system. Designing a circuit with low power, high speed performance is one of the challenging aspects. In modern VLSI systems area efficient devices are utmost popular because most of the devices are becoming portable. This paper proposes One- bit full adder circuit is designed using CMOS based on mirror logic and Domino CMOS also designed based on same logic with LTSPICE at 180nm technology with 1.8V supply. This method provides better power and delay.

Style APA, Harvard, Vancouver, ISO itp.

50

Vidhyadharan, Abhay Sanjay, and Sanjay Vidhyadharan. "Improved hetero-junction TFET-based Schmitt trigger designs for ultra-low-voltage VLSI applications." World Journal of Engineering 18, no. 5 (2021): 750–59. http://dx.doi.org/10.1108/wje-08-2020-0367.

Pełny tekst źródła

Streszczenie:

Purpose Tunnel field effect transistors (TFETs) have significantly steeper sub-threshold slope (24–30 mv/decade), as compared with the conventional metal–oxide–semiconductor field-effect transistors (MOSFETs), which have a sub-threshold slope of 60 mv/decade at room temperature. The steep sub-threshold slope of TFETs enables a much faster switching, making TFETs a better option than MOSFETs for low-voltage VLSI applications. The purpose of this paper is to present a novel hetero-junction TFET-based Schmitt triggers, which outperform the conventional complementary metal oxide semiconductor (CMO

Style APA, Harvard, Vancouver, ISO itp.

Oferujemy zniżki na wszystkie plany premium dla autorów, których prace zostały uwzględnione w tematycznych zestawieniach literatury. Skontaktuj się z nami, aby uzyskać unikalny kod promocyjny!