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Gotowe bibliografie tematyczne / Complementary Design and construction / Rozprawy doktorskie

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Rozprawy doktorskie na temat „Complementary Design and construction”

Autor: Grafiati

Data publikacji: 4 czerwca 2021

Data aktualizacji: 1 lutego 2022

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1

Bond, Steven Winfred. "Through-silicon circuit optical communications links." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/15390.

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2

Tang, Wei 1976. "High-speed parallel optical receivers." Thesis, McGill University, 2007. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=103298.

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Parallel optical interconnects (POI) have attracted a great deal of attention in the past two decades as the system bandwidth continues to increase. Optical interconnects are known to have more advantages than their electrical counterparts in many aspects such as crosstalk, bandwidth distance product, power consumption, and RC time delay. The parallelization of several optical links is also an effective method to increase the aggregate data rate while keeping the component count manageable and to reduce the unit cost of optics, electronics, and packaging at lower line rate.<br>Parallel optical

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3

Bhavnagarwala, Azeez Jenúddin. "Voltage scaling constraints for static CMOS logic and memory cirucits." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/15401.

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4

Ng, Chik-wai, and 吳植偉. "Design techniques of advanced CMOS building blocks for high-performance power management integrated circuits." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2011. http://hub.hku.hk/bib/B45896926.

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5

Mony, Madeleine. "Reprogrammable optical phase array." Thesis, McGill University, 2007. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=103276.

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The evolving needs of network carriers are changing the design of optical networks. In order to reduce cost, latency, and power consumption, electrical switches are being replaced with optical switching fabrics at the core of the networks. An example of such a network is an Agile All-Photonic Network (AAPN).<br>This thesis presents a novel device that was designed to operate as an optical switch within the context of an AAPN network. The device is a Reprogrammable Optical Phase Array (ROPA), and the design consists of applying multiple electric fields of different magnitudes across an electro-

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6

Deshpande, Sandeep. "A cost quality model for CMOS IC design." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-12042009-020251/.

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7

Mule, Anthony Victor. "Volume grating coupler-based optical interconnect technologies for polylithic gigascale integrat." Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/9447.

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8

Xiao, Haiqiao. "Design of Radio-Frequency Filters and Oscillators in Deep-Submicron CMOS Technology." PDXScholar, 2008. https://pdxscholar.library.pdx.edu/open_access_etds/5233.

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Radio-frequency filters and oscillators are widely used in wireless communication and high-speed digital systems, and they are mostly built on passive integrated inductors, which occupy a relative large silicon area. This research attempted to implement filters and oscillators operating at 1-5 GHz using transistors only, to reduce the circuits’ area. The filters and oscillators are designed using active inductors, based on the gyrator principle; they are fabricated in standard digital CMOS technology to be compatible with logic circuits and further lower the cost. To obtain the highest operati

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9

Blalock, Benjamin Joseph. "A 1-volt CMOS wide dynamic Range operational amplifier." Diss., Georgia Institute of Technology, 1996. http://hdl.handle.net/1853/15441.

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10

Gibson, Jr Allen. "Design and simulation of CMOS active mixers." Master's thesis, University of Central Florida, 2011. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/4765.

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This paper introduces a component of the Radio Frequency transceiver called the mixer. The mixer is a critical component in the RF systems, because of its ability for frequency conversion. This passage focuses on the design analysis and simulation of multiple topologies for the active down-conversion mixer. This mixer is characterized by its important design properties which consist of conversion gain, linearity, noise figure, and port isolation. The topologies that are given in this passage range from the most commonly known mixer design, to implemented design techniques that are used to incr

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11

Song, Indal. "Multi-Gbit/s CMOS Transimpedance Amplifier with Integrated Photodetector for Optical Interconnects." Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/4902.

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Trends toward increased integration and miniaturization of optical system components have created pressure to consolidate widely disparate analog and digital functions onto fewer and fewer chips with a goal of eventually built into a single mixed-signal chip. Yet, because of those performance requirements, the frontend circuit has traditionally used III-V compound semiconductor technologies, but the low-level of integration with other digital ICs limits the sustainability of such end products for short-distance applications. On the other hand, their CMOS counter parts, despite having such adva

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12

Dong, Zhiwei. "Low-power, low-distortion constant transconductance Gm-C filters." Diss., Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/25400.

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13

Kumar, Ajay. "A novel Q tuning technique for high-Q high-frequency IF bandpass filter." Thesis, Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/15904.

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14

Shin, Eung Seo. "Automated Generation of Round-robin Arbitration and Crossbar Switch Logic." Diss., Available online, Georgia Institute of Technology, (2003), 2003. http://etd.gatech.edu/theses/available/etd-11232003-150424/.

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15

Amarnath, Avinash. "A Self-Configurable Architecture on an Irregular Reconfigurable Fabric." PDXScholar, 2011. https://pdxscholar.library.pdx.edu/open_access_etds/634.

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Reconfigurable computing architectures combine the flexibility of software with the performance of custom hardware. Such architectures are of particular interest at the nanoscale level. We argue that a bottom-up self-assembled fabric of nodes will be easier and cheaper to manufacture, however, one has to make compromises with regards to the device regularity, homogeneity, and reliability. The goal of this thesis is to evaluate the performance and cost of a self-configurable computing architecture composed of simple reconfigurable nodes for unstructured and unknown fabrics. We built a software

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16

Chan, Chi Hang. "A study on comparator and offset calibration techniques in high speed Nyquist ADCs." Thesis, University of Macau, 2011. http://umaclib3.umac.mo/record=b2493284.

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17

Hass, Joanna R. "Structural characterization of epitaxial graphene on silicon carbide." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/26654.

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Thesis (Ph.D)--Physics, Georgia Institute of Technology, 2009.<br>Committee Co-Chair: Conrad, Edward; Committee Co-Chair: First, Phillip; Committee Member: Carter, Brent; Committee Member: de Heer, Walter; Committee Member: Zangwill, Andrew. Part of the SMARTech Electronic Thesis and Dissertation Collection.

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18

Long, Ethan Schuyler. "The Role of Temperature in Testing Deep Submicron CMOS ASICs." PDXScholar, 2003. https://pdxscholar.library.pdx.edu/open_access_etds/34.

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Among the many efforts to improve the IC test process are tests that attempt to differentiate between healthy and defective or low reliability ICs by manipulating the operating conditions of the IC being tested. This thesis attempts to improve the common understanding of multiple and targeted temperature testing by evaluating work published on the subject to date and by presenting previously unpublished empirical observations. The empirical observations are made from SCAN and LBIST based MinVDD measurements, Static IDD measurements, as well as parametric measurements of transistor characterist

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19

Vakili-Amini, Babak. "A Mixed-Signal Low-Noise Sigma-Delta Interface IC for Integrated Sub-Micro-Gravity Capacitive SOI Accelerometers." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/10437.

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This dissertation presents the design and development of a mixed-signal low noise second-order integrated circuit (IC) for the open-loop and closed-loop operation of integrated capacitive micro- and nano-gravity accelerometers. The micromechanical accelerometers are fabricated in thick (less than 100 m) silicon-on-insulator (SOI) substrates. The IC provides the 1-bit digital output stream and has the versatility of interfacing sensors with different sensitivities while maintaining minimum power consumption (less than 5 mW) and maximum dynamic range (90 dB). A fully-differential sampled-data

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20

Sarivisetti, Gayathri. "Design and Optimization of Components in a 45nm CMOS Phase Locked Loop." Thesis, University of North Texas, 2006. https://digital.library.unt.edu/ark:/67531/metadc5397/.

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A novel scheme of optimizing the individual components of a phase locked loop (PLL) which is used for stable clock generation and synchronization of signals is considered in this work. Verilog-A is used for the high level system design of the main components of the PLL, followed by the individual component wise optimization. The design of experiments (DOE) approach to optimize the analog, 45nm voltage controlled oscillator (VCO) is presented. Also a mixed signal analysis using the analog and digital Verilog behavior of components is studied. Overall a high level system design of a PLL, a syste

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21

Park, Yunseo. "Direct Conversion RF Front-End Implementation for Ultra-Wideband (UWB) and GSM/WCDMA Dual-Band Applications in Silicon-Based Technologies." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7563.

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This dissertation focuses on wideband circuit design and implementation issues up to 10GHz based on the direct conversion architecture in the CMOS and SiGe BiCMOS technologies. The dissertation consists of two parts: One, implementation of a RF front-end receiver for an ultra-wideband system and, two, implementation of a local oscillation (LO) signal for a GSM/WCDMA multiband application. For emerging ultra-wideband (UWB) applications, the key active components in the RF front-end receiver were designed and implemented in 0.18um SiGe BiCMOS process. The design of LNA, which is the critical cir

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22

Ukirde, Vaishali. "Trapping of hydrogen in Hf-based high κ dielectric thin films for advanced CMOS applications". Thesis, University of North Texas, 2007. https://digital.library.unt.edu/ark:/67531/metadc5114/.

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In recent years, advanced high κ gate dielectrics are under serious consideration to replace SiO2 and SiON in semiconductor industry. Hafnium-based dielectrics such as hafnium oxides, oxynitrides and Hf-based silicates/nitrided silicates are emerging as some of the most promising alternatives to SiO2/SiON gate dielectrics in complementary metal oxide semiconductor (CMOS) devices. Extensive efforts have been taken to understand the effects of hydrogen impurities in semiconductors and its behavior such as incorporation, diffusion, trapping and release with the aim of controlling and using it to

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23

Liu, Yidong. "CMOS RF cituits sic] variability and reliability resilient design, modeling, and simulation." Doctoral diss., University of Central Florida, 2011. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/4969.

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Simulation of different aging rate also shows that the sensitivity of LNA is further reduced with the accelerated aging of the biasing circuit. Thus, for majority RF transceiver circuits, the adaptive body biasing scheme provides overall performance resilience to the device reliability induced degradation. Also the tuning ability designed in RF PA and LNA provides the circuit post-process calibration capability.; The work presents a novel voltage biasing design that helps the CMOS RF circuits resilient to variability and reliability. The biasing scheme provides resilience through the threshold

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24

Srirattana, Nuttapong. "High-Efficiency Linear RF Power Amplifiers Development." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/6899.

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Next generation mobile communication systems require the use of linear RF power amplifier for higher data transmission rates. However, linear RF power amplifiers are inherently inefficient and usually require additional circuits or further system adjustments for better efficiency. This dissertation focuses on the development of new efficiency enhancement schemes for linear RF power amplifiers. The multistage Doherty amplifier technique is proposed to improve the performance of linear RF power amplifiers operated in a low power level. This technique advances the original Doherty amplifier sche

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25

Wu, Ting. "Design of terabits/s CMOS crossbar switch chip /." View Abstract or Full-Text, 2003. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202003%20WU.

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Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2003.<br>Includes bibliographical references (leaves 100-105). Also available in electronic version. Access restricted to campus users.

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26

Jha, Nand Kishore. "Design of a complementary silicon-germanium variable gain amplifier." Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/24614.

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27

Venkataraman, Sunitha. "Systematic Analysis of the Small-Signal and Broadband Noise Performance of Highly Scaled Silicon-Based Field-Effect Transistors." Diss., Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/16232.

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The objective of this work is to provide a comprehensive analysis of the small-signal and broadband noise performance of highly scaled silicon-based field-effect transistors (FETs), and develop high-frequency noise models for robust radio frequency (RF) circuit design. An analytical RF noise model is developed and implemented for scaled Si-CMOS devices, using a direct extraction procedure based on the linear two-port noise theory. This research also focuses on investigating the applicability of modern CMOS technologies for extreme environment electronics. A thorough analysis of the DC, small-

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28

Song, Shiunn Luen Steven 1960. "Characterization and design of the complementary JFET LAMBDA-DIODE SRAM." Thesis, The University of Arizona, 1988. http://hdl.handle.net/10150/276882.

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The LAMBDA-DIODE was invented in integrated-circuit form in 1974. There was a proposal about this device's application in memory circuits at that time. This thesis is to evaluate the circuit performance of the COMPLEMENTARY JFET LAMBDA-DIODE SRAM. It investigates the speed, power consumption and chip area of this circuit compared with the JFET CROSS COUPLED SRAM by using SPICE and breadboard simulation techniques. The results show positive signs of the Λ-DIODE's feasibility for use in VLSI static memory circuits from the chip area aspect if the parasitic capacitance of the JFET device could be

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29

Westerhoff, Kevin M. (Kevin Matthew) 1978. "Construction based design." Thesis, Massachusetts Institute of Technology, 2002. http://hdl.handle.net/1721.1/84827.

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30

Xie, Xiaoling. "Communications in construction design." Thesis, Loughborough University, 2002. https://dspace.lboro.ac.uk/2134/7571.

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Construction design has become an increasingly complex synthesis activity for which effective solutions depend upon co-operative participation by a number of people. Thus communication, including the integration of specialised knowledge and negotiation of differences between team members, is a vital process for collaborative design. A questionnaire survey was initially conducted to investigate communication issues and problems, which had been highlighted from a review of the literature, in current construction design. The results confirmed that communication among the different construction te

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31

North-Bates, Susan T. "The influence of complementary practices and spirituality on British design, 1930-2005." Thesis, Sheffield Hallam University, 2007. http://shura.shu.ac.uk/20298/.

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This thesis investigates the nature and role of spiritually-influenced approaches to design in Britain in the period 1930-2005. The role of spiritual factors in design is considered as a complement to the predominance of the Modernist rationalist-functionalist discourse prevalent in much twentieth century design history writing and theories of design. Non-rational and spiritual facets of Modernism in this period are also examined. The influence of 'alternative' lifestyles, the New Age movement, ecology, holism, complementary and alternative medical practices, and spirituality on design is pres

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32

Correll, Jeffrey. "The design and implementation of an 8 bit CMOS microprocessor /." Online version of thesis, 1992. http://hdl.handle.net/1850/11649.

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33

Soto, Leticia S. M. Massachusetts Institute of Technology. "Construction design as a process for flow : applying lean principles to construction design." Thesis, Massachusetts Institute of Technology, 2007. http://hdl.handle.net/1721.1/42995.

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Thesis (S.M.)--Massachusetts Institute of Technology, System Design and Management Program, 2007.<br>Includes bibliographical references (p. 108-111).<br>Delays and cost overruns are the rule rather than the exception in the construction industry. Design changes due to lack of constructability late in the construction phase generating costly ripple effect which create delay and disruption throughout the entire organization, are the largest contributors to the stated rule. In the building construction industry, of increased competitiveness, demand from many companies continued effort to develop

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34

Yuan, Fangfeng. "Construction and characterization of a full-length complementary DNA infectious clone of emerging porcine Senecavirus A." Thesis, Kansas State University, 2017. http://hdl.handle.net/2097/35511.

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Master of Science<br>Department of Diagnostic Medicine/Pathobiology<br>Ying Fang<br>Seneca Valley Virus (SVV) causes vesicular disease in pigs. Vesicular lesions on the snout and coronary band of hoof mostly resemble lesions caused by Foot-and-Mouth Disease Virus (FMDV), which may lead to the foreign animal disease investigation. In 2015, Brazil experienced major outbreaks of SVV; then in July, sporadic cases of SVV were reported in United States and became a concern in swine industry. A reverse-genetic system serves as a major tool to study pathogenesis of the virus. In our study, a full-leng

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35

Kwon, Ohsang. "On high performance multiplier design using dynamic CMOS circuits /." Full text (PDF) from UMI/Dissertation Abstracts International, 2000. http://wwwlib.umi.com/cr/utexas/fullcit?p3004310.

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36

Li, Xiaoyong. "Low noise design techniques for radio frequency integrated circuits /." Thesis, Connect to this title online; UW restricted, 2004. http://hdl.handle.net/1773/6013.

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37

Kanitkar, Hrishikesh. "Subthreshold circuits : design, implementation and application /." Online version of thesis, 2009. http://hdl.handle.net/1850/8926.

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38

Sayre, Edward P. "The design, fabrication, and test of a CMOS operational amplifier /." Online version of thesis, 1990. http://hdl.handle.net/1850/11226.

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39

McMahon, Terry E. (Terry Edwin) 1963. "Design, fabrication and characterization of complementary heterojunction field effect transistors." Thesis, 1994. http://hdl.handle.net/1957/34635.

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Complementary delta-doped AlGaAs/GaAs Heterojunction Field Effect Transistor (CHFET) devices and circuits were fabricated using MBE and a 2�� non-planar gate recess process. Several schemes were used in an attempt to improve the performance of the p-channel HFETs. These included delta-doping, carbon-doping and dipole-doping. Circuits and individual n- and p- channel devices were fabricated on a stacked delta-doped complementary structure. The circuits failed to perform due to complications with adjusting the threshold voltage. However, Individual devices were successfully characterized, p-chan

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40

Dang, Yen. "Design, fabrication and characterization of a complementary GaAs MODFET structure." Thesis, 1993. http://hdl.handle.net/1957/35639.

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41

Yoo, Byungwook 1975. "New platforms for electronic devices: n-channel organic field-effect transistors, complementary circuits, and nanowire transistors." Thesis, 2007. http://hdl.handle.net/2152/3165.

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This work focused on the fabrication and electrical characterization of electronic devices and the applications include the n-channel organic field-effect transistors (OFETs), organic complementary circuits, and the germanium nanowire transistors. In organic devices, carbonyl-functionalized [alpha],[omega]-diperfluorohexyl quaterthiophenes (DFHCO-4T) and N,N' --bis(n-octyl)-dicyanoperylene-3,4:9,10-bis(dicarboximide) (PDI-8CN2) are used as n-type semiconductors. The effect of dielectric/electrode surface treatment on the response of bottom-contact devices was also examined to maximize the de

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42

Hui, Henry. "Design of a True-Q Flip Flop." Thesis, 1994. http://hdl.handle.net/1957/35209.

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A CMOS implementation of a True-Q Flip Flop is presented. It can perform either as an asynchronous storage element in micropipelines or a part of the synchronizer. It is capable of double-edge triggering which latches data at both the rising and the trailing edges. It is also free of the metastability state problem. Some analog and digital circuits are incorporated with a true double-edge triggered Flip Flop (DETFF) making it a True-Q Flip Flop. A True-Q Flip Flop outputs an acknowledge signal only after the Q and NQ are stabilized. Therefore, if the proceeding stages utilize this acknowledge

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43

Fiez, Theresa S. "Design of CMOS switched-current filters." Thesis, 1990. http://hdl.handle.net/1957/37183.

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The design and implementation of Switched-Current (SI) ladder filters is described. SI filters require only a standard digital CMOS process and the power supply voltage requirement is low. SI circuits also can be potentially operated at higher frequencies than Switched-Capacitor (SC) filters due to the low-impedance wideband nodes of the current mirrors. A simple method has been developed to design SI ladder and biquadratic fllters with maximum dynamic range that leverages the well-established design methodologies of SC filters. A standard digital 2-micron n-well CMOS process has been used to

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44

Shrivastava, Manu B. "Comparison and analysis of current-mode logic circuits with differential and static CMOS." Thesis, 1994. http://hdl.handle.net/1957/36770.

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This thesis describes the analysis and comparison of Folded Source-Coupled Logic (FSCL) with standard static CMOS, cascode voltage-switch logic and differential split-level logic gates. The advantages of FSCL are low switching noise and high operating speed. The effect of voltage and device scaling on these topologies is evaluated in terms of average delay, power dissipation at maximum frequency, power-delay-product and current spike noise. Several two-summand adders are designed and simulated using MOSIS 1-μm CMOS process parameters and evaluations are performed in terms of area, delay, noise

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45

"Design of CMOS digital controlled oscillator (DCO)." 1998. http://library.cuhk.edu.hk/record=b5889586.

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by Cheuk-Him, To.<br>Thesis (M.Phil.)--Chinese University of Hong Kong, 1998.<br>Includes bibliographical references.<br>Abstract also in Chinese.<br>ACKNOWLEDGMENT --- p.I<br>ABSTRACT (ENGLISH) --- p.II<br>ABSTRACT (CHINESE) --- p.III<br>CONTENTS --- p.IV<br>TABLE OF FIGURES --- p.VI<br>Chapter CHAPTER 1 --- INTRODUCTION --- p.1-1<br>Chapter 1.1 --- Introduction --- p.1-1<br>Chapter 1.2 --- Different types of DCO --- p.1-2<br>Chapter 1.2.1 --- Divided by N counter --- p.1-2<br>Chapter 1.2.2 --- Increment-decrement counter --- p.1-2<br>Chapter 1.2.3 --- Controlled delay ring oscillat

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46

"Design and modelling of CMOS operational amplifiers." 1998. http://library.cuhk.edu.hk/record=b5889676.

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by Chung-Yuk Or.<br>Thesis (M.Phil.)--Chinese University of Hong Kong, 1998.<br>Includes bibliographical references (leaves 95-[98]).<br>Abstract also in Chinese.<br>Chapter 1 --- Introduction --- p.1<br>Chapter 2 --- Fully Differential CMOS Operational Amplifier Design --- p.4<br>Chapter 2.1 --- Wide-Swing Current Mirror --- p.5<br>Chapter 2.2 --- Wide-Swing Biasing Network --- p.8<br>Chapter 2.3 --- Fully differential folded-cascode operational amplifier --- p.13<br>Chapter 2.3.1 --- Small-Signal Analysis --- p.16<br>Chapter 2.4 --- Gain-boost technique --- p.18<br>Chapter 2.4.1 --- F

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47

Lo, Ivy Iun. "A wideband CMOS low-noise amplifier for UHF applications." Thesis, 2005. http://hdl.handle.net/10125/20547.

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48

"Low voltage and low power circuit techniques for CMOS RF frequency synthesizer application." 2013. http://library.cuhk.edu.hk/record=b5549762.

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在過去的幾十年中，無線通信已經歷了顯著的發展，並成為日常生活中必不可少的一部分。隨著對可移動便攜式電子設備的需求不斷增加，功耗已经成為射頻前端電路設計的一個最關鍵參數。在便攜式無線消費類電子中，頻率綜合器在收发机设计中提供本地振盪器（LO），它又是一個高功耗的子系統之一。降低頻率綜合器的功耗將會直接影响電池的使用時間。<br>為了驗證進來新型的低功耗技术，本文基於低成本的0.18微米三阱CMOS工藝，設計並實現了三個不同的電路模塊和一個頻率綜合器系統。第一個設計是一個低壓正交壓控振盪器(QVCO)和除肆分頻器的電流復用電路。在沒有損耗電壓餘量的情況下，兩個高頻模塊通過電流復用的方式，從而降低了功耗。測試結果顯示當電源電壓為1.3V ，電流消耗電流為2.7毫安。在2.2 GHz載波附近1MHz頻偏位置上的相位噪聲為 -114 dBc/Hz。第二個設計是應用於SDR的變壓器和電流復用的壓控振盪器/分頻器的電路。該電路通過調整偏置電壓，僅用一個分頻器就可以實現可變分頻比（2，3，…,9）的功能。實驗結果表明，分頻器的輸出頻率範圍從0.58至3.11 GHz，在5.72 GHz載波附近1MHz頻偏位置上的相位噪聲為-112.5 dBc / Hz，電源電壓為1.8V時，電流為4.7mA。第三個設計是應用於UWB的變壓器和電流復用的QVCO / SSBM電路。這個全新的結構電路面積為0.8平方

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"CMOS dual-modulus prescaler design for RF frequency synthesizer applications." 2005. http://library.cuhk.edu.hk/record=b5892418.

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Ng Chong Chon.<br>Thesis (M.Phil.)--Chinese University of Hong Kong, 2005.<br>Includes bibliographical references (leaves 100-103).<br>Abstract in English and Chinese.<br>摘要 --- p.iii<br>Acknowledgments --- p.iv<br>Contents --- p.vi<br>List of Figures --- p.ix<br>List of Tables --- p.xii<br>Chapter Chapter 1 --- Introduction --- p.1<br>Chapter 1.1 --- Motivation --- p.1<br>Chapter 1.2 --- Thesis Organization --- p.4<br>Chapter Chapter 2 --- DMP Architecture --- p.6<br>Chapter 2.1 --- Conventional DMP --- p.6<br>Chapter 2.1.1 --- Operating Principle --- p.7<br>Chapter 2.1.2 --- Disad

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"Novel channel materials for Si based MOS devices: Ge, strained Si and hybrid crystal orientations." Thesis, 2007. http://hdl.handle.net/2152/3107.

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