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Artykuły w czasopismach na temat „CONVENTIONAL CLOCK GATING”

Autor: Grafiati

Data publikacji: 11 września 2023

Data aktualizacji: 31 lipca 2025

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1

Titus, Joby. "LEAKAGE AND SWITCHING POWER OPTIMIZATION IN CMOS PROCESSORS USING LOW-POWER RECONFIGURABLE MATCH TABLE-BASED CLOCK GATING CONTROLLERS." ICTACT Journal on Microelectronics 11, no. 1 (2025): 2011–18. https://doi.org/10.21917/ijme.2025.0342.

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Modern CMOS processors face a significant challenge in power consumption, primarily due to switching and leakage power. With rising demands for energy-efficient systems, especially in mobile and IoT devices, managing dynamic and static power has become essential. Conventional clock gating techniques lack adaptability to workload variability, leading to inefficient power savings. Fixed gating schemes either over-constrain performance or underperform in power savings. This work proposes a Low-Power Reconfigurable Match Table (RMT)- based Clock Controller that dynamically adjusts clock gating gra

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Jyothula, Sudhakar. "Low power aware pulse triggered flip flops using modified clock gating approaches." World Journal of Engineering 15, no. 6 (2018): 792–803. http://dx.doi.org/10.1108/wje-09-2017-0309.

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PurposeThe purpose of this paper is to design a low power clock gating technique using Galeor approach by assimilated with replica path pulse triggered flip flop (RP-PTFF).Design/methodology/approachIn the present scenario, the inclination of battery for portable devices has been increasing tremendously. Therefore, battery life has become an essential element for portable devices. To increase the battery life of portable devices such as communication devices, these have to be made with low power requirements. Hence, power consumption is one of the main issues in CMOS design. To reap a low-powe

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3

Jung, Jun Mo, and Jong-Wha Chong. "A Low Power FIR Filter Design for Image Processing." VLSI Design 12, no. 3 (2001): 391–97. http://dx.doi.org/10.1155/2001/54974.

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In this paper, a new low power design method of the FIR filter for image processing is proposed. Because the correlation between adjacent pixels is very high in image data, the clock gating technique can be a good candidate for low power strategy. However, the conventional clock gating strategy that is applied independently to every flip-flop of the filter give rise to too much additional area overhead and couldn't get a good result in the power reduction. In our method, each tap register, which is used to delay the input data in the filter, is partitioned into two sub-registers according to t

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4

Varsha, K. Pavithra, and Dr V. Sumalatha. "Design of Power Optimised Truncated Approximate Booth Multiplier." International Journal for Research in Applied Science and Engineering Technology 12, no. 11 (2024): 948–55. http://dx.doi.org/10.22214/ijraset.2024.65245.

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Abstract: In digital signal processing and arithmetic circuits, Booth multipliers are widely used for efficient multiplication of signed numbers. However, conventional Booth multipliers consume significant power due to their full precision operation. This paper explores efficient approximation techniques for Booth multipliers enhanced with flip-flop clock gating to reduce power consumption. Booth multipliers traditionally consume significant power due to their full precision operations. In this approach it mainly focuses on truncating less significant bits in the Booth encoding to lower comput

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5

Sam, D. S. Shylu, P. Sam Paul, Joel Samuel, and Vimukth John. "A New Embedded Clock Gating Technique in 8- bit Synchronous Counter with Reduced Switching Activity for Clock Divider Circuit." WSEAS TRANSACTIONS ON CIRCUITS AND SYSTEMS 22 (December 31, 2023): 195–205. http://dx.doi.org/10.37394/23201.2023.22.22.

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Counters play an inevitable role in many VLSI circuits such as timers, frequency dividers, memories, and ADC/DAC. Integrating the timing discriminator, Pulse Swallow, and Correlated double sampling are various approaches used in counters for low power consumption. The main objective was to minimize the power consumption and device count. In this work, a new embedded clock gating technique is used in an 8-bit counter to reduce the switching activity. A clock gating circuit and clock buffer network pattern are used in the proposed algorithm to reduce the power consumption of synchronous counters

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6

Jeong, Seoyeong, Junhyuk Jang, Kichang Lee, and Jaemyung Lim. "P‐249: Late‐News Poster: A Low Power Digital Logic Structure for High Resolution and High Frame Rate OLEDoS Micro Displays." SID Symposium Digest of Technical Papers 55, no. 1 (2024): 1705–8. http://dx.doi.org/10.1002/sdtp.17898.

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This paper proposes a digital logic circuit in the source driver for OLEDoS micro display which uses a novel data signal tree structure with clock gating logic to reduce power consumption. The proposed structure for 4096×4096 (4K) 144 Hz micro displays was verified using a CMOS 110 nm process. The power consumption was reduced by 69.6 % compared to the conventional data signal tree structure, enabling a low‐power design.

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7

Ramalinga Reddy Kotapati. "Advanced Clock Tree Synthesis Optimization: A Multi-Source Approach to Minimizing Skew and Power in Sub-7nm ASIC Designs." International Journal of Scientific Research in Computer Science, Engineering and Information Technology 10, no. 6 (2024): 2275–83. https://doi.org/10.32628/cseit2410612440.

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Clock tree synthesis (CTS) optimization remains a critical challenge in advanced node ASIC physical design, particularly as semiconductor technologies continue to scale down. This article presents a comprehensive methodology for optimizing multi-source clock distribution networks while addressing power consumption and timing accuracy concerns. The article introduces an integrated approach that combines functional clock gating strategies with sophisticated skew management techniques to achieve optimal performance in high-frequency designs. The proposed framework incorporates latch-based timing

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8

Venkata Sudhakar, Chowdam, Suresh Babu Potladurty, and Prasad Reddy Karipireddy. "Design and evaluation of clock-gating-based approximate multiplier for error-tolerant applications." International Journal of Reconfigurable and Embedded Systems (IJRES) 14, no. 2 (2025): 398. https://doi.org/10.11591/ijres.v14.i2.pp398-411.

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<p>The multiplier is an essential component in real-time applications. Even though approximation arithmetic affects output accuracy in multipliers, it offers a realistic avenue to constructing power area and speed-efficient digital circuits. The approximation computing technique is commonly used in error-tolerant applications such as signal, image, and video processing. In this paper, approximate multipliers (AMs) are designed using both conventional and approximate half adders (A-HA) and full adders (A-FA), which are strategically placed to add partial products at the most significant b

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9

Laskar, Nivedita, Suman Debnath, Alak Majumder, and Bidyut Kumar Bhattacharyya. "A New Current Profile Determination Methodology Incorporating Gating Logic to Minimize the Noise of CPU Chip by 40%." Journal of Circuits, Systems and Computers 27, no. 03 (2017): 1850049. http://dx.doi.org/10.1142/s0218126618500494.

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The present methodology of clock distribution inside high-performance central processing unit chip offers current to ramp linearly or exponentially when the chip comes out of sleep mode to active mode or when the clock starts driving a chip to operate. This linear current ramp leads to power and ground noise due to [Formula: see text]d[Formula: see text]/d[Formula: see text]. In this paper, we have shown that for a given power delivery network (PDN), it is possible to generate a current profile (current versus time), by controlling the current on all the complementary metal oxide semiconductor

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10

Touil, Lamjed, Abdelaziz Hamdi, Ismail Gassoumi, and Abdellatif Mtibaa. "Design of Low-Power Structural FIR Filter Using Data-Driven Clock Gating and Multibit Flip-Flops." Journal of Electrical and Computer Engineering 2020 (July 10, 2020): 1–9. http://dx.doi.org/10.1155/2020/8108591.

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Optimization for power is one of the most important design objectives in modern digital signal processing (DSP) applications. The digital finite duration impulse response (FIR) filter is considered to be one of the most essential components of DSP, and consequently a number of extensive works had been carried out by researchers on the power optimization of the filters. Data-driven clock gating (DDCG) and multibit flip-flops (MBFFs) are two low-power design methods that are used and often treated separately. The combination of these methods into a single algorithm enables further power saving o

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11

Prema, S., N. Karthikeyan, and S. Karthik. "Ultra-Low Power and High Sensitivity of Joint Clock Gating Based Dual Feedback Edge Triggered Flip Flop for Biomedical Imaging Applications." Journal of Medical Imaging and Health Informatics 11, no. 12 (2021): 3215–22. http://dx.doi.org/10.1166/jmihi.2021.3919.

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To adapt to varied working situations, the latest biomedical imaging applications require low energy consumption, high performance, and extensive energy-performance scalability. State-of-the-art electronics with higher sensitivity, higher counting rate, and finer time resolution are required to create higher precision, higher temporal resolution, and maximum contrast biomedical images. In recent days, the system’s power consumption is important critically in modern VLSI circuits particularly for the low power application. In order to decrease the power, a power optimization technique must be u

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12

Shashidhar, A., and B. Ramesh K. "Design of Power Efficient and High Temperature Operational Priority Encoder." Journal of Advancement in Communication System 7, no. 3 (2024): 9–16. https://doi.org/10.5281/zenodo.12718734.

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<em>This research paper proposes a novel approach to designing a power-efficient and high-temperature operational priority encoder using Silicon Carbide (SiC) JFETs (Junction Field-Effect Transistors) and Carbon Nanotube Field-Effect Transistors (CNFETs).[1] The proposed priority encoder leverages the superior thermal stability and low power consumption characteristics of SiC JFETs and CNFETs to achieve reliable performance in extreme environments. </em><em>The proposed priority encoder architecture is meticulously designed to harness the inherent characteristics of SiC JNFET and CNTFETs, expl

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13

Thanh, Toi Le, Lac Truong Tri, and Trang Hoang. "Low power circuit design using NCL based asynchronous method." Indonesian Journal of Electrical Engineering and Computer Science 22, no. 3 (2021): 1284–94. https://doi.org/10.11591/ijeecs.v22.i3.pp1284-1294.

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The null convention logic (NCL) based circuit design methodology eliminates the problems related to noise, clock tree, electromagnetic interference and also reduces significant power consumption. In this paper, we would like to demonstrate the advantage of low power consumption of the NCL based asynchronous circuit design on a large design scale, thus we used the advanced encryption standard (AES) encryption design as an illustrative example. In addition, we also proposed two pipelined AES encryption models using the synchronous circuit design technique and the asynchronous circuit design tech

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14

R., Manjith, and Muthukumari C. "Dynamic Power Reduction in Sequential Circuits Using Look Ahead Clock Gating Technique." October 3, 2015. https://doi.org/10.5281/zenodo.1109920.

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In this paper, a novel Linear Feedback Shift Register (LFSR) with Look Ahead Clock Gating (LACG) technique is presented to reduce the power consumption in modern processors and System-on-Chip. Clock gating is a predominant technique used to reduce unwanted switching of clock signals. Several clock gating techniques to reduce the dynamic power have been developed, of which LACG is predominant. LACG computes the clock enabling signals of each flip-flop (FF) one cycle ahead of time, based on the present cycle data of the flip-flops on which it depends. It overcomes the timing problems in the exis

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15

Bhukya, Naveen Kumar, and V. Sudheer Raja Dr. "Power Reduction of Domino Logic with clock gating using 16nm CMOS Technology." September 12, 2022. https://doi.org/10.5281/zenodo.7072348.

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In this paper, a new technique of power reduction in CMOS domino logic is proposed. The proposed technique uses clock gating as well as output hold circuitry. Clock is passed to the domino logic only during the active state of the circuit. During standby mode, clock is bypassed while the state of the circuit is retained. A 2:1 multiplexer is used for clock gating and for retaining the state of the circuit. Simulation results are being carried out in a 2-input NAND gate, 2-input nor gate and 1-bit conventional full adder cell in 16nm CMOS technology. The power of the proposed circuit is reduced

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16

Jianping, Hu, and Sheng Xiaolei. "A Single-Phase Register File with Complementary Pass-Transistor Adiabatic Logic." February 21, 2010. https://doi.org/10.5281/zenodo.1057369.

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This paper introduces an adiabatic register file based on two-phase CPAL (Complementary Pass-Transistor Adiabatic Logic circuits) with power-gating scheme, which can operate on a single-phase power clock. A 32×32 single-phase adiabatic register file with power-gating scheme has been implemented with TSMC 0.18μm CMOS technology. All the circuits except for the storage cells employ two-phase CPAL circuits, and the storage cell is based on the conventional memory one. The two-phase non-overlap power-clock generator with power-gating scheme is used to supply the proposed adiabatic register file. F

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17

S., Dhanasekar, Govindaraj V., Malin Bruntha P., and Jubair Ahmed L. "A power-efficient pipeline based clock gating FIFO for a dual ported memory array." September 1, 2023. https://doi.org/10.5281/zenodo.8317717.

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A FIFO is a special type of buffer that controls the data flow between the sender and receiver. It is used to monitor the serial data flow and to avoid mismatch conditions. In general, the dual-ported memory cell array suffers from dynamic power dissipation. In this research article, a 128 x 128-bit Synchronous First-In-First-Out (FIFO) buffer is designed for dual-ported memory cell array with pipeline architecture using clock gating technique, which reduces power dissipation significantly. The FIFO-based dual-ported memory cell array will store a large amount of data and minimize the clock sk

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18

Kannan, L. Mohana, and Deepa D. "Low power and area efficient design of fir filter using enhanced clock gating technique." Journal of Engineering Research 9 (October 27, 2021). http://dx.doi.org/10.36909/jer.11307.

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The main aim of this approach is to improve the design model of filters for optimal circuit design. The objective of this proposed method is to improve the performance of VLSI circuit like area, power, and delay. In recent days, the filters are most applicable designs in DSP, medical diagnosis and arithmetic computations. In Digital Signal Processing and communication applications, the FIR filter plays an important role. The Finite Impulse Response is designed with number of adders, multipliers, subtraction units, transfer functions and delay elements. The VLSI circuits are applied in various

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19

Mounir, Zid, Pistritto Carlo, Tourki Rached, and Scandurra Alberto. "A NEW N-FOLD FLIP-FLOP WITH OUTPUT ENABLE." June 30, 2013. https://doi.org/10.5121/ijesa.2013.3202.

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With the evolution of the semiconductor industry and the continuous growing demands for high performance VLSI circuit, the aggressive scaling in feature size and high integration density along with the high operating frequencies make power consumption and digital noise in modern analog and digital devices one of the top concerns of Very Large Scale Integration (VLSI) circuit design. In this paper we delve into the design of n-fold flip-flops with output enable. A new n-fold flip-flop exploiting the clock gating technique for both outputs enabling and power saving is presented. To evaluate its

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20

Mounir, Zid, Pistritto Carlo, Tourki Rached, and Scandurra Alberto. "A New N-Fold Flip-Flop with Output Enable." June 30, 2013. https://doi.org/10.5281/zenodo.3466976.

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With the evolution of the semiconductor industry and the continuous growing demands for high performance VLSI circuit, the aggressive scaling in feature size and high integration density along with the high operating frequencies make power consumption and digital noise in modern analog and digital devices one of the top concerns of Very Large Scale Integration (VLSI) circuit design. In this paper we delve into the design of n-fold flip-flops with output enable. A new n-fold flip-flop exploiting the clock gating technique for both outputs enabling and power saving is presented. To evaluate its

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21

Jayanthi, VE, Senthil Pitchai, and M. Smitha. "Design a Hybrid FPGA Architecture for Visible Digital Image Watermarking in Spatial and Frequency Domain." Journal of Circuits, Systems and Computers, July 23, 2021, 2250020. http://dx.doi.org/10.1142/s0218126622500207.

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Hybrid field programmable gate array (FPGA) implementation is proposed to improve the performance of visible image watermarking systems. The visible watermarking process is implemented as pixel by pixel operation under a spatial domain or vector operation in the frequency domain. The proposed approach is mainly designed for watermarking the images taken from digital cameras of various sizes. The padding technique is used for unequal sizes of the watermark image and original host image. The architecture data path consists of eight and six stages of pipeline capable of watermarking on the pixel-

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