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Artykuły w czasopismach na temat "Data layout and Computation Reordering"
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Masselos, K., P. Merakos, T. Stouraitis, and C. E. Goutis. "Computation Reordering: A Novel Transformation for Low Power DSP Synthesis." VLSI Design 10, no. 2 (1999): 177–202. http://dx.doi.org/10.1155/1999/16415.
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A novel architectural transformation for low power synthesis of inner product computational structures is presented. The proposed transformation reorders the sequence of evaluation of the multiply-accumulate operations that form the inner products. Information related to both coefficients, which are statically determined, and data, which are dynamic, is used to drive the reordering of computation. The reordering of computation reduces the switching activity at the inputs of the computational units but inside them as well leading to power consumption reduction. Different classes of algorithms requiring inner product computation are identified and the problem of computation reordering is formulated for each of them. The target architecture to which the proposed transformation applies is based on a power optimal memory organization and is described in detail. Experimental results for several DSP algorithms show that the proposed transformation leads to significant savings in net switching activity and thus in power consumption.
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Shen, Zhao-Li, Yu-Tong Liu, Bruno Carpentieri, Chun Wen, and Jian-Jun Wang. "Recursive reordering and elimination method for efficient computation of PageRank problems." AIMS Mathematics 8, no. 10 (2023): 25104–30. http://dx.doi.org/10.3934/math.20231282.
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<abstract><p>The PageRank model is widely utilized for analyzing a variety of scientific issues beyond its original application in modeling web search engines. In recent years, considerable research effort has focused on developing high-performance iterative methods to solve this model, particularly when the dimension is exceedingly large. However, due to the ever-increasing extent and size of data networks in various applications, the computational requirements of the PageRank model continue to grow. This has led to the development of new techniques that aim to reduce the computational complexity required for the solution. In this paper, we present a recursive 5-type lumping algorithm combined with a two-stage elimination strategy that leverage characteristics about the nonzero structure of the underlying network and the nonzero values of the PageRank coefficient matrix. This method reduces the initial PageRank problem to the solution of a remarkably smaller and sparser linear system. As a result, it leads to significant cost reductions for computing PageRank solutions, particularly in scenarios involving large and/or multiple damping factors. Numerical experiments conducted on over 50 real-world networks demonstrate that the proposed methods can effectively exploit characteristics of PageRank problems for efficient computations.</p></abstract>
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Rodrigues, Thiago Nascimento, Maria Claudia Silva Boeres, and Lucia Catabriga. "Parallel Implementations of RCM Algorithm for Bandwidth Reduction of Sparse Matrices." TEMA (São Carlos) 18, no. 3 (2018): 449. http://dx.doi.org/10.5540/tema.2017.018.03.449.
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The Reverse Cuthill-McKee (RCM) algorithm is a well-known heuristicfor reordering sparse matrices. It is typically used to speed up the computation ofsparse linear systems of equations. This paper describes two parallel approachesfor the RCM algorithm as well as an optimized version of each one based on someproposed enhancements. The first one exploits a strategy for reducing lazy threads,while the second one makes use of a static bucket array as the main data structureand suppress some steps performed by the original algorithm. These related changesled to outstanding reordering time results and significant bandwidth reductions.The performance of two algorithms is compared with the respective implementationmade available by Boost library. The OpenMP framework is used for supportingthe parallelism and both versions of the algorithm are tested with large sparse andstructural symmetric matrices.
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LIU, YING, and WENYUAN LI. "VISUALIZING MICROARRAY DATA FOR BIOMARKER DISCOVERY BY MATRIX REORDERING AND REPLICATOR DYNAMICS." Journal of Bioinformatics and Computational Biology 06, no. 06 (2008): 1089–113. http://dx.doi.org/10.1142/s0219720008003862.
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In most microarray data sets, there are often multiple sample classes, which are categorized into the normal or diseased type. Traditional feature selection methods consider multiple classes equally without paying attention to the upregulation/downregulation across the normal and diseased classes; while the specific gene selection methods for biomarker discovery particularly consider differential gene expressions across the normal and diseased classes, but ignore the existence of multiple classes. More importantly, there are few visualization algorithms to assist biomarker discovery from microarray data. In this paper, to help users visually analyze microarray data and improve biomarker discovery, we propose to employ matrix reordering techniques that have been developed and used in matrix computation. In particular, we generalized a well-known population genetic algorithm, namely, replicator dynamics, to reorder a microarray data matrix with multiple classes. The new algorithm simultaneously takes into account the global between-class data pattern and local within-class data pattern. Our results showed that our matrix reordering algorithm not only provides a visualization method to effectively analyze microarray data on both genes and samples, but also improves the accuracy of classifying the samples.
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DE STEFANO, CLAUDIO, and ANGELO MARCELLI. "AN EFFICIENT METHOD FOR ONLINE CURSIVE HANDWRITING STROKES REORDERING." International Journal of Pattern Recognition and Artificial Intelligence 18, no. 07 (2004): 1157–71. http://dx.doi.org/10.1142/s0218001404003691.
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In the framework of online cursive handwriting recognition, we present an efficient method for reordering the sequence of strokes composing handwriting in two special cases of interest: the horizontal bar of the character "" and the dot of the character "". The proposed method exploits shape information for selecting the strokes that most likely correspond to the features of interest, and layout and topological information for locating the strokes representing the body of the characters to which the features belong to. The method does not depend on the specific algorithm used for detecting the elementary strokes in which the electronic ink may be decomposed into. The performance of our method, evaluated on a data set of cursive words produced by 50 different writers, has shown a correct reordering of the sequence in more than 85% of the cases. Thus, the proposed method allows obtaining a more stable and invariant description of the electronic ink in terms of elementary stroke sequences, and therefore can be helpfully used as a preprocessing step for both segmentation-based and word-based handwriting recognition systems.
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Mehta, Dinesh P. "CLOTH MEASURE: A Software Tool for Estimating the Memory Requirements of Corner Stitching Data Structures." VLSI Design 7, no. 4 (1998): 425–36. http://dx.doi.org/10.1155/1998/64716.
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In a previous paper [1], we derived formulae for estimating the storage requirements of the Rectangular and L-shaped Corner Stitching data structures [2, 3] for a given layout. These formulae require the computation of quantities called violations, which are geometric properties of the layout. In this paper, we present optimal Θ(n log n) algorithms for computing violations, where n is the number of rectangles in the layout. These algorithms are incorporated into a software tool called CLOTH MEASURE. Experiments conducted with CLOTH MEASURE show that it is a viable tool for estimating the memory requirements of a layout without having to implement the corner stitching data structures, which is a tedious and time-consuming task.
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Hoang, Vinh Quoc, and Yuhua Chen. "Cost-Effective Network Reordering Using FPGA." Sensors 23, no. 2 (2023): 819. http://dx.doi.org/10.3390/s23020819.
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The advancement of complex Internet of Things (IoT) devices in recent years has deepened their dependency on network connectivity, demanding low latency and high throughput. At the same time, expanding operating conditions for these devices have brought challenges that limit the design constraints and accessibility for future hardware or software upgrades. These limitations can result in data loss because of out-of-order packets if the design specification cannot keep up with network demands. In addition, existing network reordering solutions become less applicable due to the drastic changes in the type of network endpoints, as IoT devices typically have less memory and are likely to be power-constrained. One approach to address this problem is reordering packets using reconfigurable hardware to ease computation in other functions. Field Programmable Gate Array (FPGA) devices are ideal candidates for hardware implementations at the network endpoints due to their high performance and flexibility. Moreover, previous research on packet reordering using FPGAs has serious design flaws that can lead to unnecessary packet dropping due to blocking in memory. This research proposes a scalable hardware-focused method for packet reordering that can overcome the flaws from previous work while maintaining minimal resource usage and low time complexity. The design utilizes a pipelined approach to perform sorting in parallel and completes the operation within two clock cycles. FPGA resources are optimized using a two-layer memory management system that consumes minimal on-chip memory and registers. Furthermore, the design is scalable to support multi-flow applications with shared memories in a single FPGA chip.
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Meng, Xiankai, Zhuo Zhang, Jianxin Xue, Fangshu Chen, and Jiahui Wang. "Reliability Analysis for Programs with Redundancy Computation for Soft Errors." Journal of Physics: Conference Series 2522, no. 1 (2023): 012022. http://dx.doi.org/10.1088/1742-6596/2522/1/012022.
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Abstract Soft error is one of the factors which may affect the reliability of computer programs. A common method to alleviate the impact of soft errors is redundancy computation, a classical data flow error detection mechanism. However, a program with redundancy computation may still have some vulnerable spots, which might be caused by the flaw during implementation or the instruction reordering given by compiler optimization. Finding the vulnerable spots of a program with redundancy computation is of great significance to evaluate the capability of the error detection mechanism. There are some conventional methods to analyze the reliability of a program under soft errors, such as the irradiation experiment, fault injection, and modeling analysis. However, the irradiation experiment is expensive, fault injection is very time-consuming, and the existing modeling analysis methods have not considered the error detection mechanism. This paper proposes a novel method of reliability analysis for programs with redundancy computation by analyzing the dynamic instruction sequence. Experimental results show that our approach has fairly high accuracy and a false negative rate of about 0.0545.
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MISHRA, SK. "On accelerating the FFT of Cooley and Tukey." MAUSAM 36, no. 2 (2022): 167–72. http://dx.doi.org/10.54302/mausam.v36i2.1833.
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The efficient Fourier transform (EFT) and FFT algorithms are described and their computational efficiencies with respect to the direct method are discussed. An efficient procedure is proposed for the reordering of data set; the use of EFT algorithm for the initial Fourier transforms and restricting the size of final subsets to not less than 4 is also suggested for saving computation time in the FFT. It is found that on average the FFT with the proposed modifications is more than twice as fast as the original FFT. The amount of overhead operations involved in computer routine, based on the modified FFT is estimated.
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Phetkaew, Thimaporn, Wanchai Rivepiboon, and Boonserm Kijsirikul. "Reordering Adaptive Directed Acyclic Graphs for Multiclass Support Vector Machines." Journal of Advanced Computational Intelligence and Intelligent Informatics 7, no. 3 (2003): 315–21. http://dx.doi.org/10.20965/jaciii.2003.p0315.
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The problem of extending binary support vector machines (SVMs) for multiclass classification is still an ongoing research issue. Ussivakul and Kijsirikul proposed the Adaptive Directed Acyclic Graph (ADAG) approach that provides accuracy comparable to that of the standard algorithm-Max Wins and requires low computation. However, different sequences of nodes in the ADAG may provide different accuracy. In this paper we present a new method for multiclass classification, Reordering ADAG, which is the modification of the original ADAG method. We show examples to exemplify that the margin (or 2/|w| value) between two classes of each binary SVM classifier affects the accuracy of classification, and this margin indicates the magnitude of confusion between the two classes. In this paper, we propose an algorithm to choose an optimal sequence of nodes in the ADAG by considering the |w| values of all classifiers to be used in data classification. We then compare our performance with previous methods including the ADAG and the Max Wins algorithm. Experimental results demonstrate that our method gives higher accuracy. Moreover it runs faster than Max Wins, especially when the number of classes and/or the number of dimensions are relatively large.